ASoC: SOF: amd: add option to use sram for data bin loading
Provide an option to load DSP data bin to ACP SRAM. Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com> Link: https://lore.kernel.org/r/20231020062822.3913760-5-Vijendar.Mukunda@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -21,6 +21,7 @@
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#define FW_BIN 0
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#define FW_DATA_BIN 1
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#define FW_SRAM_DATA_BIN 2
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#define FW_BIN_PTE_OFFSET 0x00
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#define FW_DATA_BIN_PTE_OFFSET 0x08
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@ -49,7 +50,6 @@ int acp_dsp_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_t
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u32 offset, void *src, size_t size)
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{
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struct pci_dev *pci = to_pci_dev(sdev->dev);
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const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
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struct acp_dev_data *adata;
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void *dest;
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u32 dma_size, page_count;
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@ -86,9 +86,18 @@ int acp_dsp_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_t
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adata->is_dram_in_use = true;
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break;
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case SOF_FW_BLK_TYPE_SRAM:
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offset = offset - desc->sram_pte_offset;
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memcpy_to_scratch(sdev, offset, src, size);
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return 0;
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if (!adata->sram_data_buf) {
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adata->sram_data_buf = dma_alloc_coherent(&pci->dev,
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ACP_DEFAULT_SRAM_LENGTH,
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&adata->sram_dma_addr,
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GFP_ATOMIC);
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if (!adata->sram_data_buf)
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return -ENOMEM;
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}
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adata->fw_sram_data_bin_size = size + offset;
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dest = adata->sram_data_buf + offset;
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adata->is_sram_in_use = true;
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break;
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default:
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dev_err(sdev->dev, "bad blk type 0x%x\n", blk_type);
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return -EINVAL;
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@ -123,6 +132,10 @@ static void configure_pte_for_fw_loading(int type, int num_pages, struct acp_dev
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offset = adata->fw_bin_page_count * 8;
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addr = adata->dma_addr;
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break;
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case FW_SRAM_DATA_BIN:
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offset = (adata->fw_bin_page_count + ACP_DRAM_PAGE_COUNT) * 8;
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addr = adata->sram_dma_addr;
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break;
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default:
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dev_err(sdev->dev, "Invalid data type %x\n", type);
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return;
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@ -189,6 +202,22 @@ int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev)
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if (ret < 0)
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dev_err(sdev->dev, "acp dma transfer status: %d\n", ret);
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}
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if (adata->is_sram_in_use) {
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configure_pte_for_fw_loading(FW_SRAM_DATA_BIN, ACP_SRAM_PAGE_COUNT, adata);
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src_addr = ACP_SYSTEM_MEMORY_WINDOW + ACP_DEFAULT_SRAM_LENGTH +
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(page_count * ACP_PAGE_SIZE);
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dest_addr = ACP_SRAM_BASE_ADDRESS;
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ret = configure_and_run_dma(adata, src_addr, dest_addr,
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adata->fw_sram_data_bin_size);
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if (ret < 0) {
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dev_err(sdev->dev, "acp dma configuration failed: %d\n", ret);
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return ret;
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}
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ret = acp_dma_status(adata, 0);
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if (ret < 0)
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dev_err(sdev->dev, "acp dma transfer status: %d\n", ret);
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}
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if (desc->rev > 3) {
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/* Cache Window enable */
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@ -205,6 +234,11 @@ int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev)
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adata->dma_addr);
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adata->data_buf = NULL;
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}
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if (adata->is_sram_in_use) {
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dma_free_coherent(&pci->dev, ACP_DEFAULT_SRAM_LENGTH, adata->sram_data_buf,
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adata->sram_dma_addr);
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adata->sram_data_buf = NULL;
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}
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return ret;
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}
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EXPORT_SYMBOL_NS(acp_dsp_pre_fw_run, SND_SOC_SOF_AMD_COMMON);
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@ -56,7 +56,7 @@
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#define ACP_IRAM_BASE_ADDRESS 0x000000
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#define ACP_DRAM_BASE_ADDRESS 0x01000000
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#define ACP_DRAM_PAGE_COUNT 128
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#define ACP_SRAM_BASE_ADDRESS 0x3806000
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#define ACP_DSP_TO_HOST_IRQ 0x04
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#define ACP_RN_PCI_ID 0x01
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@ -88,6 +88,8 @@
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#define PROBE_STATUS_BIT BIT(31)
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#define ACP_FIRMWARE_SIGNATURE 0x100
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#define ACP_DEFAULT_SRAM_LENGTH 0x00080000
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#define ACP_SRAM_PAGE_COUNT 128
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enum clock_source {
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ACP_CLOCK_96M = 0,
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@ -194,13 +196,18 @@ struct acp_dev_data {
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struct platform_device *dmic_dev;
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unsigned int fw_bin_size;
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unsigned int fw_data_bin_size;
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unsigned int fw_sram_data_bin_size;
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const char *fw_code_bin;
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const char *fw_data_bin;
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const char *fw_sram_data_bin;
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u32 fw_bin_page_count;
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u32 fw_data_bin_page_count;
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dma_addr_t sha_dma_addr;
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u8 *bin_buf;
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dma_addr_t dma_addr;
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u8 *data_buf;
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dma_addr_t sram_dma_addr;
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u8 *sram_data_buf;
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bool signed_fw_image;
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struct dma_descriptor dscr_info[ACP_MAX_DESC];
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struct acp_dsp_stream stream_buf[ACP_MAX_STREAM];
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@ -209,6 +216,7 @@ struct acp_dev_data {
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struct acp_dsp_stream *probe_stream;
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bool enable_fw_debug;
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bool is_dram_in_use;
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bool is_sram_in_use;
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};
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void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes);
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