KVM: x86/pmu: Provide Intel PMU's pmc_is_enabled() as generic x86 code
Move the Intel PMU implementation of pmc_is_enabled() to common x86 code as pmc_is_globally_enabled(), and drop AMD's implementation. AMD PMU currently supports only v1, and thus not PERF_GLOBAL_CONTROL, thus the semantics for AMD are unchanged. And when support for AMD PMU v2 comes along, the common behavior will also Just Work. Signed-off-by: Like Xu <likexu@tencent.com> Co-developed-by: Sean Christopherson <seanjc@google.com> Link: https://lore.kernel.org/r/20230603011058.1038821-6-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
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@ -13,7 +13,6 @@ BUILD_BUG_ON(1)
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* at the call sites.
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*/
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KVM_X86_PMU_OP(hw_event_available)
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KVM_X86_PMU_OP(pmc_is_enabled)
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KVM_X86_PMU_OP(pmc_idx_to_pmc)
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KVM_X86_PMU_OP(rdpmc_ecx_to_pmc)
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KVM_X86_PMU_OP(msr_idx_to_pmc)
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@ -93,11 +93,6 @@ void kvm_pmu_ops_update(const struct kvm_pmu_ops *pmu_ops)
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#undef __KVM_X86_PMU_OP
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}
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static inline bool pmc_is_globally_enabled(struct kvm_pmc *pmc)
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{
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return static_call(kvm_x86_pmu_pmc_is_enabled)(pmc);
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}
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static void kvm_pmi_trigger_fn(struct irq_work *irq_work)
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{
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struct kvm_pmu *pmu = container_of(irq_work, struct kvm_pmu, irq_work);
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@ -20,7 +20,6 @@
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struct kvm_pmu_ops {
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bool (*hw_event_available)(struct kvm_pmc *pmc);
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bool (*pmc_is_enabled)(struct kvm_pmc *pmc);
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struct kvm_pmc *(*pmc_idx_to_pmc)(struct kvm_pmu *pmu, int pmc_idx);
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struct kvm_pmc *(*rdpmc_ecx_to_pmc)(struct kvm_vcpu *vcpu,
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unsigned int idx, u64 *mask);
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@ -227,6 +226,21 @@ static inline void reprogram_counters(struct kvm_pmu *pmu, u64 diff)
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kvm_make_request(KVM_REQ_PMU, pmu_to_vcpu(pmu));
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}
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/*
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* Check if a PMC is enabled by comparing it against global_ctrl bits.
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*
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* If the vPMU doesn't have global_ctrl MSR, all vPMCs are enabled.
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*/
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static inline bool pmc_is_globally_enabled(struct kvm_pmc *pmc)
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{
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struct kvm_pmu *pmu = pmc_to_pmu(pmc);
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if (!kvm_pmu_has_perf_global_ctrl(pmu))
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return true;
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return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl);
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}
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void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu);
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void kvm_pmu_handle_event(struct kvm_vcpu *vcpu);
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int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data);
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@ -78,14 +78,6 @@ static bool amd_hw_event_available(struct kvm_pmc *pmc)
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return true;
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}
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/* check if a PMC is enabled by comparing it against global_ctrl bits. Because
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* AMD CPU doesn't have global_ctrl MSR, all PMCs are enabled (return TRUE).
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*/
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static bool amd_pmc_is_enabled(struct kvm_pmc *pmc)
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{
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return true;
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}
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static bool amd_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx)
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{
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struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
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@ -220,7 +212,6 @@ static void amd_pmu_reset(struct kvm_vcpu *vcpu)
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struct kvm_pmu_ops amd_pmu_ops __initdata = {
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.hw_event_available = amd_hw_event_available,
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.pmc_is_enabled = amd_pmc_is_enabled,
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.pmc_idx_to_pmc = amd_pmc_idx_to_pmc,
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.rdpmc_ecx_to_pmc = amd_rdpmc_ecx_to_pmc,
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.msr_idx_to_pmc = amd_msr_idx_to_pmc,
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@ -95,17 +95,6 @@ static bool intel_hw_event_available(struct kvm_pmc *pmc)
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return true;
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}
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/* check if a PMC is enabled by comparing it with globl_ctrl bits. */
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static bool intel_pmc_is_enabled(struct kvm_pmc *pmc)
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{
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struct kvm_pmu *pmu = pmc_to_pmu(pmc);
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if (!kvm_pmu_has_perf_global_ctrl(pmu))
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return true;
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return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl);
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}
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static bool intel_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx)
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{
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struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
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@ -759,7 +748,7 @@ void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu)
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pmc = intel_pmc_idx_to_pmc(pmu, bit);
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if (!pmc || !pmc_speculative_in_use(pmc) ||
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!intel_pmc_is_enabled(pmc) || !pmc->perf_event)
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!pmc_is_globally_enabled(pmc) || !pmc->perf_event)
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continue;
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/*
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@ -774,7 +763,6 @@ void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu)
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struct kvm_pmu_ops intel_pmu_ops __initdata = {
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.hw_event_available = intel_hw_event_available,
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.pmc_is_enabled = intel_pmc_is_enabled,
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.pmc_idx_to_pmc = intel_pmc_idx_to_pmc,
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.rdpmc_ecx_to_pmc = intel_rdpmc_ecx_to_pmc,
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.msr_idx_to_pmc = intel_msr_idx_to_pmc,
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