diff --git a/arch/mips/boot/dts/mobileye/eyeq6h-epm6.dts b/arch/mips/boot/dts/mobileye/eyeq6h-epm6.dts new file mode 100644 index 000000000000..ebc0d363fbf8 --- /dev/null +++ b/arch/mips/boot/dts/mobileye/eyeq6h-epm6.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright 2024 Mobileye Vision Technologies Ltd. + */ + +/dts-v1/; + +#include "eyeq6h.dtsi" + +/ { + compatible = "mobileye,eyeq6-epm6", "mobileye,eyeq6"; + model = "Mobile EyeQ6H MP6 Evaluation board"; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x1 0x00000000 0x1 0x00000000>; + }; +}; diff --git a/arch/mips/boot/dts/mobileye/eyeq6h-fixed-clocks.dtsi b/arch/mips/boot/dts/mobileye/eyeq6h-fixed-clocks.dtsi new file mode 100644 index 000000000000..5fa99e06fde7 --- /dev/null +++ b/arch/mips/boot/dts/mobileye/eyeq6h-fixed-clocks.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright 2023 Mobileye Vision Technologies Ltd. + */ + +#include + +/ { + xtal: clock-30000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <30000000>; + }; + + pll_west: clock-2000000000-west { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2000000000>; + }; + + pll_cpu: clock-2000000000-cpu { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2000000000>; + }; + + /* pll-cpu derivatives */ + occ_cpu: clock-2000000000-occ-cpu { + compatible = "fixed-factor-clock"; + clocks = <&pll_cpu>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + + /* pll-west derivatives */ + occ_periph_w: clock-200000000 { + compatible = "fixed-factor-clock"; + clocks = <&pll_west>; + #clock-cells = <0>; + clock-div = <10>; + clock-mult = <1>; + }; + uart_clk: clock-200000000-uart { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph_w>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + +}; diff --git a/arch/mips/boot/dts/mobileye/eyeq6h-pins.dtsi b/arch/mips/boot/dts/mobileye/eyeq6h-pins.dtsi new file mode 100644 index 000000000000..a3d1b3684893 --- /dev/null +++ b/arch/mips/boot/dts/mobileye/eyeq6h-pins.dtsi @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright 2024 Mobileye Vision Technologies Ltd. + */ + +/* + * MUX register structure + * bits | field | comment + * [0] | MUX_SEL | 0 - GPIO, 1 - alternative func + * [4] | SW_LOOPBACK| + * [5] | SW_OUT_HZ | + * [7] | DBG_IN | + * [11:8] | DS | drive strength + * [13:12] | PUD | pull-up/pull-down. 0, 3 - no, 1 - PD, 2 - PU + * [14] | OD | Open drain + * [15] | ST_CFG | Hysteretic input enable (Schmitt trigger) + */ + +&pinctrl_west { + // TODO: use pinctrl-single,bias-pullup + // TODO: use pinctrl-single,bias-pulldown + // TODO: use pinctrl-single,drive-strength + // TODO: use pinctrl-single,input-schmitt + + i2c0_pins: i2c0-pins { + pinctrl-single,pins = < + 0x000 0x200 // I2C0_SCL pin + 0x004 0x200 // I2C0_SDA pin + >; + }; + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + 0x008 0x200 // I2C1_SCL pin + 0x00c 0x200 // I2C1_SDA pin + >; + }; + eth0_pins: eth0-pins { + pinctrl-single,pins = < + 0x080 1 // GPIO_C4__SMA0_MDC pin + 0x084 1 // GPIO_C5__SMA0_MDIO pin + >; + }; + uart0_pins: uart0-pins { + pinctrl-single,pins = <0x0a8 1>; // UART0 pin group + }; + uart1_pins: uart1-pins { + pinctrl-single,pins = <0x0a0 1>; // UART1 pin group + }; + spi0_pins: spi0-pins { + pinctrl-single,pins = <0x0ac 1>; // SPI0 pin group + }; + spi1_pins: spi1-pins { + pinctrl-single,pins = <0x0a4 1>; // SPI1 pin group + }; +}; + +&pinctrl_east { + i2c2_pins: i2c2-pins { + pinctrl-single,pins = < + 0x000 0x200 // i2c2_SCL pin + 0x004 0x200 // i2c2_SDA pin + >; + }; + i2c3_pins: i2c3-pins { + pinctrl-single,pins = < + 0x008 0x200 // i2c3_SCL pin + 0x00c 0x200 // i2c3_SDA pin + >; + }; + eth1_pins: eth1-pins { + pinctrl-single,pins = < + 0x080 1 // GPIO_D4__SMA1_MDC pin + 0x084 1 // GPIO_D5__SMA1_MDIO pin + >; + }; + uart2_sel_pins: uart2-pins { + pinctrl-single,pins = <0x0a4 1>; // UART2 pin group + }; + uart3_pins: uart3-pins { + pinctrl-single,pins = <0x09c 1>; // UART3 pin group + }; + spi2_pins: spi2-pins { + pinctrl-single,pins = <0x0a8 1>; // SPI2 pin group + }; + spi3_pins: spi3-pins { + pinctrl-single,pins = <0x0a0 1>; // SPI3 pin group + }; +}; diff --git a/arch/mips/boot/dts/mobileye/eyeq6h.dtsi b/arch/mips/boot/dts/mobileye/eyeq6h.dtsi new file mode 100644 index 000000000000..1db3c3cda2e3 --- /dev/null +++ b/arch/mips/boot/dts/mobileye/eyeq6h.dtsi @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +/* + * Copyright 2024 Mobileye Vision Technologies Ltd. + */ + +#include + +#include "eyeq6h-fixed-clocks.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "img,i6500"; + reg = <0>; + clocks = <&occ_cpu>; + }; + }; + + aliases { + serial0 = &uart0; + }; + + cpu_intc: interrupt-controller { + compatible = "mti,cpu-interrupt-controller"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + uart0: serial@d3331000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0xd3331000 0x0 0x1000>; + reg-io-width = <4>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&occ_periph_w>, <&occ_periph_w>; + clock-names = "uartclk", "apb_pclk"; + }; + + pinctrl_west: pinctrl@d3337000 { + compatible = "pinctrl-single"; + reg = <0x0 0xd3337000 0x0 0xb0>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffff>; + }; + + pinctrl_east: pinctrl@d3357000 { + compatible = "pinctrl-single"; + reg = <0x0 0xd3357000 0x0 0xb0>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffff>; + }; + + pinctrl_south: pinctrl@d8014000 { + compatible = "pinctrl-single"; + reg = <0x0 0xd8014000 0x0 0xf8>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffff>; + }; + + gic: interrupt-controller@f0920000 { + compatible = "mti,gic"; + reg = <0x0 0xf0920000 0x0 0x20000>; + interrupt-controller; + #interrupt-cells = <3>; + + /* + * Declare the interrupt-parent even though the mti,gic + * binding doesn't require it, such that the kernel can + * figure out that cpu_intc is the root interrupt + * controller & should be probed first. + */ + interrupt-parent = <&cpu_intc>; + + timer { + compatible = "mti,gic-timer"; + interrupts = ; + clocks = <&occ_cpu>; + }; + }; + }; +}; + +#include "eyeq6h-pins.dtsi"