pinctrl: rockchip: correct RK3328 iomux width flag for GPIO2-B pins
The base iomux offsets for each GPIO pin line are accumulatively calculated based off iomux width flag in rockchip_pinctrl_get_soc_data. If the iomux width flag is one of IOMUX_WIDTH_4BIT, IOMUX_WIDTH_3BIT or IOMUX_WIDTH_2BIT, the base offset for next pin line would increase by 8 bytes, otherwise it would increase by 4 bytes. Despite most of GPIO2-B iomux have 2-bit data width, which can be fit into 4 bytes space with write mask, it actually take 8 bytes width for whole GPIO2-B line. Commite8448a6c81
("pinctrl: rockchip: fix pinmux bits for RK3328 GPIO2-B pins") wrongly set iomux width flag to 0, causing all base iomux offset for line after GPIO2-B to be calculated wrong. Fix the iomux width flag to IOMUX_WIDTH_2BIT so the offset after GPIO2-B is correctly increased by 8, matching the actual width of GPIO2-B iomux. Fixes:e8448a6c81
("pinctrl: rockchip: fix pinmux bits for RK3328 GPIO2-B pins") Cc: stable@vger.kernel.org Reported-by: Richard Kojedzinszky <richard@kojedz.in> Closes: https://lore.kernel.org/linux-rockchip/4f29b743202397d60edfb3c725537415@kojedz.in/ Tested-by: Richard Kojedzinszky <richard@kojedz.in> Signed-off-by: Huang-Huang Bao <i@eh5.me> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Daniel Golle <daniel@makrotopia.org> Tested-by: Trevor Woerner <twoerner@gmail.com> Link: https://lore.kernel.org/20240709105428.1176375-1-i@eh5.me Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -3795,7 +3795,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = {
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PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
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PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
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PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
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PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
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PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
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PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
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0,
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IOMUX_WIDTH_2BIT,
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IOMUX_WIDTH_3BIT,
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IOMUX_WIDTH_3BIT,
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0),
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0),
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PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
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PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
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