mailbox: Add support for QTI CPUCP mailbox controller
Add support for CPUSS Control Processor (CPUCP) mailbox controller, this driver enables communication between AP and CPUCP by acting as a doorbell between them. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
This commit is contained in:
Sibi Sankar
Jassi Brar
parent
6e7c4cc55d
commit
0e2a9a0310
@ -18461,6 +18461,13 @@ S: Maintained
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F: Documentation/devicetree/bindings/power/avs/qcom,cpr.yaml
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F: drivers/pmdomain/qcom/cpr.c
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QUALCOMM CPUCP MAILBOX DRIVER
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M: Sibi Sankar <quic_sibis@quicinc.com>
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L: linux-arm-msm@vger.kernel.org
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S: Supported
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F: Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml
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F: drivers/mailbox/qcom-cpucp-mbox.c
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QUALCOMM CPUFREQ DRIVER MSM8996/APQ8096
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M: Ilia Lin <ilia.lin@kernel.org>
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L: linux-pm@vger.kernel.org
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@ -276,6 +276,14 @@ config SPRD_MBOX
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to send message between application processors and MCU. Say Y here if
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you want to build the Spreatrum mailbox controller driver.
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config QCOM_CPUCP_MBOX
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tristate "Qualcomm Technologies, Inc. CPUCP mailbox driver"
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depends on ARCH_QCOM || (COMPILE_TEST && 64BIT)
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help
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Qualcomm Technologies, Inc. CPUSS Control Processor (CPUCP) mailbox
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controller driver enables communication between AP and CPUCP. Say
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Y here if you want to build this driver.
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config QCOM_IPCC
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tristate "Qualcomm Technologies, Inc. IPCC driver"
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depends on ARCH_QCOM || COMPILE_TEST
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@ -61,4 +61,6 @@ obj-$(CONFIG_SUN6I_MSGBOX) += sun6i-msgbox.o
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obj-$(CONFIG_SPRD_MBOX) += sprd-mailbox.o
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obj-$(CONFIG_QCOM_CPUCP_MBOX) += qcom-cpucp-mbox.o
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obj-$(CONFIG_QCOM_IPCC) += qcom-ipcc.o
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187
drivers/mailbox/qcom-cpucp-mbox.c
Normal file
187
drivers/mailbox/qcom-cpucp-mbox.c
Normal file
@ -0,0 +1,187 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/bitops.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/mailbox_controller.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#define APSS_CPUCP_IPC_CHAN_SUPPORTED 3
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#define APSS_CPUCP_MBOX_CMD_OFF 0x4
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/* Tx Registers */
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#define APSS_CPUCP_TX_MBOX_CMD(i) (0x100 + ((i) * 8))
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/* Rx Registers */
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#define APSS_CPUCP_RX_MBOX_CMD(i) (0x100 + ((i) * 8))
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#define APSS_CPUCP_RX_MBOX_MAP 0x4000
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#define APSS_CPUCP_RX_MBOX_STAT 0x4400
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#define APSS_CPUCP_RX_MBOX_CLEAR 0x4800
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#define APSS_CPUCP_RX_MBOX_EN 0x4c00
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#define APSS_CPUCP_RX_MBOX_CMD_MASK GENMASK_ULL(63, 0)
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/**
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* struct qcom_cpucp_mbox - Holder for the mailbox driver
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* @chans: The mailbox channel
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* @mbox: The mailbox controller
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* @tx_base: Base address of the CPUCP tx registers
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* @rx_base: Base address of the CPUCP rx registers
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*/
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struct qcom_cpucp_mbox {
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struct mbox_chan chans[APSS_CPUCP_IPC_CHAN_SUPPORTED];
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struct mbox_controller mbox;
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void __iomem *tx_base;
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void __iomem *rx_base;
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};
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static inline int channel_number(struct mbox_chan *chan)
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{
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return chan - chan->mbox->chans;
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}
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static irqreturn_t qcom_cpucp_mbox_irq_fn(int irq, void *data)
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{
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struct qcom_cpucp_mbox *cpucp = data;
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u64 status;
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int i;
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status = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT);
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for_each_set_bit(i, (unsigned long *)&status, APSS_CPUCP_IPC_CHAN_SUPPORTED) {
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u32 val = readl(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i) + APSS_CPUCP_MBOX_CMD_OFF);
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struct mbox_chan *chan = &cpucp->chans[i];
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unsigned long flags;
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/* Provide mutual exclusion with changes to chan->cl */
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spin_lock_irqsave(&chan->lock, flags);
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if (chan->cl)
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mbox_chan_received_data(chan, &val);
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writeq(BIT(i), cpucp->rx_base + APSS_CPUCP_RX_MBOX_CLEAR);
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spin_unlock_irqrestore(&chan->lock, flags);
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}
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return IRQ_HANDLED;
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}
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static int qcom_cpucp_mbox_startup(struct mbox_chan *chan)
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{
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struct qcom_cpucp_mbox *cpucp = container_of(chan->mbox, struct qcom_cpucp_mbox, mbox);
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unsigned long chan_id = channel_number(chan);
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u64 val;
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val = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN);
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val |= BIT(chan_id);
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writeq(val, cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN);
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return 0;
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}
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static void qcom_cpucp_mbox_shutdown(struct mbox_chan *chan)
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{
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struct qcom_cpucp_mbox *cpucp = container_of(chan->mbox, struct qcom_cpucp_mbox, mbox);
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unsigned long chan_id = channel_number(chan);
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u64 val;
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val = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN);
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val &= ~BIT(chan_id);
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writeq(val, cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN);
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}
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static int qcom_cpucp_mbox_send_data(struct mbox_chan *chan, void *data)
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{
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struct qcom_cpucp_mbox *cpucp = container_of(chan->mbox, struct qcom_cpucp_mbox, mbox);
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unsigned long chan_id = channel_number(chan);
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u32 *val = data;
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writel(*val, cpucp->tx_base + APSS_CPUCP_TX_MBOX_CMD(chan_id) + APSS_CPUCP_MBOX_CMD_OFF);
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return 0;
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}
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static const struct mbox_chan_ops qcom_cpucp_mbox_chan_ops = {
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.startup = qcom_cpucp_mbox_startup,
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.send_data = qcom_cpucp_mbox_send_data,
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.shutdown = qcom_cpucp_mbox_shutdown
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};
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static int qcom_cpucp_mbox_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct qcom_cpucp_mbox *cpucp;
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struct mbox_controller *mbox;
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int irq, ret;
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cpucp = devm_kzalloc(dev, sizeof(*cpucp), GFP_KERNEL);
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if (!cpucp)
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return -ENOMEM;
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cpucp->rx_base = devm_of_iomap(dev, dev->of_node, 0, NULL);
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if (IS_ERR(cpucp->rx_base))
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return PTR_ERR(cpucp->rx_base);
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cpucp->tx_base = devm_of_iomap(dev, dev->of_node, 1, NULL);
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if (IS_ERR(cpucp->tx_base))
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return PTR_ERR(cpucp->tx_base);
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writeq(0, cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN);
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writeq(0, cpucp->rx_base + APSS_CPUCP_RX_MBOX_CLEAR);
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writeq(0, cpucp->rx_base + APSS_CPUCP_RX_MBOX_MAP);
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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ret = devm_request_irq(dev, irq, qcom_cpucp_mbox_irq_fn,
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IRQF_TRIGGER_HIGH, "apss_cpucp_mbox", cpucp);
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if (ret < 0)
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return dev_err_probe(dev, ret, "Failed to register irq: %d\n", irq);
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writeq(APSS_CPUCP_RX_MBOX_CMD_MASK, cpucp->rx_base + APSS_CPUCP_RX_MBOX_MAP);
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mbox = &cpucp->mbox;
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mbox->dev = dev;
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mbox->num_chans = APSS_CPUCP_IPC_CHAN_SUPPORTED;
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mbox->chans = cpucp->chans;
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mbox->ops = &qcom_cpucp_mbox_chan_ops;
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ret = devm_mbox_controller_register(dev, mbox);
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if (ret)
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return dev_err_probe(dev, ret, "Failed to create mailbox\n");
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return 0;
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}
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static const struct of_device_id qcom_cpucp_mbox_of_match[] = {
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{ .compatible = "qcom,x1e80100-cpucp-mbox" },
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{}
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};
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MODULE_DEVICE_TABLE(of, qcom_cpucp_mbox_of_match);
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static struct platform_driver qcom_cpucp_mbox_driver = {
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.probe = qcom_cpucp_mbox_probe,
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.driver = {
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.name = "qcom_cpucp_mbox",
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.of_match_table = qcom_cpucp_mbox_of_match,
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},
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};
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static int __init qcom_cpucp_mbox_init(void)
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{
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return platform_driver_register(&qcom_cpucp_mbox_driver);
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}
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core_initcall(qcom_cpucp_mbox_init);
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static void __exit qcom_cpucp_mbox_exit(void)
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{
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platform_driver_unregister(&qcom_cpucp_mbox_driver);
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}
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module_exit(qcom_cpucp_mbox_exit);
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MODULE_DESCRIPTION("QTI CPUCP MBOX Driver");
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MODULE_LICENSE("GPL");
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