dt-bindings: PCI: qcom: Convert to YAML
Changes to the schema: - Fixed the ordering of clock-names/reset-names according to the dtsi files. - Mark vdda-supply as required only for apq/ipq8064 (as it was marked as generally required in the txt file). Changes to examples: - Inline clock and reset numbers rather than including dt-bindings files because of conflicts between the headers - Split ranges and reg properties to follow current practice - Change -gpio to -gpios - Update IRQ flags to LEVEL_HIGH rater than NONE - Removed extra "snps,dw-pcie" compatibility. Note: while it was not clearly described in text schema, the majority of Qualcomm platforms follow the snps,dw-pcie schema and use two compatibility strings in the DT files: platform-specific one and a fallback to the generic snps,dw-pcie one. However the platform itself is not compatible with the snps,dw-pcie interface, so we are going to remove it. Link: https://lore.kernel.org/r/20220506152107.1527552-2-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Dmitry Baryshkov
Bjorn Helgaas
parent
83013631f0
commit
075a9d5593
@ -1,398 +0,0 @@
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* Qualcomm PCI express root complex
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- compatible:
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Usage: required
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Value type: <stringlist>
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Definition: Value should contain
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- "qcom,pcie-ipq8064" for ipq8064
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- "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065
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- "qcom,pcie-apq8064" for apq8064
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- "qcom,pcie-apq8084" for apq8084
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- "qcom,pcie-msm8996" for msm8996 or apq8096
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- "qcom,pcie-ipq4019" for ipq4019
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- "qcom,pcie-ipq8074" for ipq8074
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- "qcom,pcie-qcs404" for qcs404
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- "qcom,pcie-sc8180x" for sc8180x
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- "qcom,pcie-sdm845" for sdm845
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- "qcom,pcie-sm8150" for sm8150
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- "qcom,pcie-sm8250" for sm8250
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- "qcom,pcie-sm8450-pcie0" for PCIe0 on sm8450
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- "qcom,pcie-sm8450-pcie1" for PCIe1 on sm8450
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- "qcom,pcie-ipq6018" for ipq6018
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- reg:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: Register ranges as listed in the reg-names property
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- reg-names:
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Usage: required
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Value type: <stringlist>
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Definition: Must include the following entries
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- "parf" Qualcomm specific registers
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- "dbi" DesignWare PCIe registers
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- "elbi" External local bus interface registers
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- "config" PCIe configuration space
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- "atu" ATU address space (optional)
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- device_type:
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Usage: required
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Value type: <string>
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Definition: Should be "pci". As specified in snps,dw-pcie.yaml
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- #address-cells:
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Usage: required
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Value type: <u32>
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Definition: Should be 3. As specified in snps,dw-pcie.yaml
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- #size-cells:
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Usage: required
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Value type: <u32>
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Definition: Should be 2. As specified in snps,dw-pcie.yaml
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- ranges:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: As specified in snps,dw-pcie.yaml
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- interrupts:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: MSI interrupt
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- interrupt-names:
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Usage: required
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Value type: <stringlist>
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Definition: Should contain "msi"
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- #interrupt-cells:
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Usage: required
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Value type: <u32>
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Definition: Should be 1. As specified in snps,dw-pcie.yaml
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- interrupt-map-mask:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: As specified in snps,dw-pcie.yaml
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- interrupt-map:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: As specified in snps,dw-pcie.yaml
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- clocks:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: List of phandle and clock specifier pairs as listed
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in clock-names property
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- clock-names:
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Usage: required
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Value type: <stringlist>
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Definition: Should contain the following entries
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- "iface" Configuration AHB clock
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- clock-names:
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Usage: required for ipq/apq8064
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Value type: <stringlist>
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Definition: Should contain the following entries
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- "core" Clocks the pcie hw block
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- "phy" Clocks the pcie PHY block
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- "aux" Clocks the pcie AUX block
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- "ref" Clocks the pcie ref block
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- clock-names:
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Usage: required for apq8084/ipq4019
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Value type: <stringlist>
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Definition: Should contain the following entries
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- "aux" Auxiliary (AUX) clock
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- "bus_master" Master AXI clock
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- "bus_slave" Slave AXI clock
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- clock-names:
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Usage: required for msm8996/apq8096
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Value type: <stringlist>
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Definition: Should contain the following entries
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- "pipe" Pipe Clock driving internal logic
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- "aux" Auxiliary (AUX) clock
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- "cfg" Configuration clock
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- "bus_master" Master AXI clock
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- "bus_slave" Slave AXI clock
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- clock-names:
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Usage: required for ipq8074
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Value type: <stringlist>
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Definition: Should contain the following entries
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- "iface" PCIe to SysNOC BIU clock
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- "axi_m" AXI Master clock
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- "axi_s" AXI Slave clock
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- "ahb" AHB clock
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- "aux" Auxiliary clock
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- clock-names:
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Usage: required for ipq6018
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Value type: <stringlist>
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Definition: Should contain the following entries
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- "iface" PCIe to SysNOC BIU clock
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- "axi_m" AXI Master clock
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- "axi_s" AXI Slave clock
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- "axi_bridge" AXI bridge clock
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- "rchng"
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- clock-names:
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Usage: required for qcs404
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Value type: <stringlist>
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Definition: Should contain the following entries
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- "iface" AHB clock
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- "aux" Auxiliary clock
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- "master_bus" AXI Master clock
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- "slave_bus" AXI Slave clock
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- clock-names:
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Usage: required for sdm845
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Value type: <stringlist>
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Definition: Should contain the following entries
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- "aux" Auxiliary clock
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- "cfg" Configuration clock
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- "bus_master" Master AXI clock
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- "bus_slave" Slave AXI clock
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- "slave_q2a" Slave Q2A clock
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- "tbu" PCIe TBU clock
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- "pipe" PIPE clock
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- clock-names:
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Usage: required for sc8180x, sm8150 and sm8250
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Value type: <stringlist>
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Definition: Should contain the following entries
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- "aux" Auxiliary clock
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- "cfg" Configuration clock
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- "bus_master" Master AXI clock
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- "bus_slave" Slave AXI clock
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- "slave_q2a" Slave Q2A clock
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- "tbu" PCIe TBU clock
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- "ddrss_sf_tbu" PCIe SF TBU clock
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- "pipe" PIPE clock
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- clock-names:
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Usage: required for sm8450-pcie0 and sm8450-pcie1
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Value type: <stringlist>
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Definition: Should contain the following entries
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- "aux" Auxiliary clock
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- "cfg" Configuration clock
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- "bus_master" Master AXI clock
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- "bus_slave" Slave AXI clock
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- "slave_q2a" Slave Q2A clock
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- "tbu" PCIe TBU clock
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- "ddrss_sf_tbu" PCIe SF TBU clock
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- "pipe" PIPE clock
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- "pipe_mux" PIPE MUX
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- "phy_pipe" PIPE output clock
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- "ref" REFERENCE clock
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- "aggre0" Aggre NoC PCIe0 AXI clock, only for sm8450-pcie0
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- "aggre1" Aggre NoC PCIe1 AXI clock
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- resets:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: List of phandle and reset specifier pairs as listed
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in reset-names property
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- reset-names:
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Usage: required for ipq/apq8064
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Value type: <stringlist>
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Definition: Should contain the following entries
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- "axi" AXI reset
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- "ahb" AHB reset
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- "por" POR reset
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- "pci" PCI reset
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- "phy" PHY reset
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- reset-names:
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Usage: required for apq8084
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Value type: <stringlist>
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Definition: Should contain the following entries
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- "core" Core reset
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- reset-names:
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Usage: required for ipq/apq8064
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Value type: <stringlist>
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Definition: Should contain the following entries
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- "axi_m" AXI master reset
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- "axi_s" AXI slave reset
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- "pipe" PIPE reset
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- "axi_m_vmid" VMID reset
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- "axi_s_xpu" XPU reset
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- "parf" PARF reset
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- "phy" PHY reset
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- "axi_m_sticky" AXI sticky reset
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- "pipe_sticky" PIPE sticky reset
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- "pwr" PWR reset
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- "ahb" AHB reset
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- "phy_ahb" PHY AHB reset
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- "ext" EXT reset
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- reset-names:
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Usage: required for ipq8074
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Value type: <stringlist>
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Definition: Should contain the following entries
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- "pipe" PIPE reset
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- "sleep" Sleep reset
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- "sticky" Core Sticky reset
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- "axi_m" AXI Master reset
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- "axi_s" AXI Slave reset
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- "ahb" AHB Reset
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- "axi_m_sticky" AXI Master Sticky reset
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- reset-names:
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Usage: required for ipq6018
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Value type: <stringlist>
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Definition: Should contain the following entries
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- "pipe" PIPE reset
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- "sleep" Sleep reset
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- "sticky" Core Sticky reset
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- "axi_m" AXI Master reset
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- "axi_s" AXI Slave reset
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- "ahb" AHB Reset
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- "axi_m_sticky" AXI Master Sticky reset
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- "axi_s_sticky" AXI Slave Sticky reset
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- reset-names:
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Usage: required for qcs404
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Value type: <stringlist>
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Definition: Should contain the following entries
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- "axi_m" AXI Master reset
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- "axi_s" AXI Slave reset
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- "axi_m_sticky" AXI Master Sticky reset
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- "pipe_sticky" PIPE sticky reset
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- "pwr" PWR reset
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- "ahb" AHB reset
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- reset-names:
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Usage: required for sc8180x, sdm845, sm8150, sm8250 and sm8450
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Value type: <stringlist>
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Definition: Should contain the following entries
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- "pci" PCIe core reset
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- power-domains:
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Usage: required for apq8084 and msm8996/apq8096
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Value type: <prop-encoded-array>
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Definition: A phandle and power domain specifier pair to the
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power domain which is responsible for collapsing
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and restoring power to the peripheral
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- vdda-supply:
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Usage: required
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Value type: <phandle>
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Definition: A phandle to the core analog power supply
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- vdda_phy-supply:
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Usage: required for ipq/apq8064
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Value type: <phandle>
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Definition: A phandle to the analog power supply for PHY
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- vdda_refclk-supply:
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Usage: required for ipq/apq8064
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Value type: <phandle>
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Definition: A phandle to the analog power supply for IC which generates
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reference clock
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- vddpe-3v3-supply:
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Usage: optional
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Value type: <phandle>
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Definition: A phandle to the PCIe endpoint power supply
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- phys:
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Usage: required for apq8084 and qcs404
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Value type: <phandle>
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Definition: List of phandle(s) as listed in phy-names property
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- phy-names:
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Usage: required for apq8084 and qcs404
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Value type: <stringlist>
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Definition: Should contain "pciephy"
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- <name>-gpios:
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Usage: optional
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Value type: <prop-encoded-array>
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Definition: List of phandle and GPIO specifier pairs. Should contain
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- "perst-gpios" PCIe endpoint reset signal line
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- "wake-gpios" PCIe endpoint wake signal line
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* Example for ipq/apq8064
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pcie@1b500000 {
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compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie";
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reg = <0x1b500000 0x1000
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0x1b502000 0x80
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0x1b600000 0x100
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0x0ff00000 0x100000>;
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reg-names = "dbi", "elbi", "parf", "config";
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device_type = "pci";
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linux,pci-domain = <0>;
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bus-range = <0x00 0xff>;
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num-lanes = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
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0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
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interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
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<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
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<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
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<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
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clocks = <&gcc PCIE_A_CLK>,
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<&gcc PCIE_H_CLK>,
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<&gcc PCIE_PHY_CLK>,
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<&gcc PCIE_AUX_CLK>,
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<&gcc PCIE_ALT_REF_CLK>;
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clock-names = "core", "iface", "phy", "aux", "ref";
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resets = <&gcc PCIE_ACLK_RESET>,
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<&gcc PCIE_HCLK_RESET>,
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<&gcc PCIE_POR_RESET>,
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<&gcc PCIE_PCI_RESET>,
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<&gcc PCIE_PHY_RESET>,
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<&gcc PCIE_EXT_RESET>;
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reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
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pinctrl-0 = <&pcie_pins_default>;
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pinctrl-names = "default";
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};
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* Example for apq8084
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pcie0@fc520000 {
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compatible = "qcom,pcie-apq8084", "snps,dw-pcie";
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reg = <0xfc520000 0x2000>,
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<0xff000000 0x1000>,
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<0xff001000 0x1000>,
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<0xff002000 0x2000>;
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reg-names = "parf", "dbi", "elbi", "config";
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device_type = "pci";
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linux,pci-domain = <0>;
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bus-range = <0x00 0xff>;
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num-lanes = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x81000000 0 0 0xff200000 0 0x00100000 /* I/O */
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0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */
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interrupts = <GIC_SPI 243 IRQ_TYPE_NONE>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
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<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
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<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
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<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
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clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_0_AUX_CLK>;
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clock-names = "iface", "master_bus", "slave_bus", "aux";
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resets = <&gcc GCC_PCIE_0_BCR>;
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reset-names = "core";
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power-domains = <&gcc PCIE0_GDSC>;
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vdda-supply = <&pma8084_l3>;
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phys = <&pciephy0>;
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phy-names = "pciephy";
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perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>;
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pinctrl-0 = <&pcie0_pins_default>;
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pinctrl-names = "default";
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};
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595
Documentation/devicetree/bindings/pci/qcom,pcie.yaml
Normal file
595
Documentation/devicetree/bindings/pci/qcom,pcie.yaml
Normal file
@ -0,0 +1,595 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm PCI express root complex
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maintainers:
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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- Stanimir Varbanov <svarbanov@mm-sol.com>
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description: |
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Qualcomm PCIe root complex controller is bansed on the Synopsys DesignWare
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PCIe IP.
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properties:
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compatible:
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enum:
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- qcom,pcie-ipq8064
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- qcom,pcie-ipq8064-v2
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- qcom,pcie-apq8064
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- qcom,pcie-apq8084
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- qcom,pcie-msm8996
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- qcom,pcie-ipq4019
|
||||
- qcom,pcie-ipq8074
|
||||
- qcom,pcie-qcs404
|
||||
- qcom,pcie-sc8180x
|
||||
- qcom,pcie-sdm845
|
||||
- qcom,pcie-sm8150
|
||||
- qcom,pcie-sm8250
|
||||
- qcom,pcie-sm8450-pcie0
|
||||
- qcom,pcie-sm8450-pcie1
|
||||
- qcom,pcie-ipq6018
|
||||
|
||||
reg:
|
||||
minItems: 4
|
||||
maxItems: 5
|
||||
|
||||
reg-names:
|
||||
minItems: 4
|
||||
maxItems: 5
|
||||
items:
|
||||
enum:
|
||||
- parf # Qualcomm specific registers
|
||||
- dbi # DesignWare PCIe registers
|
||||
- elbi # External local bus interface registers
|
||||
- config # PCIe configuration space
|
||||
- atu # ATU address space (optional)
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi
|
||||
|
||||
# Common definitions for clocks, clock-names and reset.
|
||||
# Platform constraints are described later.
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 12
|
||||
|
||||
clock-names:
|
||||
minItems: 3
|
||||
maxItems: 12
|
||||
|
||||
resets:
|
||||
minItems: 1
|
||||
maxItems: 12
|
||||
|
||||
resets-names:
|
||||
minItems: 1
|
||||
maxItems: 12
|
||||
|
||||
vdda-supply:
|
||||
description: A phandle to the core analog power supply
|
||||
|
||||
vdda_phy-supply:
|
||||
description: A phandle to the core analog power supply for PHY
|
||||
|
||||
vdda_refclk-supply:
|
||||
description: A phandle to the core analog power supply for IC which generates reference clock
|
||||
|
||||
vddpe-3v3-supply:
|
||||
description: A phandle to the PCIe endpoint power supply
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
phy-names:
|
||||
items:
|
||||
- const: pciephy
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
perst-gpios:
|
||||
description: GPIO controlled connection to PERST# signal
|
||||
maxItems: 1
|
||||
|
||||
wake-gpios:
|
||||
description: GPIO controlled connection to WAKE# signal
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- "#interrupt-cells"
|
||||
- interrupt-map-mask
|
||||
- interrupt-map
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-bus.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-apq8064
|
||||
- qcom,pcie-ipq8064
|
||||
- qcom,pcie-ipq8064v2
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 5
|
||||
clock-names:
|
||||
minItems: 3
|
||||
items:
|
||||
- const: core # Clocks the pcie hw block
|
||||
- const: iface # Configuration AHB clock
|
||||
- const: phy # Clocks the pcie PHY block
|
||||
- const: aux # Clocks the pcie AUX block, not on apq8064
|
||||
- const: ref # Clocks the pcie ref block, not on apq8064
|
||||
resets:
|
||||
minItems: 5
|
||||
maxItems: 6
|
||||
reset-names:
|
||||
minItems: 5
|
||||
items:
|
||||
- const: axi # AXI reset
|
||||
- const: ahb # AHB reset
|
||||
- const: por # POR reset
|
||||
- const: pci # PCI reset
|
||||
- const: phy # PHY reset
|
||||
- const: ext # EXT reset, not on apq8064
|
||||
required:
|
||||
- vdda-supply
|
||||
- vdda_phy-supply
|
||||
- vdda_refclk-supply
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-apq8084
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface # Configuration AHB clock
|
||||
- const: master_bus # Master AXI clock
|
||||
- const: slave_bus # Slave AXI clock
|
||||
- const: aux # Auxiliary (AUX) clock
|
||||
resets:
|
||||
maxItems: 1
|
||||
reset-names:
|
||||
items:
|
||||
- const: core # Core reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-ipq4019
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
clock-names:
|
||||
items:
|
||||
- const: aux # Auxiliary (AUX) clock
|
||||
- const: master_bus # Master AXI clock
|
||||
- const: slave_bus # Slave AXI clock
|
||||
resets:
|
||||
minItems: 12
|
||||
maxItems: 12
|
||||
reset-names:
|
||||
items:
|
||||
- const: axi_m # AXI master reset
|
||||
- const: axi_s # AXI slave reset
|
||||
- const: pipe # PIPE reset
|
||||
- const: axi_m_vmid # VMID reset
|
||||
- const: axi_s_xpu # XPU reset
|
||||
- const: parf # PARF reset
|
||||
- const: phy # PHY reset
|
||||
- const: axi_m_sticky # AXI sticky reset
|
||||
- const: pipe_sticky # PIPE sticky reset
|
||||
- const: pwr # PWR reset
|
||||
- const: ahb # AHB reset
|
||||
- const: phy_ahb # PHY AHB reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-msm8996
|
||||
then:
|
||||
oneOf:
|
||||
- properties:
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # Pipe Clock driving internal logic
|
||||
- const: aux # Auxiliary (AUX) clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- properties:
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # Pipe Clock driving internal logic
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: aux # Auxiliary (AUX) clock
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 5
|
||||
maxItems: 5
|
||||
resets: false
|
||||
reset-names: false
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-ipq8074
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 5
|
||||
maxItems: 5
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface # PCIe to SysNOC BIU clock
|
||||
- const: axi_m # AXI Master clock
|
||||
- const: axi_s # AXI Slave clock
|
||||
- const: ahb # AHB clock
|
||||
- const: aux # Auxiliary clock
|
||||
resets:
|
||||
minItems: 7
|
||||
maxItems: 7
|
||||
reset-names:
|
||||
items:
|
||||
- const: pipe # PIPE reset
|
||||
- const: sleep # Sleep reset
|
||||
- const: sticky # Core Sticky reset
|
||||
- const: axi_m # AXI Master reset
|
||||
- const: axi_s # AXI Slave reset
|
||||
- const: ahb # AHB Reset
|
||||
- const: axi_m_sticky # AXI Master Sticky reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-ipq6018
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 5
|
||||
maxItems: 5
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface # PCIe to SysNOC BIU clock
|
||||
- const: axi_m # AXI Master clock
|
||||
- const: axi_s # AXI Slave clock
|
||||
- const: axi_bridge # AXI bridge clock
|
||||
- const: rchng
|
||||
resets:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
reset-names:
|
||||
items:
|
||||
- const: pipe # PIPE reset
|
||||
- const: sleep # Sleep reset
|
||||
- const: sticky # Core Sticky reset
|
||||
- const: axi_m # AXI Master reset
|
||||
- const: axi_s # AXI Slave reset
|
||||
- const: ahb # AHB Reset
|
||||
- const: axi_m_sticky # AXI Master Sticky reset
|
||||
- const: axi_s_sticky # AXI Slave Sticky reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-qcs404
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface # AHB clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: master_bus # AXI Master clock
|
||||
- const: slave_bus # AXI Slave clock
|
||||
resets:
|
||||
minItems: 6
|
||||
maxItems: 6
|
||||
reset-names:
|
||||
items:
|
||||
- const: axi_m # AXI Master reset
|
||||
- const: axi_s # AXI Slave reset
|
||||
- const: axi_m_sticky # AXI Master Sticky reset
|
||||
- const: pipe_sticky # PIPE sticky reset
|
||||
- const: pwr # PWR reset
|
||||
- const: ahb # AHB reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-sdm845
|
||||
then:
|
||||
oneOf:
|
||||
# Unfortunately the "optional" ref clock is used in the middle of the list
|
||||
- properties:
|
||||
clocks:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # PIPE clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: ref # REFERENCE clock
|
||||
- const: tbu # PCIe TBU clock
|
||||
- properties:
|
||||
clocks:
|
||||
minItems: 7
|
||||
maxItems: 7
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # PIPE clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: tbu # PCIe TBU clock
|
||||
properties:
|
||||
resets:
|
||||
maxItems: 1
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci # PCIe core reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-sc8180x
|
||||
- qcom,pcie-sm8150
|
||||
- qcom,pcie-sm8250
|
||||
then:
|
||||
oneOf:
|
||||
# Unfortunately the "optional" ref clock is used in the middle of the list
|
||||
- properties:
|
||||
clocks:
|
||||
minItems: 9
|
||||
maxItems: 9
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # PIPE clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: ref # REFERENCE clock
|
||||
- const: tbu # PCIe TBU clock
|
||||
- const: ddrss_sf_tbu # PCIe SF TBU clock
|
||||
- properties:
|
||||
clocks:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # PIPE clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: tbu # PCIe TBU clock
|
||||
- const: ddrss_sf_tbu # PCIe SF TBU clock
|
||||
properties:
|
||||
resets:
|
||||
maxItems: 1
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci # PCIe core reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-sm8450-pcie0
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 12
|
||||
maxItems: 12
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # PIPE clock
|
||||
- const: pipe_mux # PIPE MUX
|
||||
- const: phy_pipe # PIPE output clock
|
||||
- const: ref # REFERENCE clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: ddrss_sf_tbu # PCIe SF TBU clock
|
||||
- const: aggre0 # Aggre NoC PCIe0 AXI clock
|
||||
- const: aggre1 # Aggre NoC PCIe1 AXI clock
|
||||
resets:
|
||||
maxItems: 1
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci # PCIe core reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-sm8450-pcie1
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 11
|
||||
maxItems: 11
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # PIPE clock
|
||||
- const: pipe_mux # PIPE MUX
|
||||
- const: phy_pipe # PIPE output clock
|
||||
- const: ref # REFERENCE clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: ddrss_sf_tbu # PCIe SF TBU clock
|
||||
- const: aggre1 # Aggre NoC PCIe1 AXI clock
|
||||
resets:
|
||||
maxItems: 1
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci # PCIe core reset
|
||||
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-apq8064
|
||||
- qcom,pcie-ipq4019
|
||||
- qcom,pcie-ipq8064
|
||||
- qcom,pcie-ipq8064v2
|
||||
- qcom,pcie-ipq8074
|
||||
- qcom,pcie-qcs404
|
||||
then:
|
||||
required:
|
||||
- power-domains
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
pcie@1b500000 {
|
||||
compatible = "qcom,pcie-ipq8064";
|
||||
reg = <0x1b500000 0x1000>,
|
||||
<0x1b502000 0x80>,
|
||||
<0x1b600000 0x100>,
|
||||
<0x0ff00000 0x100000>;
|
||||
reg-names = "dbi", "elbi", "parf", "config";
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>,
|
||||
<0x82000000 0 0 0x08000000 0 0x07e00000>;
|
||||
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc 41>,
|
||||
<&gcc 43>,
|
||||
<&gcc 44>,
|
||||
<&gcc 42>,
|
||||
<&gcc 248>;
|
||||
clock-names = "core", "iface", "phy", "aux", "ref";
|
||||
resets = <&gcc 27>,
|
||||
<&gcc 26>,
|
||||
<&gcc 25>,
|
||||
<&gcc 24>,
|
||||
<&gcc 23>,
|
||||
<&gcc 22>;
|
||||
reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
|
||||
pinctrl-0 = <&pcie_pins_default>;
|
||||
pinctrl-names = "default";
|
||||
vdda-supply = <&pm8921_s3>;
|
||||
vdda_phy-supply = <&pm8921_lvs6>;
|
||||
vdda_refclk-supply = <&ext_3p3v>;
|
||||
};
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
pcie@fc520000 {
|
||||
compatible = "qcom,pcie-apq8084";
|
||||
reg = <0xfc520000 0x2000>,
|
||||
<0xff000000 0x1000>,
|
||||
<0xff001000 0x1000>,
|
||||
<0xff002000 0x2000>;
|
||||
reg-names = "parf", "dbi", "elbi", "config";
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x81000000 0 0 0xff200000 0 0x00100000>,
|
||||
<0x82000000 0 0x00300000 0xff300000 0 0x00d00000>;
|
||||
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc 324>,
|
||||
<&gcc 325>,
|
||||
<&gcc 327>,
|
||||
<&gcc 323>;
|
||||
clock-names = "iface", "master_bus", "slave_bus", "aux";
|
||||
resets = <&gcc 81>;
|
||||
reset-names = "core";
|
||||
power-domains = <&gcc 1>;
|
||||
vdda-supply = <&pma8084_l3>;
|
||||
phys = <&pciephy0>;
|
||||
phy-names = "pciephy";
|
||||
perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-0 = <&pcie0_pins_default>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
...
|
||||
Loading…
Reference in New Issue
Block a user