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dt-bindings: clock: google,gs101-clock: add HSI2 clock management unit

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Add dt schema documentation and clock IDs for the High Speed Interface
2 (HSI2) clock management unit. This CMU feeds high speed interfaces
such as PCIe and UFS.

[AD: * keep CMUs in google,gs101.h sorted alphabetically
     * resolve minor merge conflicts in google,gs101-clock.yaml
     * s/ufs_embd/ufs    s/mmc_card/mmc

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Link: https://lore.kernel.org/r/20240429-hsi0-gs101-v3-1-f233be0a2455@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Peter Griffin 2024-04-29 14:02:17 +01:00 committed by Krzysztof Kozlowski
parent dbf76c0d3d
commit 01aea123b1
2 changed files with 88 additions and 0 deletions
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26
Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
View File

@ -31,6 +31,7 @@ properties:
- google,gs101-cmu-apm
- google,gs101-cmu-misc
- google,gs101-cmu-hsi0
- google,gs101-cmu-hsi2
- google,gs101-cmu-peric0
- google,gs101-cmu-peric1
@ -97,6 +98,31 @@ allOf:
- const: usb31drd
- const: usbdpdbg
- if:
properties:
compatible:
contains:
enum:
- google,gs101-cmu-hsi2
then:
properties:
clocks:
items:
- description: External reference clock (24.576 MHz)
- description: High Speed Interface bus clock (from CMU_TOP)
- description: High Speed Interface pcie clock (from CMU_TOP)
- description: High Speed Interface ufs clock (from CMU_TOP)
- description: High Speed Interface mmc clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: bus
- const: pcie
- const: ufs
- const: mmc
- if:
properties:
compatible:

62
include/dt-bindings/clock/google,gs101.h
View File

@ -367,6 +367,68 @@
#define CLK_GOUT_HSI0_XIU_D1_HSI0_ACLK 51
#define CLK_GOUT_HSI0_XIU_P_HSI0_ACLK 52
/* CMU_HSI2 */
#define CLK_MOUT_HSI2_BUS_USER 1
#define CLK_MOUT_HSI2_MMC_CARD_USER 2
#define CLK_MOUT_HSI2_PCIE_USER 3
#define CLK_MOUT_HSI2_UFS_EMBD_USER 4
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_PHY_REFCLK_IN 5
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_PHY_REFCLK_IN 6
#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_ACLK 7
#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_PCLK 8
#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_ACLK 9
#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_PCLK 10
#define CLK_GOUT_HSI2_D_TZPC_HSI2_PCLK 11
#define CLK_GOUT_HSI2_GPC_HSI2_PCLK 12
#define CLK_GOUT_HSI2_GPIO_HSI2_PCLK 13
#define CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK 14
#define CLK_GOUT_HSI2_LHM_AXI_P_HSI2_I_CLK 15
#define CLK_GOUT_HSI2_LHS_ACEL_D_HSI2_I_CLK 16
#define CLK_GOUT_HSI2_MMC_CARD_I_ACLK 17
#define CLK_GOUT_HSI2_MMC_CARD_SDCLKIN 18
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_DBI_ACLK_UG 19
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_MSTR_ACLK_UG 20
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_SLV_ACLK_UG 21
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_I_DRIVER_APB_CLK 22
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_DBI_ACLK_UG 23
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_MSTR_ACLK_UG 24
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_SLV_ACLK_UG 25
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_I_DRIVER_APB_CLK 26
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PHY_UDBG_I_APB_PCLK 27
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PIPE_PAL_PCIE_I_APB_PCLK 28
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PCIEPHY210X2_QCH_I_APB_PCLK 29
#define CLK_GOUT_HSI2_PCIE_IA_GEN4A_1_I_CLK 30
#define CLK_GOUT_HSI2_PCIE_IA_GEN4B_1_I_CLK 31
#define CLK_GOUT_HSI2_PPMU_HSI2_ACLK 32
#define CLK_GOUT_HSI2_PPMU_HSI2_PCLK 33
#define CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_ACLK 34
#define CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_PCLK 35
#define CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_ACLK 36
#define CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_PCLK 37
#define CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_ACLK 38
#define CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_PCLK 39
#define CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK 40
#define CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK 41
#define CLK_GOUT_HSI2_CLK_HSI2_BUS_CLK 42
#define CLK_GOUT_HSI2_CLK_HSI2_OSCCLK_CLK 43
#define CLK_GOUT_HSI2_SSMT_HSI2_ACLK 44
#define CLK_GOUT_HSI2_SSMT_HSI2_PCLK 45
#define CLK_GOUT_HSI2_SYSMMU_HSI2_CLK_S2 46
#define CLK_GOUT_HSI2_SYSREG_HSI2_PCLK 47
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_ACLK 48
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_PCLK 49
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_ACLK 50
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_PCLK 51
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_ACLK 52
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_PCLK 53
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_ACLK 54
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_PCLK 55
#define CLK_GOUT_HSI2_UFS_EMBD_I_ACLK 56
#define CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO 57
#define CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK 58
#define CLK_GOUT_HSI2_XIU_D_HSI2_ACLK 59
#define CLK_GOUT_HSI2_XIU_P_HSI2_ACLK 60
/* CMU_MISC */
#define CLK_MOUT_MISC_BUS_USER 1
#define CLK_MOUT_MISC_SSS_USER 2