2005-04-16 15:20:36 -07:00
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/*
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* File: msi.c
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* Purpose: PCI Message Signaled Interrupt (MSI)
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*
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* Copyright (C) 2003-2004 Intel
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* Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
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*/
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2006-10-04 02:16:41 -07:00
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#include <linux/err.h>
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2005-04-16 15:20:36 -07:00
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#include <linux/mm.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/pci.h>
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#include <linux/proc_fs.h>
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2006-10-04 02:16:59 -07:00
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#include <linux/msi.h>
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2007-04-26 18:21:38 -07:00
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#include <linux/smp.h>
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2005-04-16 15:20:36 -07:00
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#include <asm/errno.h>
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#include <asm/io.h>
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#include "pci.h"
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#include "msi.h"
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static int pci_msi_enable = 1;
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2007-03-05 01:30:10 -07:00
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static void msi_set_enable(struct pci_dev *dev, int enable)
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{
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int pos;
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u16 control;
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pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
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if (pos) {
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pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
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control &= ~PCI_MSI_FLAGS_ENABLE;
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if (enable)
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control |= PCI_MSI_FLAGS_ENABLE;
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pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
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}
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}
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static void msix_set_enable(struct pci_dev *dev, int enable)
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{
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int pos;
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u16 control;
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pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
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if (pos) {
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pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
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control &= ~PCI_MSIX_FLAGS_ENABLE;
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if (enable)
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control |= PCI_MSIX_FLAGS_ENABLE;
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pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
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}
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}
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2007-03-30 11:54:08 -07:00
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static void msix_flush_writes(unsigned int irq)
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{
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struct msi_desc *entry;
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entry = get_irq_msi(irq);
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BUG_ON(!entry || !entry->dev);
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switch (entry->msi_attrib.type) {
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case PCI_CAP_ID_MSI:
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/* nothing to do */
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break;
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case PCI_CAP_ID_MSIX:
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{
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int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
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PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET;
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readl(entry->mask_base + offset);
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break;
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}
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default:
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BUG();
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break;
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}
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}
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2006-10-04 02:16:41 -07:00
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static void msi_set_mask_bit(unsigned int irq, int flag)
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2005-04-16 15:20:36 -07:00
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{
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struct msi_desc *entry;
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2007-01-28 12:52:03 -07:00
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entry = get_irq_msi(irq);
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2006-10-04 02:16:57 -07:00
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BUG_ON(!entry || !entry->dev);
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2005-04-16 15:20:36 -07:00
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switch (entry->msi_attrib.type) {
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case PCI_CAP_ID_MSI:
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2006-10-04 02:16:57 -07:00
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if (entry->msi_attrib.maskbit) {
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2007-01-17 21:50:05 -07:00
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int pos;
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u32 mask_bits;
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2006-10-04 02:16:57 -07:00
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pos = (long)entry->mask_base;
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pci_read_config_dword(entry->dev, pos, &mask_bits);
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mask_bits &= ~(1);
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mask_bits |= flag;
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pci_write_config_dword(entry->dev, pos, mask_bits);
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2007-03-05 01:30:11 -07:00
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} else {
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msi_set_enable(entry->dev, !flag);
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2006-10-04 02:16:57 -07:00
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}
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2005-04-16 15:20:36 -07:00
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break;
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case PCI_CAP_ID_MSIX:
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{
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int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
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PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET;
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writel(flag, entry->mask_base + offset);
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[PATCH] msi: synchronously mask and unmask msi-x irqs.
This is a simplified and actually more comprehensive form of a bug
fix from Mitch Williams <mitch.a.williams@intel.com>.
When we mask or unmask a msi-x irqs the writes may be posted because
we are writing to memory mapped region. This means the mask and
unmask don't happen immediately but at some unspecified time in the
future. Which is out of sync with how the mask/unmask logic work
for ioapic irqs.
The practical result is that we get very subtle and hard to track down
irq migration bugs.
This patch performs a read flush after writes to the MSI-X table for mask
and unmask operations. Since the SMP affinity is set while the interrupt
is masked, and since it's unmasked immediately after, no additional flushes
are required in the various affinity setting routines.
The testing by Mitch Williams on his especially problematic system should
still be valid as I have only simplified the code, not changed the
functionality.
We currently have 7 drivers: cciss, mthca, cxgb3, forceth, s2io,
pcie/portdrv_core, and qla2xxx in 2.6.21 that are affected by this
problem when the hardware they driver is plugged into the right slot.
Given the difficulty of reproducing this bug and tracing it down to
anything that even remotely resembles a cause, even if people are
being affected we aren't likely to see many meaningful bug reports, and
the people who see this bug aren't likely to be able to reproduce this
bug in a timely fashion. So it is best to get this problem fixed
as soon as we can so people don't have problems.
Then if people do have a kernel message stating "No irq for vector" we
will know it is yet another novel cause that needs a complete new
investigation.
Cc: Greg KH <greg@kroah.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
Acked-by: Mitch Williams <mitch.a.williams@intel.com>
Acked-by: "Siddha, Suresh B" <suresh.b.siddha@intel.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-04-03 00:41:49 -07:00
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readl(entry->mask_base + offset);
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2005-04-16 15:20:36 -07:00
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break;
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}
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default:
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2006-10-04 02:16:57 -07:00
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BUG();
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2005-04-16 15:20:36 -07:00
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break;
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}
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2007-03-08 13:04:57 -07:00
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entry->msi_attrib.masked = !!flag;
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2005-04-16 15:20:36 -07:00
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}
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2006-10-04 02:16:59 -07:00
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void read_msi_msg(unsigned int irq, struct msi_msg *msg)
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2005-04-16 15:20:36 -07:00
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{
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2007-01-28 12:52:03 -07:00
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struct msi_desc *entry = get_irq_msi(irq);
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2006-10-04 02:16:33 -07:00
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switch(entry->msi_attrib.type) {
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case PCI_CAP_ID_MSI:
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{
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struct pci_dev *dev = entry->dev;
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int pos = entry->msi_attrib.pos;
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u16 data;
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pci_read_config_dword(dev, msi_lower_address_reg(pos),
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&msg->address_lo);
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if (entry->msi_attrib.is_64) {
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pci_read_config_dword(dev, msi_upper_address_reg(pos),
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&msg->address_hi);
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pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
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} else {
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msg->address_hi = 0;
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2007-10-03 11:15:11 -07:00
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pci_read_config_word(dev, msi_data_reg(pos, 0), &data);
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2006-10-04 02:16:33 -07:00
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}
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msg->data = data;
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break;
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}
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case PCI_CAP_ID_MSIX:
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{
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void __iomem *base;
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base = entry->mask_base +
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entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
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msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
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msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
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msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET);
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break;
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}
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default:
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BUG();
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}
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}
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2005-04-16 15:20:36 -07:00
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2006-10-04 02:16:59 -07:00
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void write_msi_msg(unsigned int irq, struct msi_msg *msg)
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2006-10-04 02:16:33 -07:00
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{
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2007-01-28 12:52:03 -07:00
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struct msi_desc *entry = get_irq_msi(irq);
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2005-04-16 15:20:36 -07:00
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switch (entry->msi_attrib.type) {
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case PCI_CAP_ID_MSI:
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{
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2006-10-04 02:16:33 -07:00
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struct pci_dev *dev = entry->dev;
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int pos = entry->msi_attrib.pos;
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pci_write_config_dword(dev, msi_lower_address_reg(pos),
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msg->address_lo);
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if (entry->msi_attrib.is_64) {
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pci_write_config_dword(dev, msi_upper_address_reg(pos),
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msg->address_hi);
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pci_write_config_word(dev, msi_data_reg(pos, 1),
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msg->data);
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} else {
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pci_write_config_word(dev, msi_data_reg(pos, 0),
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msg->data);
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}
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2005-04-16 15:20:36 -07:00
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break;
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}
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case PCI_CAP_ID_MSIX:
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{
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2006-10-04 02:16:33 -07:00
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void __iomem *base;
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base = entry->mask_base +
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entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
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writel(msg->address_lo,
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base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
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writel(msg->address_hi,
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base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
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writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET);
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2005-04-16 15:20:36 -07:00
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break;
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}
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default:
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2006-10-04 02:16:33 -07:00
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BUG();
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2005-04-16 15:20:36 -07:00
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}
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2007-03-08 13:04:57 -07:00
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entry->msg = *msg;
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2005-04-16 15:20:36 -07:00
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}
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2006-10-04 02:16:33 -07:00
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2006-10-04 02:16:59 -07:00
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void mask_msi_irq(unsigned int irq)
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2005-04-16 15:20:36 -07:00
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{
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2006-10-04 02:16:41 -07:00
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msi_set_mask_bit(irq, 1);
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2007-03-30 11:54:08 -07:00
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msix_flush_writes(irq);
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2005-04-16 15:20:36 -07:00
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}
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2006-10-04 02:16:59 -07:00
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void unmask_msi_irq(unsigned int irq)
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2005-04-16 15:20:36 -07:00
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{
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2006-10-04 02:16:41 -07:00
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msi_set_mask_bit(irq, 0);
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2007-03-30 11:54:08 -07:00
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msix_flush_writes(irq);
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2005-04-16 15:20:36 -07:00
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}
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2007-04-18 02:39:22 -07:00
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static int msi_free_irqs(struct pci_dev* dev);
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2007-01-17 21:50:05 -07:00
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2005-04-16 15:20:36 -07:00
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static struct msi_desc* alloc_msi_entry(void)
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{
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struct msi_desc *entry;
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2007-03-22 03:51:36 -07:00
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entry = kzalloc(sizeof(struct msi_desc), GFP_KERNEL);
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2005-04-16 15:20:36 -07:00
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if (!entry)
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return NULL;
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2007-04-05 00:19:10 -07:00
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INIT_LIST_HEAD(&entry->list);
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entry->irq = 0;
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2005-04-16 15:20:36 -07:00
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entry->dev = NULL;
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return entry;
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}
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2007-10-25 01:16:30 -07:00
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static void pci_intx_for_msi(struct pci_dev *dev, int enable)
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{
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if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
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pci_intx(dev, enable);
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}
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2006-02-08 02:11:38 -07:00
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#ifdef CONFIG_PM
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2007-01-25 01:34:08 -07:00
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static void __pci_restore_msi_state(struct pci_dev *dev)
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2006-02-08 02:11:38 -07:00
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{
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2007-03-08 13:04:57 -07:00
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int pos;
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2006-02-08 02:11:38 -07:00
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u16 control;
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2007-03-08 13:04:57 -07:00
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struct msi_desc *entry;
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2006-02-08 02:11:38 -07:00
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2007-03-05 01:30:10 -07:00
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if (!dev->msi_enabled)
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return;
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2007-03-08 13:04:57 -07:00
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entry = get_irq_msi(dev->irq);
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pos = entry->msi_attrib.pos;
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2006-02-08 02:11:38 -07:00
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2007-10-25 01:16:30 -07:00
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pci_intx_for_msi(dev, 0);
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2007-03-05 01:30:10 -07:00
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msi_set_enable(dev, 0);
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2007-03-08 13:04:57 -07:00
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write_msi_msg(dev->irq, &entry->msg);
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if (entry->msi_attrib.maskbit)
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msi_set_mask_bit(dev->irq, entry->msi_attrib.masked);
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pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
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control &= ~(PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE);
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if (entry->msi_attrib.maskbit || !entry->msi_attrib.masked)
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control |= PCI_MSI_FLAGS_ENABLE;
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2006-02-08 02:11:38 -07:00
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pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
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2007-01-25 01:34:08 -07:00
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}
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static void __pci_restore_msix_state(struct pci_dev *dev)
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2006-02-08 02:11:38 -07:00
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{
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int pos;
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struct msi_desc *entry;
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2007-03-08 13:04:57 -07:00
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u16 control;
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2006-02-08 02:11:38 -07:00
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2007-01-28 12:42:52 -07:00
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if (!dev->msix_enabled)
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return;
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2006-02-08 02:11:38 -07:00
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/* route the table */
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2007-10-25 01:16:30 -07:00
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pci_intx_for_msi(dev, 0);
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2007-03-05 01:30:10 -07:00
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msix_set_enable(dev, 0);
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2006-02-08 02:11:38 -07:00
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2007-04-05 00:19:10 -07:00
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list_for_each_entry(entry, &dev->msi_list, list) {
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write_msi_msg(entry->irq, &entry->msg);
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msi_set_mask_bit(entry->irq, entry->msi_attrib.masked);
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2006-02-08 02:11:38 -07:00
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}
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2007-04-05 00:19:12 -07:00
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BUG_ON(list_empty(&dev->msi_list));
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entry = list_entry(dev->msi_list.next, struct msi_desc, list);
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2007-04-05 00:19:10 -07:00
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pos = entry->msi_attrib.pos;
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2007-03-08 13:04:57 -07:00
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pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
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|
|
|
control &= ~PCI_MSIX_FLAGS_MASKALL;
|
|
|
|
control |= PCI_MSIX_FLAGS_ENABLE;
|
|
|
|
pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
|
2006-02-08 02:11:38 -07:00
|
|
|
}
|
2007-01-25 01:34:08 -07:00
|
|
|
|
|
|
|
void pci_restore_msi_state(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
__pci_restore_msi_state(dev);
|
|
|
|
__pci_restore_msix_state(dev);
|
|
|
|
}
|
2007-01-17 21:50:05 -07:00
|
|
|
#endif /* CONFIG_PM */
|
2006-02-08 02:11:38 -07:00
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
/**
|
|
|
|
* msi_capability_init - configure device's MSI capability structure
|
|
|
|
* @dev: pointer to the pci_dev data structure of MSI device function
|
|
|
|
*
|
2005-05-03 17:38:30 -07:00
|
|
|
* Setup the MSI capability structure of device function with a single
|
2006-10-04 02:16:41 -07:00
|
|
|
* MSI irq, regardless of device function is capable of handling
|
2005-04-16 15:20:36 -07:00
|
|
|
* multiple messages. A return of zero indicates the successful setup
|
2006-10-04 02:16:41 -07:00
|
|
|
* of an entry zero with the new MSI irq or non-zero for otherwise.
|
2005-04-16 15:20:36 -07:00
|
|
|
**/
|
|
|
|
static int msi_capability_init(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
struct msi_desc *entry;
|
2007-04-18 02:39:21 -07:00
|
|
|
int pos, ret;
|
2005-04-16 15:20:36 -07:00
|
|
|
u16 control;
|
|
|
|
|
2007-03-05 01:30:10 -07:00
|
|
|
msi_set_enable(dev, 0); /* Ensure msi is disabled as I set it up */
|
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
|
|
|
|
pci_read_config_word(dev, msi_control_reg(pos), &control);
|
|
|
|
/* MSI Entry Initialization */
|
2007-01-28 12:56:37 -07:00
|
|
|
entry = alloc_msi_entry();
|
|
|
|
if (!entry)
|
|
|
|
return -ENOMEM;
|
2006-10-04 02:16:41 -07:00
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
entry->msi_attrib.type = PCI_CAP_ID_MSI;
|
2006-10-04 02:16:33 -07:00
|
|
|
entry->msi_attrib.is_64 = is_64bit_address(control);
|
2005-04-16 15:20:36 -07:00
|
|
|
entry->msi_attrib.entry_nr = 0;
|
|
|
|
entry->msi_attrib.maskbit = is_mask_bit_support(control);
|
2007-03-08 13:04:57 -07:00
|
|
|
entry->msi_attrib.masked = 1;
|
2006-10-04 02:16:41 -07:00
|
|
|
entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
|
2006-10-04 02:16:33 -07:00
|
|
|
entry->msi_attrib.pos = pos;
|
2005-04-16 15:20:36 -07:00
|
|
|
if (is_mask_bit_support(control)) {
|
|
|
|
entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos,
|
|
|
|
is_64bit_address(control));
|
|
|
|
}
|
2006-10-04 02:16:59 -07:00
|
|
|
entry->dev = dev;
|
|
|
|
if (entry->msi_attrib.maskbit) {
|
|
|
|
unsigned int maskbits, temp;
|
|
|
|
/* All MSIs are unmasked by default, Mask them all */
|
|
|
|
pci_read_config_dword(dev,
|
|
|
|
msi_mask_bits_reg(pos, is_64bit_address(control)),
|
|
|
|
&maskbits);
|
|
|
|
temp = (1 << multi_msi_capable(control));
|
|
|
|
temp = ((temp - 1) & ~temp);
|
|
|
|
maskbits |= temp;
|
|
|
|
pci_write_config_dword(dev,
|
|
|
|
msi_mask_bits_reg(pos, is_64bit_address(control)),
|
|
|
|
maskbits);
|
|
|
|
}
|
2007-06-01 00:46:32 -07:00
|
|
|
list_add_tail(&entry->list, &dev->msi_list);
|
MSI: Give archs the option to allocate all MSI/Xs at once.
This patch introduces an optional function, arch_setup_msi_irqs(),
(note the plural) which gives an arch the opportunity to do per-device
setup for MSI/X and then allocate all the requested MSI/Xs at once.
If that's not required by the arch, the default version simply calls
arch_setup_msi_irq() for each MSI irq required.
arch_setup_msi_irqs() is passed a pdev, attached to the pdev is a list
of msi_descs with irq == 0, it is up to the arch to connect these up to
an irq (via set_irq_msi()) or return an error. For convenience the number
of vectors and the type are passed also.
All msi_descs with irq != 0 are considered allocated, and the arch
teardown routine will be called on them when necessary.
The existing semantics of pci_enable_msix() are that if the requested
number of irqs can not be allocated, the maximum number that _could_ be
allocated is returned. To support that, we define that in case of an
error from arch_setup_msi_irqs(), the number of msi_descs with irq != 0
are considered allocated, and are counted toward the "max that could be
allocated".
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2007-04-18 02:39:21 -07:00
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
/* Configure MSI capability structure */
|
MSI: Give archs the option to allocate all MSI/Xs at once.
This patch introduces an optional function, arch_setup_msi_irqs(),
(note the plural) which gives an arch the opportunity to do per-device
setup for MSI/X and then allocate all the requested MSI/Xs at once.
If that's not required by the arch, the default version simply calls
arch_setup_msi_irq() for each MSI irq required.
arch_setup_msi_irqs() is passed a pdev, attached to the pdev is a list
of msi_descs with irq == 0, it is up to the arch to connect these up to
an irq (via set_irq_msi()) or return an error. For convenience the number
of vectors and the type are passed also.
All msi_descs with irq != 0 are considered allocated, and the arch
teardown routine will be called on them when necessary.
The existing semantics of pci_enable_msix() are that if the requested
number of irqs can not be allocated, the maximum number that _could_ be
allocated is returned. To support that, we define that in case of an
error from arch_setup_msi_irqs(), the number of msi_descs with irq != 0
are considered allocated, and are counted toward the "max that could be
allocated".
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2007-04-18 02:39:21 -07:00
|
|
|
ret = arch_setup_msi_irqs(dev, 1, PCI_CAP_ID_MSI);
|
2007-04-18 02:39:21 -07:00
|
|
|
if (ret) {
|
2007-04-18 02:39:22 -07:00
|
|
|
msi_free_irqs(dev);
|
2007-04-18 02:39:21 -07:00
|
|
|
return ret;
|
2006-04-10 19:17:48 -07:00
|
|
|
}
|
2007-01-28 12:56:37 -07:00
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
/* Set MSI enabled bits */
|
2007-10-25 01:16:30 -07:00
|
|
|
pci_intx_for_msi(dev, 0);
|
2007-03-05 01:30:10 -07:00
|
|
|
msi_set_enable(dev, 1);
|
|
|
|
dev->msi_enabled = 1;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-04-18 02:39:21 -07:00
|
|
|
dev->irq = entry->irq;
|
2005-04-16 15:20:36 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* msix_capability_init - configure device's MSI-X capability
|
|
|
|
* @dev: pointer to the pci_dev data structure of MSI-X device function
|
2005-10-23 11:57:38 -07:00
|
|
|
* @entries: pointer to an array of struct msix_entry entries
|
|
|
|
* @nvec: number of @entries
|
2005-04-16 15:20:36 -07:00
|
|
|
*
|
2005-05-03 17:38:30 -07:00
|
|
|
* Setup the MSI-X capability structure of device function with a
|
2006-10-04 02:16:41 -07:00
|
|
|
* single MSI-X irq. A return of zero indicates the successful setup of
|
|
|
|
* requested MSI-X entries with allocated irqs or non-zero for otherwise.
|
2005-04-16 15:20:36 -07:00
|
|
|
**/
|
|
|
|
static int msix_capability_init(struct pci_dev *dev,
|
|
|
|
struct msix_entry *entries, int nvec)
|
|
|
|
{
|
2007-04-05 00:19:10 -07:00
|
|
|
struct msi_desc *entry;
|
MSI: Give archs the option to allocate all MSI/Xs at once.
This patch introduces an optional function, arch_setup_msi_irqs(),
(note the plural) which gives an arch the opportunity to do per-device
setup for MSI/X and then allocate all the requested MSI/Xs at once.
If that's not required by the arch, the default version simply calls
arch_setup_msi_irq() for each MSI irq required.
arch_setup_msi_irqs() is passed a pdev, attached to the pdev is a list
of msi_descs with irq == 0, it is up to the arch to connect these up to
an irq (via set_irq_msi()) or return an error. For convenience the number
of vectors and the type are passed also.
All msi_descs with irq != 0 are considered allocated, and the arch
teardown routine will be called on them when necessary.
The existing semantics of pci_enable_msix() are that if the requested
number of irqs can not be allocated, the maximum number that _could_ be
allocated is returned. To support that, we define that in case of an
error from arch_setup_msi_irqs(), the number of msi_descs with irq != 0
are considered allocated, and are counted toward the "max that could be
allocated".
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2007-04-18 02:39:21 -07:00
|
|
|
int pos, i, j, nr_entries, ret;
|
2006-02-17 00:58:29 -07:00
|
|
|
unsigned long phys_addr;
|
|
|
|
u32 table_offset;
|
2005-04-16 15:20:36 -07:00
|
|
|
u16 control;
|
|
|
|
u8 bir;
|
|
|
|
void __iomem *base;
|
|
|
|
|
2007-03-05 01:30:10 -07:00
|
|
|
msix_set_enable(dev, 0);/* Ensure msix is disabled as I set it up */
|
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
|
|
|
|
/* Request & Map MSI-X table region */
|
|
|
|
pci_read_config_word(dev, msi_control_reg(pos), &control);
|
|
|
|
nr_entries = multi_msix_capable(control);
|
2006-02-17 00:58:29 -07:00
|
|
|
|
|
|
|
pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset);
|
2005-04-16 15:20:36 -07:00
|
|
|
bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
|
2006-02-17 00:58:29 -07:00
|
|
|
table_offset &= ~PCI_MSIX_FLAGS_BIRMASK;
|
|
|
|
phys_addr = pci_resource_start (dev, bir) + table_offset;
|
2005-04-16 15:20:36 -07:00
|
|
|
base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
|
|
|
|
if (base == NULL)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
/* MSI-X Table Initialization */
|
|
|
|
for (i = 0; i < nvec; i++) {
|
2007-01-28 12:56:37 -07:00
|
|
|
entry = alloc_msi_entry();
|
|
|
|
if (!entry)
|
2005-04-16 15:20:36 -07:00
|
|
|
break;
|
|
|
|
|
|
|
|
j = entries[i].entry;
|
|
|
|
entry->msi_attrib.type = PCI_CAP_ID_MSIX;
|
2006-10-04 02:16:33 -07:00
|
|
|
entry->msi_attrib.is_64 = 1;
|
2005-04-16 15:20:36 -07:00
|
|
|
entry->msi_attrib.entry_nr = j;
|
|
|
|
entry->msi_attrib.maskbit = 1;
|
2007-03-08 13:04:57 -07:00
|
|
|
entry->msi_attrib.masked = 1;
|
2006-10-04 02:16:41 -07:00
|
|
|
entry->msi_attrib.default_irq = dev->irq;
|
2006-10-04 02:16:33 -07:00
|
|
|
entry->msi_attrib.pos = pos;
|
2005-04-16 15:20:36 -07:00
|
|
|
entry->dev = dev;
|
|
|
|
entry->mask_base = base;
|
2007-01-28 12:56:37 -07:00
|
|
|
|
2007-06-01 00:46:32 -07:00
|
|
|
list_add_tail(&entry->list, &dev->msi_list);
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
MSI: Give archs the option to allocate all MSI/Xs at once.
This patch introduces an optional function, arch_setup_msi_irqs(),
(note the plural) which gives an arch the opportunity to do per-device
setup for MSI/X and then allocate all the requested MSI/Xs at once.
If that's not required by the arch, the default version simply calls
arch_setup_msi_irq() for each MSI irq required.
arch_setup_msi_irqs() is passed a pdev, attached to the pdev is a list
of msi_descs with irq == 0, it is up to the arch to connect these up to
an irq (via set_irq_msi()) or return an error. For convenience the number
of vectors and the type are passed also.
All msi_descs with irq != 0 are considered allocated, and the arch
teardown routine will be called on them when necessary.
The existing semantics of pci_enable_msix() are that if the requested
number of irqs can not be allocated, the maximum number that _could_ be
allocated is returned. To support that, we define that in case of an
error from arch_setup_msi_irqs(), the number of msi_descs with irq != 0
are considered allocated, and are counted toward the "max that could be
allocated".
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2007-04-18 02:39:21 -07:00
|
|
|
|
|
|
|
ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
|
|
|
|
if (ret) {
|
|
|
|
int avail = 0;
|
|
|
|
list_for_each_entry(entry, &dev->msi_list, list) {
|
|
|
|
if (entry->irq != 0) {
|
|
|
|
avail++;
|
|
|
|
}
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
MSI: Give archs the option to allocate all MSI/Xs at once.
This patch introduces an optional function, arch_setup_msi_irqs(),
(note the plural) which gives an arch the opportunity to do per-device
setup for MSI/X and then allocate all the requested MSI/Xs at once.
If that's not required by the arch, the default version simply calls
arch_setup_msi_irq() for each MSI irq required.
arch_setup_msi_irqs() is passed a pdev, attached to the pdev is a list
of msi_descs with irq == 0, it is up to the arch to connect these up to
an irq (via set_irq_msi()) or return an error. For convenience the number
of vectors and the type are passed also.
All msi_descs with irq != 0 are considered allocated, and the arch
teardown routine will be called on them when necessary.
The existing semantics of pci_enable_msix() are that if the requested
number of irqs can not be allocated, the maximum number that _could_ be
allocated is returned. To support that, we define that in case of an
error from arch_setup_msi_irqs(), the number of msi_descs with irq != 0
are considered allocated, and are counted toward the "max that could be
allocated".
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2007-04-18 02:39:21 -07:00
|
|
|
|
2007-04-18 02:39:22 -07:00
|
|
|
msi_free_irqs(dev);
|
|
|
|
|
2006-10-04 02:16:35 -07:00
|
|
|
/* If we had some success report the number of irqs
|
|
|
|
* we succeeded in setting up.
|
|
|
|
*/
|
MSI: Give archs the option to allocate all MSI/Xs at once.
This patch introduces an optional function, arch_setup_msi_irqs(),
(note the plural) which gives an arch the opportunity to do per-device
setup for MSI/X and then allocate all the requested MSI/Xs at once.
If that's not required by the arch, the default version simply calls
arch_setup_msi_irq() for each MSI irq required.
arch_setup_msi_irqs() is passed a pdev, attached to the pdev is a list
of msi_descs with irq == 0, it is up to the arch to connect these up to
an irq (via set_irq_msi()) or return an error. For convenience the number
of vectors and the type are passed also.
All msi_descs with irq != 0 are considered allocated, and the arch
teardown routine will be called on them when necessary.
The existing semantics of pci_enable_msix() are that if the requested
number of irqs can not be allocated, the maximum number that _could_ be
allocated is returned. To support that, we define that in case of an
error from arch_setup_msi_irqs(), the number of msi_descs with irq != 0
are considered allocated, and are counted toward the "max that could be
allocated".
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2007-04-18 02:39:21 -07:00
|
|
|
if (avail == 0)
|
|
|
|
avail = ret;
|
2006-10-04 02:16:35 -07:00
|
|
|
return avail;
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
MSI: Give archs the option to allocate all MSI/Xs at once.
This patch introduces an optional function, arch_setup_msi_irqs(),
(note the plural) which gives an arch the opportunity to do per-device
setup for MSI/X and then allocate all the requested MSI/Xs at once.
If that's not required by the arch, the default version simply calls
arch_setup_msi_irq() for each MSI irq required.
arch_setup_msi_irqs() is passed a pdev, attached to the pdev is a list
of msi_descs with irq == 0, it is up to the arch to connect these up to
an irq (via set_irq_msi()) or return an error. For convenience the number
of vectors and the type are passed also.
All msi_descs with irq != 0 are considered allocated, and the arch
teardown routine will be called on them when necessary.
The existing semantics of pci_enable_msix() are that if the requested
number of irqs can not be allocated, the maximum number that _could_ be
allocated is returned. To support that, we define that in case of an
error from arch_setup_msi_irqs(), the number of msi_descs with irq != 0
are considered allocated, and are counted toward the "max that could be
allocated".
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2007-04-18 02:39:21 -07:00
|
|
|
|
|
|
|
i = 0;
|
|
|
|
list_for_each_entry(entry, &dev->msi_list, list) {
|
|
|
|
entries[i].vector = entry->irq;
|
|
|
|
set_irq_msi(entry->irq, entry);
|
|
|
|
i++;
|
|
|
|
}
|
2005-04-16 15:20:36 -07:00
|
|
|
/* Set MSI-X enabled bits */
|
2007-10-25 01:16:30 -07:00
|
|
|
pci_intx_for_msi(dev, 0);
|
2007-03-05 01:30:10 -07:00
|
|
|
msix_set_enable(dev, 1);
|
|
|
|
dev->msix_enabled = 1;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2006-08-30 22:55:07 -07:00
|
|
|
/**
|
2007-04-05 00:19:07 -07:00
|
|
|
* pci_msi_check_device - check whether MSI may be enabled on a device
|
2006-08-30 22:55:07 -07:00
|
|
|
* @dev: pointer to the pci_dev data structure of MSI device function
|
2007-04-05 00:19:08 -07:00
|
|
|
* @nvec: how many MSIs have been requested ?
|
2007-03-22 03:51:39 -07:00
|
|
|
* @type: are we checking for MSI or MSI-X ?
|
2006-08-30 22:55:07 -07:00
|
|
|
*
|
2006-10-05 01:24:31 -07:00
|
|
|
* Look at global flags, the device itself, and its parent busses
|
2007-04-05 00:19:07 -07:00
|
|
|
* to determine if MSI/-X are supported for the device. If MSI/-X is
|
|
|
|
* supported return 0, else return an error code.
|
2006-08-30 22:55:07 -07:00
|
|
|
**/
|
2007-04-05 00:19:08 -07:00
|
|
|
static int pci_msi_check_device(struct pci_dev* dev, int nvec, int type)
|
2006-08-30 22:55:07 -07:00
|
|
|
{
|
|
|
|
struct pci_bus *bus;
|
2007-04-05 00:19:08 -07:00
|
|
|
int ret;
|
2006-08-30 22:55:07 -07:00
|
|
|
|
2006-10-05 01:24:31 -07:00
|
|
|
/* MSI must be globally enabled and supported by the device */
|
2006-08-30 22:55:07 -07:00
|
|
|
if (!pci_msi_enable || !dev || dev->no_msi)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2007-04-05 00:19:12 -07:00
|
|
|
/*
|
|
|
|
* You can't ask to have 0 or less MSIs configured.
|
|
|
|
* a) it's stupid ..
|
|
|
|
* b) the list manipulation code assumes nvec >= 1.
|
|
|
|
*/
|
|
|
|
if (nvec < 1)
|
|
|
|
return -ERANGE;
|
|
|
|
|
2006-10-05 01:24:31 -07:00
|
|
|
/* Any bridge which does NOT route MSI transactions from it's
|
|
|
|
* secondary bus to it's primary bus must set NO_MSI flag on
|
|
|
|
* the secondary pci_bus.
|
|
|
|
* We expect only arch-specific PCI host bus controller driver
|
|
|
|
* or quirks for specific PCI bridges to be setting NO_MSI.
|
|
|
|
*/
|
2006-08-30 22:55:07 -07:00
|
|
|
for (bus = dev->bus; bus; bus = bus->parent)
|
|
|
|
if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2007-04-05 00:19:08 -07:00
|
|
|
ret = arch_msi_check_device(dev, nvec, type);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2007-03-22 03:51:39 -07:00
|
|
|
if (!pci_find_capability(dev, type))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2006-08-30 22:55:07 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
/**
|
|
|
|
* pci_enable_msi - configure device's MSI capability structure
|
|
|
|
* @dev: pointer to the pci_dev data structure of MSI device function
|
|
|
|
*
|
|
|
|
* Setup the MSI capability structure of device function with
|
2006-10-04 02:16:41 -07:00
|
|
|
* a single MSI irq upon its software driver call to request for
|
2005-04-16 15:20:36 -07:00
|
|
|
* MSI mode enabled on its hardware device function. A return of zero
|
|
|
|
* indicates the successful setup of an entry zero with the new MSI
|
2006-10-04 02:16:41 -07:00
|
|
|
* irq or non-zero for otherwise.
|
2005-04-16 15:20:36 -07:00
|
|
|
**/
|
|
|
|
int pci_enable_msi(struct pci_dev* dev)
|
|
|
|
{
|
2007-03-22 03:51:39 -07:00
|
|
|
int status;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-04-05 00:19:08 -07:00
|
|
|
status = pci_msi_check_device(dev, 1, PCI_CAP_ID_MSI);
|
|
|
|
if (status)
|
|
|
|
return status;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-01-28 12:42:52 -07:00
|
|
|
WARN_ON(!!dev->msi_enabled);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2006-10-04 02:16:41 -07:00
|
|
|
/* Check whether driver already requested for MSI-X irqs */
|
2007-03-05 01:30:10 -07:00
|
|
|
if (dev->msix_enabled) {
|
|
|
|
printk(KERN_INFO "PCI: %s: Can't enable MSI. "
|
|
|
|
"Device already has MSI-X enabled\n",
|
|
|
|
pci_name(dev));
|
|
|
|
return -EINVAL;
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
status = msi_capability_init(dev);
|
|
|
|
return status;
|
|
|
|
}
|
2007-03-22 03:51:34 -07:00
|
|
|
EXPORT_SYMBOL(pci_enable_msi);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
void pci_disable_msi(struct pci_dev* dev)
|
|
|
|
{
|
|
|
|
struct msi_desc *entry;
|
2007-03-05 01:30:10 -07:00
|
|
|
int default_irq;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-03-22 03:51:39 -07:00
|
|
|
if (!pci_msi_enable || !dev || !dev->msi_enabled)
|
2007-01-28 12:42:52 -07:00
|
|
|
return;
|
|
|
|
|
2007-03-05 01:30:10 -07:00
|
|
|
msi_set_enable(dev, 0);
|
2007-10-25 01:16:30 -07:00
|
|
|
pci_intx_for_msi(dev, 1);
|
2007-03-05 01:30:10 -07:00
|
|
|
dev->msi_enabled = 0;
|
2006-10-04 02:16:31 -07:00
|
|
|
|
2007-04-05 00:19:12 -07:00
|
|
|
BUG_ON(list_empty(&dev->msi_list));
|
|
|
|
entry = list_entry(dev->msi_list.next, struct msi_desc, list);
|
|
|
|
if (!entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) {
|
2005-04-16 15:20:36 -07:00
|
|
|
return;
|
|
|
|
}
|
2007-03-22 03:51:27 -07:00
|
|
|
|
|
|
|
default_irq = entry->msi_attrib.default_irq;
|
2007-04-18 02:39:22 -07:00
|
|
|
msi_free_irqs(dev);
|
2007-03-22 03:51:27 -07:00
|
|
|
|
|
|
|
/* Restore dev->irq to its default pin-assertion irq */
|
|
|
|
dev->irq = default_irq;
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
2007-03-22 03:51:34 -07:00
|
|
|
EXPORT_SYMBOL(pci_disable_msi);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-04-18 02:39:22 -07:00
|
|
|
static int msi_free_irqs(struct pci_dev* dev)
|
2005-04-16 15:20:36 -07:00
|
|
|
{
|
2007-04-18 02:39:22 -07:00
|
|
|
struct msi_desc *entry, *tmp;
|
2007-03-22 03:51:34 -07:00
|
|
|
|
2007-05-11 13:26:44 -07:00
|
|
|
list_for_each_entry(entry, &dev->msi_list, list) {
|
|
|
|
if (entry->irq)
|
|
|
|
BUG_ON(irq_has_action(entry->irq));
|
|
|
|
}
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-04-18 02:39:22 -07:00
|
|
|
arch_teardown_msi_irqs(dev);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-04-18 02:39:22 -07:00
|
|
|
list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) {
|
|
|
|
if (entry->msi_attrib.type == PCI_CAP_ID_MSIX) {
|
|
|
|
writel(1, entry->mask_base + entry->msi_attrib.entry_nr
|
|
|
|
* PCI_MSIX_ENTRY_SIZE
|
|
|
|
+ PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET);
|
2007-06-01 00:46:33 -07:00
|
|
|
|
|
|
|
if (list_is_last(&entry->list, &dev->msi_list))
|
|
|
|
iounmap(entry->mask_base);
|
2007-04-18 02:39:22 -07:00
|
|
|
}
|
|
|
|
list_del(&entry->list);
|
|
|
|
kfree(entry);
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_enable_msix - configure device's MSI-X capability structure
|
|
|
|
* @dev: pointer to the pci_dev data structure of MSI-X device function
|
2005-06-06 23:07:46 -07:00
|
|
|
* @entries: pointer to an array of MSI-X entries
|
2006-10-04 02:16:41 -07:00
|
|
|
* @nvec: number of MSI-X irqs requested for allocation by device driver
|
2005-04-16 15:20:36 -07:00
|
|
|
*
|
|
|
|
* Setup the MSI-X capability structure of device function with the number
|
2006-10-04 02:16:41 -07:00
|
|
|
* of requested irqs upon its software driver call to request for
|
2005-04-16 15:20:36 -07:00
|
|
|
* MSI-X mode enabled on its hardware device function. A return of zero
|
|
|
|
* indicates the successful configuration of MSI-X capability structure
|
2006-10-04 02:16:41 -07:00
|
|
|
* with new allocated MSI-X irqs. A return of < 0 indicates a failure.
|
2005-04-16 15:20:36 -07:00
|
|
|
* Or a return of > 0 indicates that driver request is exceeding the number
|
2006-10-04 02:16:41 -07:00
|
|
|
* of irqs available. Driver should use the returned value to re-send
|
2005-04-16 15:20:36 -07:00
|
|
|
* its request.
|
|
|
|
**/
|
|
|
|
int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec)
|
|
|
|
{
|
2006-10-04 02:16:35 -07:00
|
|
|
int status, pos, nr_entries;
|
2007-01-28 12:42:52 -07:00
|
|
|
int i, j;
|
2005-04-16 15:20:36 -07:00
|
|
|
u16 control;
|
|
|
|
|
2007-04-05 00:19:08 -07:00
|
|
|
if (!entries)
|
2005-04-16 15:20:36 -07:00
|
|
|
return -EINVAL;
|
|
|
|
|
2007-04-05 00:19:08 -07:00
|
|
|
status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX);
|
|
|
|
if (status)
|
|
|
|
return status;
|
|
|
|
|
2006-01-14 00:34:53 -07:00
|
|
|
pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
|
2005-04-16 15:20:36 -07:00
|
|
|
pci_read_config_word(dev, msi_control_reg(pos), &control);
|
|
|
|
nr_entries = multi_msix_capable(control);
|
|
|
|
if (nvec > nr_entries)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
/* Check for any invalid entries */
|
|
|
|
for (i = 0; i < nvec; i++) {
|
|
|
|
if (entries[i].entry >= nr_entries)
|
|
|
|
return -EINVAL; /* invalid entry */
|
|
|
|
for (j = i + 1; j < nvec; j++) {
|
|
|
|
if (entries[i].entry == entries[j].entry)
|
|
|
|
return -EINVAL; /* duplicate entry */
|
|
|
|
}
|
|
|
|
}
|
2007-01-28 12:42:52 -07:00
|
|
|
WARN_ON(!!dev->msix_enabled);
|
2006-10-04 02:16:31 -07:00
|
|
|
|
2006-10-04 02:16:41 -07:00
|
|
|
/* Check whether driver already requested for MSI irq */
|
2007-03-05 01:30:10 -07:00
|
|
|
if (dev->msi_enabled) {
|
2005-04-16 15:20:36 -07:00
|
|
|
printk(KERN_INFO "PCI: %s: Can't enable MSI-X. "
|
2006-10-04 02:16:41 -07:00
|
|
|
"Device already has an MSI irq assigned\n",
|
2005-04-16 15:20:36 -07:00
|
|
|
pci_name(dev));
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
status = msix_capability_init(dev, entries, nvec);
|
|
|
|
return status;
|
|
|
|
}
|
2007-03-22 03:51:34 -07:00
|
|
|
EXPORT_SYMBOL(pci_enable_msix);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-03-22 03:51:33 -07:00
|
|
|
static void msix_free_all_irqs(struct pci_dev *dev)
|
2005-04-16 15:20:36 -07:00
|
|
|
{
|
2007-04-18 02:39:22 -07:00
|
|
|
msi_free_irqs(dev);
|
2007-03-22 03:51:33 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
void pci_disable_msix(struct pci_dev* dev)
|
|
|
|
{
|
2007-03-22 03:51:39 -07:00
|
|
|
if (!pci_msi_enable || !dev || !dev->msix_enabled)
|
2007-01-28 12:42:52 -07:00
|
|
|
return;
|
|
|
|
|
2007-03-05 01:30:10 -07:00
|
|
|
msix_set_enable(dev, 0);
|
2007-10-25 01:16:30 -07:00
|
|
|
pci_intx_for_msi(dev, 1);
|
2007-03-05 01:30:10 -07:00
|
|
|
dev->msix_enabled = 0;
|
2006-10-04 02:16:31 -07:00
|
|
|
|
2007-03-22 03:51:33 -07:00
|
|
|
msix_free_all_irqs(dev);
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
2007-03-22 03:51:34 -07:00
|
|
|
EXPORT_SYMBOL(pci_disable_msix);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
/**
|
2006-10-04 02:16:41 -07:00
|
|
|
* msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
|
2005-04-16 15:20:36 -07:00
|
|
|
* @dev: pointer to the pci_dev data structure of MSI(X) device function
|
|
|
|
*
|
2005-05-03 17:38:30 -07:00
|
|
|
* Being called during hotplug remove, from which the device function
|
2006-10-04 02:16:41 -07:00
|
|
|
* is hot-removed. All previous assigned MSI/MSI-X irqs, if
|
2005-04-16 15:20:36 -07:00
|
|
|
* allocated for this device function, are reclaimed to unused state,
|
|
|
|
* which may be used later on.
|
|
|
|
**/
|
|
|
|
void msi_remove_pci_irq_vectors(struct pci_dev* dev)
|
|
|
|
{
|
|
|
|
if (!pci_msi_enable || !dev)
|
|
|
|
return;
|
|
|
|
|
2007-04-18 02:39:22 -07:00
|
|
|
if (dev->msi_enabled)
|
|
|
|
msi_free_irqs(dev);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-03-22 03:51:33 -07:00
|
|
|
if (dev->msix_enabled)
|
|
|
|
msix_free_all_irqs(dev);
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
2006-03-05 22:33:34 -07:00
|
|
|
void pci_no_msi(void)
|
|
|
|
{
|
|
|
|
pci_msi_enable = 0;
|
|
|
|
}
|
2007-04-05 00:19:08 -07:00
|
|
|
|
2007-04-05 00:19:10 -07:00
|
|
|
void pci_msi_init_pci_dev(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
INIT_LIST_HEAD(&dev->msi_list);
|
|
|
|
}
|
|
|
|
|
2007-04-05 00:19:08 -07:00
|
|
|
|
|
|
|
/* Arch hooks */
|
|
|
|
|
|
|
|
int __attribute__ ((weak))
|
|
|
|
arch_msi_check_device(struct pci_dev* dev, int nvec, int type)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
MSI: Give archs the option to allocate all MSI/Xs at once.
This patch introduces an optional function, arch_setup_msi_irqs(),
(note the plural) which gives an arch the opportunity to do per-device
setup for MSI/X and then allocate all the requested MSI/Xs at once.
If that's not required by the arch, the default version simply calls
arch_setup_msi_irq() for each MSI irq required.
arch_setup_msi_irqs() is passed a pdev, attached to the pdev is a list
of msi_descs with irq == 0, it is up to the arch to connect these up to
an irq (via set_irq_msi()) or return an error. For convenience the number
of vectors and the type are passed also.
All msi_descs with irq != 0 are considered allocated, and the arch
teardown routine will be called on them when necessary.
The existing semantics of pci_enable_msix() are that if the requested
number of irqs can not be allocated, the maximum number that _could_ be
allocated is returned. To support that, we define that in case of an
error from arch_setup_msi_irqs(), the number of msi_descs with irq != 0
are considered allocated, and are counted toward the "max that could be
allocated".
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2007-04-18 02:39:21 -07:00
|
|
|
int __attribute__ ((weak))
|
|
|
|
arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *entry)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int __attribute__ ((weak))
|
|
|
|
arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
|
|
|
|
{
|
|
|
|
struct msi_desc *entry;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
list_for_each_entry(entry, &dev->msi_list, list) {
|
|
|
|
ret = arch_setup_msi_irq(dev, entry);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2007-04-18 02:39:22 -07:00
|
|
|
|
|
|
|
void __attribute__ ((weak)) arch_teardown_msi_irq(unsigned int irq)
|
|
|
|
{
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
void __attribute__ ((weak))
|
|
|
|
arch_teardown_msi_irqs(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
struct msi_desc *entry;
|
|
|
|
|
|
|
|
list_for_each_entry(entry, &dev->msi_list, list) {
|
|
|
|
if (entry->irq != 0)
|
|
|
|
arch_teardown_msi_irq(entry->irq);
|
|
|
|
}
|
|
|
|
}
|