2005-04-16 15:20:36 -07:00
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/* This only handles 32bit MTRR on 32bit hosts. This is strictly wrong
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because MTRRs can span upto 40 bits (36bits on most modern x86) */
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/mm.h>
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#include <asm/io.h>
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#include <asm/mtrr.h>
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#include <asm/msr.h>
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#include <asm/system.h>
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#include <asm/cpufeature.h>
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#include <asm/tlbflush.h>
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#include "mtrr.h"
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struct mtrr_state {
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struct mtrr_var_range *var_ranges;
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mtrr_type fixed_ranges[NUM_FIXED_RANGES];
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unsigned char enabled;
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mtrr_type def_type;
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};
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static unsigned long smp_changes_mask;
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static struct mtrr_state mtrr_state = {};
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/* Get the MSR pair relating to a var range */
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static void __init
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get_mtrr_var_range(unsigned int index, struct mtrr_var_range *vr)
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{
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rdmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi);
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rdmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);
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}
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static void __init
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get_fixed_ranges(mtrr_type * frs)
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{
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unsigned int *p = (unsigned int *) frs;
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int i;
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rdmsr(MTRRfix64K_00000_MSR, p[0], p[1]);
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for (i = 0; i < 2; i++)
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rdmsr(MTRRfix16K_80000_MSR + i, p[2 + i * 2], p[3 + i * 2]);
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for (i = 0; i < 8; i++)
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rdmsr(MTRRfix4K_C0000_MSR + i, p[6 + i * 2], p[7 + i * 2]);
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}
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/* Grab all of the MTRR state for this CPU into *state */
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void __init get_mtrr_state(void)
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{
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unsigned int i;
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struct mtrr_var_range *vrs;
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unsigned lo, dummy;
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if (!mtrr_state.var_ranges) {
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mtrr_state.var_ranges = kmalloc(num_var_ranges * sizeof (struct mtrr_var_range),
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GFP_KERNEL);
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if (!mtrr_state.var_ranges)
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return;
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}
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vrs = mtrr_state.var_ranges;
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for (i = 0; i < num_var_ranges; i++)
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get_mtrr_var_range(i, &vrs[i]);
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get_fixed_ranges(mtrr_state.fixed_ranges);
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rdmsr(MTRRdefType_MSR, lo, dummy);
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mtrr_state.def_type = (lo & 0xff);
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mtrr_state.enabled = (lo & 0xc00) >> 10;
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}
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/* Some BIOS's are fucked and don't set all MTRRs the same! */
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void __init mtrr_state_warn(void)
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{
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unsigned long mask = smp_changes_mask;
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if (!mask)
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return;
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if (mask & MTRR_CHANGE_MASK_FIXED)
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printk(KERN_WARNING "mtrr: your CPUs had inconsistent fixed MTRR settings\n");
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if (mask & MTRR_CHANGE_MASK_VARIABLE)
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printk(KERN_WARNING "mtrr: your CPUs had inconsistent variable MTRR settings\n");
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if (mask & MTRR_CHANGE_MASK_DEFTYPE)
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printk(KERN_WARNING "mtrr: your CPUs had inconsistent MTRRdefType settings\n");
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printk(KERN_INFO "mtrr: probably your BIOS does not setup all CPUs.\n");
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printk(KERN_INFO "mtrr: corrected configuration.\n");
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}
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/* Doesn't attempt to pass an error out to MTRR users
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because it's quite complicated in some cases and probably not
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worth it because the best error handling is to ignore it. */
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void mtrr_wrmsr(unsigned msr, unsigned a, unsigned b)
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{
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if (wrmsr_safe(msr, a, b) < 0)
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printk(KERN_ERR
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"MTRR: CPU %u: Writing MSR %x to %x:%x failed\n",
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smp_processor_id(), msr, a, b);
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}
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int generic_get_free_region(unsigned long base, unsigned long size)
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/* [SUMMARY] Get a free MTRR.
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<base> The starting (base) address of the region.
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<size> The size (in bytes) of the region.
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[RETURNS] The index of the region on success, else -1 on error.
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*/
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{
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int i, max;
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mtrr_type ltype;
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unsigned long lbase;
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unsigned lsize;
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max = num_var_ranges;
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for (i = 0; i < max; ++i) {
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mtrr_if->get(i, &lbase, &lsize, <ype);
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if (lsize == 0)
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return i;
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}
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return -ENOSPC;
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}
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2005-05-01 08:59:29 -07:00
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static void generic_get_mtrr(unsigned int reg, unsigned long *base,
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unsigned int *size, mtrr_type * type)
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2005-04-16 15:20:36 -07:00
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{
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unsigned int mask_lo, mask_hi, base_lo, base_hi;
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rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi);
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if ((mask_lo & 0x800) == 0) {
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/* Invalid (i.e. free) range */
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*base = 0;
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*size = 0;
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*type = 0;
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return;
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}
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rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi);
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/* Work out the shifted address mask. */
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mask_lo = size_or_mask | mask_hi << (32 - PAGE_SHIFT)
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| mask_lo >> PAGE_SHIFT;
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/* This works correctly if size is a power of two, i.e. a
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contiguous range. */
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*size = -mask_lo;
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*base = base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT;
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*type = base_lo & 0xff;
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}
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static int set_fixed_ranges(mtrr_type * frs)
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{
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unsigned int *p = (unsigned int *) frs;
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int changed = FALSE;
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int i;
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unsigned int lo, hi;
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rdmsr(MTRRfix64K_00000_MSR, lo, hi);
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if (p[0] != lo || p[1] != hi) {
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mtrr_wrmsr(MTRRfix64K_00000_MSR, p[0], p[1]);
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changed = TRUE;
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}
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for (i = 0; i < 2; i++) {
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rdmsr(MTRRfix16K_80000_MSR + i, lo, hi);
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if (p[2 + i * 2] != lo || p[3 + i * 2] != hi) {
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mtrr_wrmsr(MTRRfix16K_80000_MSR + i, p[2 + i * 2],
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p[3 + i * 2]);
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changed = TRUE;
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}
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}
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for (i = 0; i < 8; i++) {
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rdmsr(MTRRfix4K_C0000_MSR + i, lo, hi);
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if (p[6 + i * 2] != lo || p[7 + i * 2] != hi) {
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mtrr_wrmsr(MTRRfix4K_C0000_MSR + i, p[6 + i * 2],
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p[7 + i * 2]);
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changed = TRUE;
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}
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}
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return changed;
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}
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/* Set the MSR pair relating to a var range. Returns TRUE if
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changes are made */
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static int set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr)
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{
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unsigned int lo, hi;
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int changed = FALSE;
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rdmsr(MTRRphysBase_MSR(index), lo, hi);
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if ((vr->base_lo & 0xfffff0ffUL) != (lo & 0xfffff0ffUL)
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2005-04-16 15:25:11 -07:00
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|| (vr->base_hi & (size_and_mask >> (32 - PAGE_SHIFT))) !=
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(hi & (size_and_mask >> (32 - PAGE_SHIFT)))) {
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2005-04-16 15:20:36 -07:00
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mtrr_wrmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi);
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changed = TRUE;
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}
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rdmsr(MTRRphysMask_MSR(index), lo, hi);
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if ((vr->mask_lo & 0xfffff800UL) != (lo & 0xfffff800UL)
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2005-04-16 15:25:11 -07:00
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|| (vr->mask_hi & (size_and_mask >> (32 - PAGE_SHIFT))) !=
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(hi & (size_and_mask >> (32 - PAGE_SHIFT)))) {
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2005-04-16 15:20:36 -07:00
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mtrr_wrmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);
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changed = TRUE;
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}
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return changed;
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}
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static unsigned long set_mtrr_state(u32 deftype_lo, u32 deftype_hi)
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/* [SUMMARY] Set the MTRR state for this CPU.
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<state> The MTRR state information to read.
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<ctxt> Some relevant CPU context.
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[NOTE] The CPU must already be in a safe state for MTRR changes.
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[RETURNS] 0 if no changes made, else a mask indication what was changed.
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*/
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{
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unsigned int i;
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unsigned long change_mask = 0;
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for (i = 0; i < num_var_ranges; i++)
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if (set_mtrr_var_ranges(i, &mtrr_state.var_ranges[i]))
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change_mask |= MTRR_CHANGE_MASK_VARIABLE;
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if (set_fixed_ranges(mtrr_state.fixed_ranges))
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change_mask |= MTRR_CHANGE_MASK_FIXED;
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/* Set_mtrr_restore restores the old value of MTRRdefType,
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so to set it we fiddle with the saved value */
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if ((deftype_lo & 0xff) != mtrr_state.def_type
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|| ((deftype_lo & 0xc00) >> 10) != mtrr_state.enabled) {
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deftype_lo |= (mtrr_state.def_type | mtrr_state.enabled << 10);
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change_mask |= MTRR_CHANGE_MASK_DEFTYPE;
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}
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return change_mask;
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}
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static unsigned long cr4 = 0;
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static u32 deftype_lo, deftype_hi;
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static DEFINE_SPINLOCK(set_atomicity_lock);
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/*
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* Since we are disabling the cache don't allow any interrupts - they
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* would run extremely slow and would only increase the pain. The caller must
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* ensure that local interrupts are disabled and are reenabled after post_set()
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* has been called.
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*/
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2006-09-25 23:32:36 -07:00
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static void prepare_set(void) __acquires(set_atomicity_lock)
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2005-04-16 15:20:36 -07:00
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{
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unsigned long cr0;
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/* Note that this is not ideal, since the cache is only flushed/disabled
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for this CPU while the MTRRs are changed, but changing this requires
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more invasive changes to the way the kernel boots */
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spin_lock(&set_atomicity_lock);
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/* Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */
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cr0 = read_cr0() | 0x40000000; /* set CD flag */
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write_cr0(cr0);
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wbinvd();
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/* Save value of CR4 and clear Page Global Enable (bit 7) */
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if ( cpu_has_pge ) {
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cr4 = read_cr4();
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write_cr4(cr4 & ~X86_CR4_PGE);
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}
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/* Flush all TLBs via a mov %cr3, %reg; mov %reg, %cr3 */
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__flush_tlb();
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/* Save MTRR state */
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rdmsr(MTRRdefType_MSR, deftype_lo, deftype_hi);
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/* Disable MTRRs, and set the default type to uncached */
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mtrr_wrmsr(MTRRdefType_MSR, deftype_lo & 0xf300UL, deftype_hi);
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}
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2006-09-25 23:32:36 -07:00
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static void post_set(void) __releases(set_atomicity_lock)
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2005-04-16 15:20:36 -07:00
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{
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/* Flush TLBs (no need to flush caches - they are disabled) */
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__flush_tlb();
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/* Intel (P6) standard MTRRs */
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mtrr_wrmsr(MTRRdefType_MSR, deftype_lo, deftype_hi);
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/* Enable caches */
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write_cr0(read_cr0() & 0xbfffffff);
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/* Restore value of CR4 */
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if ( cpu_has_pge )
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write_cr4(cr4);
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spin_unlock(&set_atomicity_lock);
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}
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static void generic_set_all(void)
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{
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unsigned long mask, count;
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unsigned long flags;
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local_irq_save(flags);
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prepare_set();
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/* Actually set the state */
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mask = set_mtrr_state(deftype_lo,deftype_hi);
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post_set();
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local_irq_restore(flags);
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/* Use the atomic bitops to update the global mask */
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for (count = 0; count < sizeof mask * 8; ++count) {
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if (mask & 0x01)
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set_bit(count, &smp_changes_mask);
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mask >>= 1;
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}
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}
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static void generic_set_mtrr(unsigned int reg, unsigned long base,
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unsigned long size, mtrr_type type)
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/* [SUMMARY] Set variable MTRR register on the local CPU.
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<reg> The register to set.
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<base> The base address of the region.
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<size> The size of the region. If this is 0 the region is disabled.
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<type> The type of the region.
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<do_safe> If TRUE, do the change safely. If FALSE, safety measures should
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be done externally.
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[RETURNS] Nothing.
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*/
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{
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unsigned long flags;
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2005-07-07 17:56:38 -07:00
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struct mtrr_var_range *vr;
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vr = &mtrr_state.var_ranges[reg];
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2005-04-16 15:20:36 -07:00
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local_irq_save(flags);
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prepare_set();
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if (size == 0) {
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/* The invalid bit is kept in the mask, so we simply clear the
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relevant mask register to disable a range. */
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mtrr_wrmsr(MTRRphysMask_MSR(reg), 0, 0);
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2005-07-07 17:56:38 -07:00
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memset(vr, 0, sizeof(struct mtrr_var_range));
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2005-04-16 15:20:36 -07:00
|
|
|
} else {
|
2005-07-07 17:56:38 -07:00
|
|
|
vr->base_lo = base << PAGE_SHIFT | type;
|
|
|
|
vr->base_hi = (base & size_and_mask) >> (32 - PAGE_SHIFT);
|
|
|
|
vr->mask_lo = -size << PAGE_SHIFT | 0x800;
|
|
|
|
vr->mask_hi = (-size & size_and_mask) >> (32 - PAGE_SHIFT);
|
|
|
|
|
|
|
|
mtrr_wrmsr(MTRRphysBase_MSR(reg), vr->base_lo, vr->base_hi);
|
|
|
|
mtrr_wrmsr(MTRRphysMask_MSR(reg), vr->mask_lo, vr->mask_hi);
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
post_set();
|
|
|
|
local_irq_restore(flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
int generic_validate_add_page(unsigned long base, unsigned long size, unsigned int type)
|
|
|
|
{
|
|
|
|
unsigned long lbase, last;
|
|
|
|
|
|
|
|
/* For Intel PPro stepping <= 7, must be 4 MiB aligned
|
|
|
|
and not touch 0x70000000->0x7003FFFF */
|
|
|
|
if (is_cpu(INTEL) && boot_cpu_data.x86 == 6 &&
|
|
|
|
boot_cpu_data.x86_model == 1 &&
|
|
|
|
boot_cpu_data.x86_mask <= 7) {
|
|
|
|
if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) {
|
|
|
|
printk(KERN_WARNING "mtrr: base(0x%lx000) is not 4 MiB aligned\n", base);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
if (!(base + size < 0x70000000 || base > 0x7003FFFF) &&
|
|
|
|
(type == MTRR_TYPE_WRCOMB
|
|
|
|
|| type == MTRR_TYPE_WRBACK)) {
|
|
|
|
printk(KERN_WARNING "mtrr: writable mtrr between 0x70000000 and 0x7003FFFF may hang the CPU.\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (base + size < 0x100) {
|
|
|
|
printk(KERN_WARNING "mtrr: cannot set region below 1 MiB (0x%lx000,0x%lx000)\n",
|
|
|
|
base, size);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
/* Check upper bits of base and last are equal and lower bits are 0
|
|
|
|
for base and 1 for last */
|
|
|
|
last = base + size - 1;
|
|
|
|
for (lbase = base; !(lbase & 1) && (last & 1);
|
|
|
|
lbase = lbase >> 1, last = last >> 1) ;
|
|
|
|
if (lbase != last) {
|
|
|
|
printk(KERN_WARNING "mtrr: base(0x%lx000) is not aligned on a size(0x%lx000) boundary\n",
|
|
|
|
base, size);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static int generic_have_wrcomb(void)
|
|
|
|
{
|
|
|
|
unsigned long config, dummy;
|
|
|
|
rdmsr(MTRRcap_MSR, config, dummy);
|
|
|
|
return (config & (1 << 10));
|
|
|
|
}
|
|
|
|
|
|
|
|
int positive_have_wrcomb(void)
|
|
|
|
{
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* generic structure...
|
|
|
|
*/
|
|
|
|
struct mtrr_ops generic_mtrr_ops = {
|
|
|
|
.use_intel_if = 1,
|
|
|
|
.set_all = generic_set_all,
|
|
|
|
.get = generic_get_mtrr,
|
|
|
|
.get_free_region = generic_get_free_region,
|
|
|
|
.set = generic_set_mtrr,
|
|
|
|
.validate_add_page = generic_validate_add_page,
|
|
|
|
.have_wrcomb = generic_have_wrcomb,
|
|
|
|
};
|