2018-08-02 22:29:19 -07:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de>
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2022-03-09 03:03:44 -07:00
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* Copyright 2022 NXP, Peng Fan <peng.fan@nxp.com>
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2018-08-02 22:29:19 -07:00
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*/
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2024-02-18 22:22:38 -07:00
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#include <linux/bitfield.h>
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2018-08-02 22:29:19 -07:00
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#include <linux/clk.h>
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mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
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#include <linux/firmware/imx/ipc.h>
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2021-10-22 03:18:56 -07:00
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#include <linux/firmware/imx/s4.h>
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2018-08-02 22:29:19 -07:00
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#include <linux/interrupt.h>
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#include <linux/io.h>
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mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
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#include <linux/iopoll.h>
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2022-02-06 18:52:11 -07:00
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#include <linux/jiffies.h>
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2018-08-02 22:29:19 -07:00
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#include <linux/kernel.h>
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#include <linux/mailbox_controller.h>
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#include <linux/module.h>
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2023-07-14 10:47:01 -07:00
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#include <linux/of.h>
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2024-02-18 22:22:39 -07:00
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#include <linux/of_platform.h>
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2023-07-14 10:47:01 -07:00
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#include <linux/platform_device.h>
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mailbox: imx: Support runtime PM
Some power hungry sub-systems like VPU has its own MUs which also
use mailbox driver, current mailbox driver uses platform driver
model and MU's power will be ON after driver probed and left ON
there, it may cause the whole sub-system can NOT enter lower power
mode, take VPU driver for example, it has runtime PM support, but
due to its MU always ON, the VPU sub-system will be always ON and
consume many power during kernel idle.
To save power in kernel idle, mailbox driver needs to support
runtime PM in order to power off MU when it is unused. However,
the runtime suspend/resume can ONLY be implemented in mailbox's
.shutdown/.startup callback, so its consumer needs to call
mbox_request_channel()/mbox_free_channel() in consumer driver's
runtime PM callback, then the MU's power will be ON/OFF along with
consumer's runtime PM status.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-04-13 05:25:30 -07:00
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#include <linux/pm_runtime.h>
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2022-02-06 18:52:06 -07:00
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#include <linux/suspend.h>
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2018-08-02 22:29:19 -07:00
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#include <linux/slab.h>
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2024-03-27 09:03:10 -07:00
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#include <linux/workqueue.h>
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2018-08-02 22:29:19 -07:00
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2023-09-17 05:43:51 -07:00
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#include "mailbox.h"
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#define IMX_MU_CHANS 24
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mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
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/* TX0/RX0/RXDB[0-3] */
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#define IMX_MU_SCU_CHANS 6
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2021-10-22 03:18:56 -07:00
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/* TX0/RX0 */
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#define IMX_MU_S4_CHANS 2
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2024-07-29 00:47:09 -07:00
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#define IMX_MU_CHAN_NAME_SIZE 32
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2018-08-02 22:29:19 -07:00
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2024-02-18 22:22:38 -07:00
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#define IMX_MU_V2_PAR_OFF 0x4
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#define IMX_MU_V2_TR_MASK GENMASK(7, 0)
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#define IMX_MU_V2_RR_MASK GENMASK(15, 8)
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2022-08-03 00:53:26 -07:00
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2022-02-06 18:52:11 -07:00
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#define IMX_MU_SECO_TX_TOUT (msecs_to_jiffies(3000))
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#define IMX_MU_SECO_RX_TOUT (msecs_to_jiffies(3000))
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2022-03-09 03:03:44 -07:00
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/* Please not change TX & RX */
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2018-08-02 22:29:19 -07:00
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enum imx_mu_chan_type {
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2022-03-09 03:03:44 -07:00
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IMX_MU_TYPE_TX = 0, /* Tx */
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IMX_MU_TYPE_RX = 1, /* Rx */
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IMX_MU_TYPE_TXDB = 2, /* Tx doorbell */
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IMX_MU_TYPE_RXDB = 3, /* Rx doorbell */
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2022-06-15 06:00:09 -07:00
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IMX_MU_TYPE_RST = 4, /* Reset */
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2023-09-17 05:43:51 -07:00
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IMX_MU_TYPE_TXDB_V2 = 5, /* Tx doorbell with S/W ACK */
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2018-08-02 22:29:19 -07:00
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};
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2021-05-28 03:06:02 -07:00
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enum imx_mu_xcr {
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2022-06-15 06:00:09 -07:00
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IMX_MU_CR,
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2021-05-28 03:06:03 -07:00
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IMX_MU_GIER,
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2021-05-28 03:06:02 -07:00
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IMX_MU_GCR,
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IMX_MU_TCR,
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IMX_MU_RCR,
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IMX_MU_xCR_MAX,
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};
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enum imx_mu_xsr {
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IMX_MU_SR,
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IMX_MU_GSR,
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IMX_MU_TSR,
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IMX_MU_RSR,
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2022-06-15 06:00:09 -07:00
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IMX_MU_xSR_MAX,
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2021-05-28 03:06:02 -07:00
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};
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mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
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struct imx_sc_rpc_msg_max {
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struct imx_sc_rpc_msg hdr;
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2022-02-06 18:52:11 -07:00
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u32 data[30];
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mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
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};
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2021-10-22 03:18:56 -07:00
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struct imx_s4_rpc_msg_max {
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struct imx_s4_rpc_msg hdr;
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u32 data[254];
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};
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2018-08-02 22:29:19 -07:00
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struct imx_mu_con_priv {
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unsigned int idx;
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char irq_desc[IMX_MU_CHAN_NAME_SIZE];
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enum imx_mu_chan_type type;
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struct mbox_chan *chan;
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2024-03-27 09:03:10 -07:00
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struct work_struct txdb_work;
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2018-08-02 22:29:19 -07:00
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};
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struct imx_mu_priv {
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struct device *dev;
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void __iomem *base;
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2021-10-22 03:18:56 -07:00
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void *msg;
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2018-08-02 22:29:19 -07:00
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spinlock_t xcr_lock; /* control register lock */
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struct mbox_controller mbox;
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struct mbox_chan mbox_chans[IMX_MU_CHANS];
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struct imx_mu_con_priv con_priv[IMX_MU_CHANS];
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2019-10-09 01:07:21 -07:00
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const struct imx_mu_dcfg *dcfg;
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2018-08-02 22:29:19 -07:00
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struct clk *clk;
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2022-03-09 03:03:43 -07:00
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int irq[IMX_MU_CHANS];
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2022-02-06 18:52:06 -07:00
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bool suspend;
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2018-08-02 22:29:19 -07:00
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bool side_b;
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2024-02-18 22:22:38 -07:00
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u32 xcr[IMX_MU_xCR_MAX];
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u32 num_tr;
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u32 num_rr;
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2018-08-02 22:29:19 -07:00
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};
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2021-05-28 03:06:03 -07:00
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enum imx_mu_type {
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IMX_MU_V1,
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2021-10-22 03:18:56 -07:00
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IMX_MU_V2 = BIT(1),
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IMX_MU_V2_S4 = BIT(15),
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2022-03-09 03:03:44 -07:00
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IMX_MU_V2_IRQ = BIT(16),
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2021-05-28 03:06:03 -07:00
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};
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2020-03-19 00:49:51 -07:00
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struct imx_mu_dcfg {
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int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
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int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
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2022-02-06 18:52:10 -07:00
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int (*rxdb)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
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2024-02-18 22:22:37 -07:00
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int (*init)(struct imx_mu_priv *priv);
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2021-05-28 03:06:03 -07:00
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enum imx_mu_type type;
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2021-05-28 03:06:01 -07:00
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u32 xTR; /* Transmit Register0 */
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u32 xRR; /* Receive Register0 */
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2022-06-15 06:00:09 -07:00
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u32 xSR[IMX_MU_xSR_MAX]; /* Status Registers */
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u32 xCR[IMX_MU_xCR_MAX]; /* Control Registers */
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2019-10-09 01:07:21 -07:00
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};
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2021-10-22 03:18:56 -07:00
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#define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
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#define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
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#define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
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2021-05-28 03:06:03 -07:00
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/* General Purpose Interrupt Enable */
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2021-10-22 03:18:56 -07:00
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#define IMX_MU_xCR_GIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
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2021-05-28 03:06:03 -07:00
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/* Receive Interrupt Enable */
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2021-10-22 03:18:56 -07:00
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#define IMX_MU_xCR_RIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
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2021-05-28 03:06:03 -07:00
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/* Transmit Interrupt Enable */
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2021-10-22 03:18:56 -07:00
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#define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
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2021-05-28 03:06:03 -07:00
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/* General Purpose Interrupt Request */
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2021-10-22 03:18:56 -07:00
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#define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x))))
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2022-06-15 06:00:09 -07:00
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/* MU reset */
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#define IMX_MU_xCR_RST(type) (type & IMX_MU_V2 ? BIT(0) : BIT(5))
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#define IMX_MU_xSR_RST(type) (type & IMX_MU_V2 ? BIT(0) : BIT(7))
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2021-05-28 03:06:03 -07:00
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2018-08-02 22:29:19 -07:00
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static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
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{
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return container_of(mbox, struct imx_mu_priv, mbox);
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}
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static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs)
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{
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iowrite32(val, priv->base + offs);
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}
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static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs)
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{
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return ioread32(priv->base + offs);
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}
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2022-02-06 18:52:11 -07:00
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static int imx_mu_tx_waiting_write(struct imx_mu_priv *priv, u32 val, u32 idx)
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{
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u64 timeout_time = get_jiffies_64() + IMX_MU_SECO_TX_TOUT;
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u32 status;
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u32 can_write;
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dev_dbg(priv->dev, "Trying to write %.8x to idx %d\n", val, idx);
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do {
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status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
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can_write = status & IMX_MU_xSR_TEn(priv->dcfg->type, idx % 4);
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} while (!can_write && time_is_after_jiffies64(timeout_time));
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if (!can_write) {
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dev_err(priv->dev, "timeout trying to write %.8x at %d(%.8x)\n",
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val, idx, status);
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|
|
return -ETIME;
|
|
|
|
}
|
|
|
|
|
|
|
|
imx_mu_write(priv, val, priv->dcfg->xTR + (idx % 4) * 4);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int imx_mu_rx_waiting_read(struct imx_mu_priv *priv, u32 *val, u32 idx)
|
|
|
|
{
|
|
|
|
u64 timeout_time = get_jiffies_64() + IMX_MU_SECO_RX_TOUT;
|
|
|
|
u32 status;
|
|
|
|
u32 can_read;
|
|
|
|
|
|
|
|
dev_dbg(priv->dev, "Trying to read from idx %d\n", idx);
|
|
|
|
|
|
|
|
do {
|
|
|
|
status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
|
|
|
|
can_read = status & IMX_MU_xSR_RFn(priv->dcfg->type, idx % 4);
|
|
|
|
} while (!can_read && time_is_after_jiffies64(timeout_time));
|
|
|
|
|
|
|
|
if (!can_read) {
|
|
|
|
dev_err(priv->dev, "timeout trying to read idx %d (%.8x)\n",
|
|
|
|
idx, status);
|
|
|
|
return -ETIME;
|
|
|
|
}
|
|
|
|
|
|
|
|
*val = imx_mu_read(priv, priv->dcfg->xRR + (idx % 4) * 4);
|
|
|
|
dev_dbg(priv->dev, "Read %.8x\n", *val);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2021-05-28 03:06:02 -07:00
|
|
|
static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, enum imx_mu_xcr type, u32 set, u32 clr)
|
2018-08-02 22:29:19 -07:00
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&priv->xcr_lock, flags);
|
2021-05-28 03:06:02 -07:00
|
|
|
val = imx_mu_read(priv, priv->dcfg->xCR[type]);
|
2018-08-02 22:29:19 -07:00
|
|
|
val &= ~clr;
|
|
|
|
val |= set;
|
2021-05-28 03:06:02 -07:00
|
|
|
imx_mu_write(priv, val, priv->dcfg->xCR[type]);
|
2018-08-02 22:29:19 -07:00
|
|
|
spin_unlock_irqrestore(&priv->xcr_lock, flags);
|
|
|
|
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2020-03-19 00:49:51 -07:00
|
|
|
static int imx_mu_generic_tx(struct imx_mu_priv *priv,
|
|
|
|
struct imx_mu_con_priv *cp,
|
|
|
|
void *data)
|
|
|
|
{
|
|
|
|
u32 *arg = data;
|
mailbox: imx: fix TXDB_V2 channel race condition
Two TXDB_V2 channels are used between Linux and System Manager(SM).
Channel0 for normal TX, Channel 1 for notification completion.
The TXDB_V2 trigger logic is using imx_mu_xcr_rmw which uses
read/modify/update logic.
Note: clear MUB GSR BITs, the MUA side GCR BITs will also got cleared per
hardware design.
Channel0 Linux
read GCR->modify GCR->write GCR->M33 SM->read GSR----->clear GSR
|-(1)-|
Channel1 Linux start in time slot(1)
read GCR->modify GCR->write GCR->M33 SM->read GSR->clear GSR
So Channel1 read GCR will read back the GCR that Channel0 wrote, because
M33 has not finish clear GSR, this means Channel1 GCR writing will
trigger Channel1 and Channel0 interrupt both which is wrong.
Channel0 will be freed(SCMI channel status set to FREE) in M33 SM when
processing the 1st Channel0 interrupt. So when 2nd interrupt trigger
(channel 0/1 trigger together), SM will see a freed Channel0, and report
protocol error.
To address the issue, not using read/modify/update logic, just use
write, because write 0 to GCR will be ignored. And after write MUA GCR,
wait the SM to clear MUB GSR by looping MUA GCR value.
Fixes: 5bfe4067d350 ("mailbox: imx: support channel type tx doorbell v2")
Reviewed-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2024-05-24 00:56:32 -07:00
|
|
|
u32 val;
|
|
|
|
int ret;
|
2020-03-19 00:49:51 -07:00
|
|
|
|
|
|
|
switch (cp->type) {
|
|
|
|
case IMX_MU_TYPE_TX:
|
2021-05-28 03:06:01 -07:00
|
|
|
imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4);
|
2021-05-28 03:06:03 -07:00
|
|
|
imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
|
2020-03-19 00:49:51 -07:00
|
|
|
break;
|
|
|
|
case IMX_MU_TYPE_TXDB:
|
2021-05-28 03:06:03 -07:00
|
|
|
imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);
|
2024-03-27 09:03:10 -07:00
|
|
|
queue_work(system_bh_wq, &cp->txdb_work);
|
2020-03-19 00:49:51 -07:00
|
|
|
break;
|
2023-09-17 05:43:51 -07:00
|
|
|
case IMX_MU_TYPE_TXDB_V2:
|
mailbox: imx: fix TXDB_V2 channel race condition
Two TXDB_V2 channels are used between Linux and System Manager(SM).
Channel0 for normal TX, Channel 1 for notification completion.
The TXDB_V2 trigger logic is using imx_mu_xcr_rmw which uses
read/modify/update logic.
Note: clear MUB GSR BITs, the MUA side GCR BITs will also got cleared per
hardware design.
Channel0 Linux
read GCR->modify GCR->write GCR->M33 SM->read GSR----->clear GSR
|-(1)-|
Channel1 Linux start in time slot(1)
read GCR->modify GCR->write GCR->M33 SM->read GSR->clear GSR
So Channel1 read GCR will read back the GCR that Channel0 wrote, because
M33 has not finish clear GSR, this means Channel1 GCR writing will
trigger Channel1 and Channel0 interrupt both which is wrong.
Channel0 will be freed(SCMI channel status set to FREE) in M33 SM when
processing the 1st Channel0 interrupt. So when 2nd interrupt trigger
(channel 0/1 trigger together), SM will see a freed Channel0, and report
protocol error.
To address the issue, not using read/modify/update logic, just use
write, because write 0 to GCR will be ignored. And after write MUA GCR,
wait the SM to clear MUB GSR by looping MUA GCR value.
Fixes: 5bfe4067d350 ("mailbox: imx: support channel type tx doorbell v2")
Reviewed-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
2024-05-24 00:56:32 -07:00
|
|
|
imx_mu_write(priv, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx),
|
|
|
|
priv->dcfg->xCR[IMX_MU_GCR]);
|
|
|
|
ret = readl_poll_timeout(priv->base + priv->dcfg->xCR[IMX_MU_GCR], val,
|
|
|
|
!(val & IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx)),
|
|
|
|
0, 1000);
|
|
|
|
if (ret)
|
|
|
|
dev_warn_ratelimited(priv->dev, "channel type: %d failure\n", cp->type);
|
2023-09-17 05:43:51 -07:00
|
|
|
break;
|
2020-03-19 00:49:51 -07:00
|
|
|
default:
|
|
|
|
dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int imx_mu_generic_rx(struct imx_mu_priv *priv,
|
|
|
|
struct imx_mu_con_priv *cp)
|
|
|
|
{
|
|
|
|
u32 dat;
|
|
|
|
|
2021-05-28 03:06:01 -07:00
|
|
|
dat = imx_mu_read(priv, priv->dcfg->xRR + (cp->idx) * 4);
|
2020-03-19 00:49:51 -07:00
|
|
|
mbox_chan_received_data(cp->chan, (void *)&dat);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2022-02-06 18:52:10 -07:00
|
|
|
static int imx_mu_generic_rxdb(struct imx_mu_priv *priv,
|
|
|
|
struct imx_mu_con_priv *cp)
|
|
|
|
{
|
|
|
|
imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),
|
|
|
|
priv->dcfg->xSR[IMX_MU_GSR]);
|
|
|
|
mbox_chan_received_data(cp->chan, NULL);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2021-10-22 03:18:56 -07:00
|
|
|
static int imx_mu_specific_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data)
|
mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
|
|
|
{
|
|
|
|
u32 *arg = data;
|
2024-02-18 22:22:38 -07:00
|
|
|
u32 num_tr = priv->num_tr;
|
mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
|
|
|
int i, ret;
|
|
|
|
u32 xsr;
|
2024-02-18 22:22:38 -07:00
|
|
|
u32 size, max_size;
|
2021-10-22 03:18:56 -07:00
|
|
|
|
|
|
|
if (priv->dcfg->type & IMX_MU_V2_S4) {
|
|
|
|
size = ((struct imx_s4_rpc_msg_max *)data)->hdr.size;
|
|
|
|
max_size = sizeof(struct imx_s4_rpc_msg_max);
|
|
|
|
} else {
|
|
|
|
size = ((struct imx_sc_rpc_msg_max *)data)->hdr.size;
|
|
|
|
max_size = sizeof(struct imx_sc_rpc_msg_max);
|
|
|
|
}
|
mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
|
|
|
|
|
|
|
switch (cp->type) {
|
|
|
|
case IMX_MU_TYPE_TX:
|
2020-04-14 06:21:15 -07:00
|
|
|
/*
|
|
|
|
* msg->hdr.size specifies the number of u32 words while
|
|
|
|
* sizeof yields bytes.
|
|
|
|
*/
|
|
|
|
|
2021-10-22 03:18:56 -07:00
|
|
|
if (size > max_size / 4) {
|
mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
|
|
|
/*
|
|
|
|
* The real message size can be different to
|
2021-10-22 03:18:56 -07:00
|
|
|
* struct imx_sc_rpc_msg_max/imx_s4_rpc_msg_max size
|
mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
|
|
|
*/
|
2021-10-22 03:18:56 -07:00
|
|
|
dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on TX; got: %i bytes\n", max_size, size << 2);
|
mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2021-10-22 03:18:56 -07:00
|
|
|
for (i = 0; i < num_tr && i < size; i++)
|
|
|
|
imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4);
|
|
|
|
for (; i < size; i++) {
|
2021-05-28 03:06:02 -07:00
|
|
|
ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR],
|
mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
|
|
|
xsr,
|
2021-10-22 03:18:56 -07:00
|
|
|
xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % num_tr),
|
2022-02-06 18:52:08 -07:00
|
|
|
0, 5 * USEC_PER_SEC);
|
mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
|
|
|
if (ret) {
|
|
|
|
dev_err(priv->dev, "Send data index: %d timeout\n", i);
|
|
|
|
return ret;
|
|
|
|
}
|
2021-10-22 03:18:56 -07:00
|
|
|
imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4);
|
mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
|
|
|
}
|
|
|
|
|
2021-05-28 03:06:03 -07:00
|
|
|
imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
|
mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2021-10-22 03:18:56 -07:00
|
|
|
static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp)
|
mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
|
|
|
{
|
2021-10-22 03:18:56 -07:00
|
|
|
u32 *data;
|
mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
|
|
|
int i, ret;
|
|
|
|
u32 xsr;
|
2021-10-22 03:18:56 -07:00
|
|
|
u32 size, max_size;
|
2024-02-18 22:22:38 -07:00
|
|
|
u32 num_rr = priv->num_rr;
|
2021-10-22 03:18:56 -07:00
|
|
|
|
|
|
|
data = (u32 *)priv->msg;
|
mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
|
|
|
|
2021-05-28 03:06:03 -07:00
|
|
|
imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, 0));
|
2021-05-28 03:06:01 -07:00
|
|
|
*data++ = imx_mu_read(priv, priv->dcfg->xRR);
|
mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
|
|
|
|
2021-10-22 03:18:56 -07:00
|
|
|
if (priv->dcfg->type & IMX_MU_V2_S4) {
|
|
|
|
size = ((struct imx_s4_rpc_msg_max *)priv->msg)->hdr.size;
|
|
|
|
max_size = sizeof(struct imx_s4_rpc_msg_max);
|
|
|
|
} else {
|
|
|
|
size = ((struct imx_sc_rpc_msg_max *)priv->msg)->hdr.size;
|
|
|
|
max_size = sizeof(struct imx_sc_rpc_msg_max);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (size > max_size / 4) {
|
|
|
|
dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on RX; got: %i bytes\n", max_size, size << 2);
|
mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2021-10-22 03:18:56 -07:00
|
|
|
for (i = 1; i < size; i++) {
|
2021-05-28 03:06:02 -07:00
|
|
|
ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr,
|
2024-02-18 22:22:38 -07:00
|
|
|
xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % num_rr), 0,
|
2022-02-06 18:52:08 -07:00
|
|
|
5 * USEC_PER_SEC);
|
mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
|
|
|
if (ret) {
|
|
|
|
dev_err(priv->dev, "timeout read idx %d\n", i);
|
|
|
|
return ret;
|
|
|
|
}
|
2024-02-18 22:22:38 -07:00
|
|
|
*data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % num_rr) * 4);
|
mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
|
|
|
}
|
|
|
|
|
2021-05-28 03:06:03 -07:00
|
|
|
imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0);
|
2021-10-22 03:18:56 -07:00
|
|
|
mbox_chan_received_data(cp->chan, (void *)priv->msg);
|
mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2022-02-06 18:52:11 -07:00
|
|
|
static int imx_mu_seco_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp,
|
|
|
|
void *data)
|
|
|
|
{
|
|
|
|
struct imx_sc_rpc_msg_max *msg = data;
|
|
|
|
u32 *arg = data;
|
|
|
|
u32 byte_size;
|
|
|
|
int err;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
dev_dbg(priv->dev, "Sending message\n");
|
|
|
|
|
|
|
|
switch (cp->type) {
|
|
|
|
case IMX_MU_TYPE_TXDB:
|
|
|
|
byte_size = msg->hdr.size * sizeof(u32);
|
|
|
|
if (byte_size > sizeof(*msg)) {
|
|
|
|
/*
|
|
|
|
* The real message size can be different to
|
|
|
|
* struct imx_sc_rpc_msg_max size
|
|
|
|
*/
|
|
|
|
dev_err(priv->dev,
|
|
|
|
"Exceed max msg size (%zu) on TX, got: %i\n",
|
|
|
|
sizeof(*msg), byte_size);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
print_hex_dump_debug("from client ", DUMP_PREFIX_OFFSET, 4, 4,
|
|
|
|
data, byte_size, false);
|
|
|
|
|
|
|
|
/* Send first word */
|
|
|
|
dev_dbg(priv->dev, "Sending header\n");
|
|
|
|
imx_mu_write(priv, *arg++, priv->dcfg->xTR);
|
|
|
|
|
|
|
|
/* Send signaling */
|
|
|
|
dev_dbg(priv->dev, "Sending signaling\n");
|
|
|
|
imx_mu_xcr_rmw(priv, IMX_MU_GCR,
|
|
|
|
IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);
|
|
|
|
|
|
|
|
/* Send words to fill the mailbox */
|
|
|
|
for (i = 1; i < 4 && i < msg->hdr.size; i++) {
|
|
|
|
dev_dbg(priv->dev, "Sending word %d\n", i);
|
|
|
|
imx_mu_write(priv, *arg++,
|
|
|
|
priv->dcfg->xTR + (i % 4) * 4);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Send rest of message waiting for remote read */
|
|
|
|
for (; i < msg->hdr.size; i++) {
|
|
|
|
dev_dbg(priv->dev, "Sending word %d\n", i);
|
|
|
|
err = imx_mu_tx_waiting_write(priv, *arg++, i);
|
|
|
|
if (err) {
|
|
|
|
dev_err(priv->dev, "Timeout tx %d\n", i);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Simulate hack for mbox framework */
|
2024-03-27 09:03:10 -07:00
|
|
|
queue_work(system_bh_wq, &cp->txdb_work);
|
2022-02-06 18:52:11 -07:00
|
|
|
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_warn_ratelimited(priv->dev,
|
|
|
|
"Send data on wrong channel type: %d\n",
|
|
|
|
cp->type);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int imx_mu_seco_rxdb(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp)
|
|
|
|
{
|
|
|
|
struct imx_sc_rpc_msg_max msg;
|
|
|
|
u32 *data = (u32 *)&msg;
|
|
|
|
u32 byte_size;
|
|
|
|
int err = 0;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
dev_dbg(priv->dev, "Receiving message\n");
|
|
|
|
|
|
|
|
/* Read header */
|
|
|
|
dev_dbg(priv->dev, "Receiving header\n");
|
|
|
|
*data++ = imx_mu_read(priv, priv->dcfg->xRR);
|
|
|
|
byte_size = msg.hdr.size * sizeof(u32);
|
|
|
|
if (byte_size > sizeof(msg)) {
|
|
|
|
dev_err(priv->dev, "Exceed max msg size (%zu) on RX, got: %i\n",
|
|
|
|
sizeof(msg), byte_size);
|
|
|
|
err = -EINVAL;
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Read message waiting they are written */
|
|
|
|
for (i = 1; i < msg.hdr.size; i++) {
|
|
|
|
dev_dbg(priv->dev, "Receiving word %d\n", i);
|
|
|
|
err = imx_mu_rx_waiting_read(priv, data++, i);
|
|
|
|
if (err) {
|
|
|
|
dev_err(priv->dev, "Timeout rx %d\n", i);
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Clear GIP */
|
|
|
|
imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),
|
|
|
|
priv->dcfg->xSR[IMX_MU_GSR]);
|
|
|
|
|
|
|
|
print_hex_dump_debug("to client ", DUMP_PREFIX_OFFSET, 4, 4,
|
|
|
|
&msg, byte_size, false);
|
|
|
|
|
|
|
|
/* send data to client */
|
|
|
|
dev_dbg(priv->dev, "Sending message to client\n");
|
|
|
|
mbox_chan_received_data(cp->chan, (void *)&msg);
|
|
|
|
|
|
|
|
goto exit;
|
|
|
|
|
|
|
|
error:
|
|
|
|
mbox_chan_received_data(cp->chan, ERR_PTR(err));
|
|
|
|
|
|
|
|
exit:
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2024-03-27 09:03:10 -07:00
|
|
|
static void imx_mu_txdb_work(struct work_struct *t)
|
2018-08-02 22:29:19 -07:00
|
|
|
{
|
2024-03-27 09:03:10 -07:00
|
|
|
struct imx_mu_con_priv *cp = from_work(cp, t, txdb_work);
|
2018-08-02 22:29:19 -07:00
|
|
|
|
|
|
|
mbox_chan_txdone(cp->chan, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t imx_mu_isr(int irq, void *p)
|
|
|
|
{
|
|
|
|
struct mbox_chan *chan = p;
|
|
|
|
struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
|
|
|
|
struct imx_mu_con_priv *cp = chan->con_priv;
|
2020-03-19 00:49:51 -07:00
|
|
|
u32 val, ctrl;
|
2018-08-02 22:29:19 -07:00
|
|
|
|
|
|
|
switch (cp->type) {
|
|
|
|
case IMX_MU_TYPE_TX:
|
2021-05-28 03:06:02 -07:00
|
|
|
ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_TCR]);
|
|
|
|
val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
|
2021-05-28 03:06:03 -07:00
|
|
|
val &= IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx) &
|
|
|
|
(ctrl & IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
|
2018-08-02 22:29:19 -07:00
|
|
|
break;
|
|
|
|
case IMX_MU_TYPE_RX:
|
2021-05-28 03:06:02 -07:00
|
|
|
ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_RCR]);
|
|
|
|
val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
|
2021-05-28 03:06:03 -07:00
|
|
|
val &= IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx) &
|
|
|
|
(ctrl & IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
|
2018-08-02 22:29:19 -07:00
|
|
|
break;
|
|
|
|
case IMX_MU_TYPE_RXDB:
|
2021-05-28 03:06:03 -07:00
|
|
|
ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GIER]);
|
2021-05-28 03:06:02 -07:00
|
|
|
val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);
|
2021-05-28 03:06:03 -07:00
|
|
|
val &= IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx) &
|
|
|
|
(ctrl & IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
|
2018-08-02 22:29:19 -07:00
|
|
|
break;
|
2022-06-15 06:00:09 -07:00
|
|
|
case IMX_MU_TYPE_RST:
|
|
|
|
return IRQ_NONE;
|
2018-08-02 22:29:19 -07:00
|
|
|
default:
|
2021-06-21 11:56:45 -07:00
|
|
|
dev_warn_ratelimited(priv->dev, "Unhandled channel type %d\n",
|
|
|
|
cp->type);
|
|
|
|
return IRQ_NONE;
|
2018-08-02 22:29:19 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
if (!val)
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
2021-05-28 03:06:03 -07:00
|
|
|
if ((val == IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx)) &&
|
|
|
|
(cp->type == IMX_MU_TYPE_TX)) {
|
|
|
|
imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
|
2018-08-02 22:29:19 -07:00
|
|
|
mbox_chan_txdone(chan, 0);
|
2021-05-28 03:06:03 -07:00
|
|
|
} else if ((val == IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx)) &&
|
|
|
|
(cp->type == IMX_MU_TYPE_RX)) {
|
2020-03-19 00:49:51 -07:00
|
|
|
priv->dcfg->rx(priv, cp);
|
2021-05-28 03:06:03 -07:00
|
|
|
} else if ((val == IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx)) &&
|
|
|
|
(cp->type == IMX_MU_TYPE_RXDB)) {
|
2022-02-06 18:52:10 -07:00
|
|
|
priv->dcfg->rxdb(priv, cp);
|
2018-08-02 22:29:19 -07:00
|
|
|
} else {
|
|
|
|
dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
|
|
|
|
return IRQ_NONE;
|
|
|
|
}
|
|
|
|
|
2022-02-06 18:52:06 -07:00
|
|
|
if (priv->suspend)
|
|
|
|
pm_system_wakeup();
|
|
|
|
|
2018-08-02 22:29:19 -07:00
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int imx_mu_send_data(struct mbox_chan *chan, void *data)
|
|
|
|
{
|
|
|
|
struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
|
|
|
|
struct imx_mu_con_priv *cp = chan->con_priv;
|
|
|
|
|
2020-03-19 00:49:51 -07:00
|
|
|
return priv->dcfg->tx(priv, cp, data);
|
2018-08-02 22:29:19 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int imx_mu_startup(struct mbox_chan *chan)
|
|
|
|
{
|
|
|
|
struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
|
|
|
|
struct imx_mu_con_priv *cp = chan->con_priv;
|
2022-03-09 03:03:44 -07:00
|
|
|
unsigned long irq_flag = 0;
|
2018-08-02 22:29:19 -07:00
|
|
|
int ret;
|
|
|
|
|
mailbox: imx: Support runtime PM
Some power hungry sub-systems like VPU has its own MUs which also
use mailbox driver, current mailbox driver uses platform driver
model and MU's power will be ON after driver probed and left ON
there, it may cause the whole sub-system can NOT enter lower power
mode, take VPU driver for example, it has runtime PM support, but
due to its MU always ON, the VPU sub-system will be always ON and
consume many power during kernel idle.
To save power in kernel idle, mailbox driver needs to support
runtime PM in order to power off MU when it is unused. However,
the runtime suspend/resume can ONLY be implemented in mailbox's
.shutdown/.startup callback, so its consumer needs to call
mbox_request_channel()/mbox_free_channel() in consumer driver's
runtime PM callback, then the MU's power will be ON/OFF along with
consumer's runtime PM status.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-04-13 05:25:30 -07:00
|
|
|
pm_runtime_get_sync(priv->dev);
|
2023-09-17 05:43:51 -07:00
|
|
|
if (cp->type == IMX_MU_TYPE_TXDB_V2)
|
|
|
|
return 0;
|
|
|
|
|
2018-08-02 22:29:19 -07:00
|
|
|
if (cp->type == IMX_MU_TYPE_TXDB) {
|
|
|
|
/* Tx doorbell don't have ACK support */
|
2024-03-27 09:03:10 -07:00
|
|
|
INIT_WORK(&cp->txdb_work, imx_mu_txdb_work);
|
2018-08-02 22:29:19 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-06-02 22:15:44 -07:00
|
|
|
/* IPC MU should be with IRQF_NO_SUSPEND set */
|
|
|
|
if (!priv->dev->pm_domain)
|
|
|
|
irq_flag |= IRQF_NO_SUSPEND;
|
|
|
|
|
2022-03-09 03:03:44 -07:00
|
|
|
if (!(priv->dcfg->type & IMX_MU_V2_IRQ))
|
|
|
|
irq_flag |= IRQF_SHARED;
|
|
|
|
|
|
|
|
ret = request_irq(priv->irq[cp->type], imx_mu_isr, irq_flag, cp->irq_desc, chan);
|
2018-08-02 22:29:19 -07:00
|
|
|
if (ret) {
|
2022-03-09 03:03:44 -07:00
|
|
|
dev_err(priv->dev, "Unable to acquire IRQ %d\n", priv->irq[cp->type]);
|
2018-08-02 22:29:19 -07:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (cp->type) {
|
|
|
|
case IMX_MU_TYPE_RX:
|
2021-05-28 03:06:03 -07:00
|
|
|
imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx), 0);
|
2018-08-02 22:29:19 -07:00
|
|
|
break;
|
|
|
|
case IMX_MU_TYPE_RXDB:
|
2021-05-28 03:06:03 -07:00
|
|
|
imx_mu_xcr_rmw(priv, IMX_MU_GIER, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx), 0);
|
2018-08-02 22:29:19 -07:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void imx_mu_shutdown(struct mbox_chan *chan)
|
|
|
|
{
|
|
|
|
struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
|
|
|
|
struct imx_mu_con_priv *cp = chan->con_priv;
|
2022-06-15 06:00:09 -07:00
|
|
|
int ret;
|
|
|
|
u32 sr;
|
2018-08-02 22:29:19 -07:00
|
|
|
|
2023-09-17 05:43:51 -07:00
|
|
|
if (cp->type == IMX_MU_TYPE_TXDB_V2) {
|
|
|
|
pm_runtime_put_sync(priv->dev);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2019-10-09 01:07:18 -07:00
|
|
|
if (cp->type == IMX_MU_TYPE_TXDB) {
|
2024-03-27 09:03:10 -07:00
|
|
|
cancel_work_sync(&cp->txdb_work);
|
mailbox: imx: Support runtime PM
Some power hungry sub-systems like VPU has its own MUs which also
use mailbox driver, current mailbox driver uses platform driver
model and MU's power will be ON after driver probed and left ON
there, it may cause the whole sub-system can NOT enter lower power
mode, take VPU driver for example, it has runtime PM support, but
due to its MU always ON, the VPU sub-system will be always ON and
consume many power during kernel idle.
To save power in kernel idle, mailbox driver needs to support
runtime PM in order to power off MU when it is unused. However,
the runtime suspend/resume can ONLY be implemented in mailbox's
.shutdown/.startup callback, so its consumer needs to call
mbox_request_channel()/mbox_free_channel() in consumer driver's
runtime PM callback, then the MU's power will be ON/OFF along with
consumer's runtime PM status.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-04-13 05:25:30 -07:00
|
|
|
pm_runtime_put_sync(priv->dev);
|
2019-10-09 01:07:18 -07:00
|
|
|
return;
|
|
|
|
}
|
2018-08-02 22:29:19 -07:00
|
|
|
|
2019-10-09 01:07:19 -07:00
|
|
|
switch (cp->type) {
|
|
|
|
case IMX_MU_TYPE_TX:
|
2021-05-28 03:06:03 -07:00
|
|
|
imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
|
2019-10-09 01:07:19 -07:00
|
|
|
break;
|
|
|
|
case IMX_MU_TYPE_RX:
|
2021-05-28 03:06:03 -07:00
|
|
|
imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
|
2019-10-09 01:07:19 -07:00
|
|
|
break;
|
|
|
|
case IMX_MU_TYPE_RXDB:
|
2021-05-28 03:06:03 -07:00
|
|
|
imx_mu_xcr_rmw(priv, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
|
2019-10-09 01:07:19 -07:00
|
|
|
break;
|
2022-06-15 06:00:09 -07:00
|
|
|
case IMX_MU_TYPE_RST:
|
|
|
|
imx_mu_xcr_rmw(priv, IMX_MU_CR, IMX_MU_xCR_RST(priv->dcfg->type), 0);
|
|
|
|
ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_SR], sr,
|
|
|
|
!(sr & IMX_MU_xSR_RST(priv->dcfg->type)), 1, 5);
|
|
|
|
if (ret)
|
|
|
|
dev_warn(priv->dev, "RST channel timeout\n");
|
|
|
|
break;
|
2019-10-09 01:07:19 -07:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
2018-08-02 22:29:19 -07:00
|
|
|
|
2022-03-09 03:03:44 -07:00
|
|
|
free_irq(priv->irq[cp->type], chan);
|
mailbox: imx: Support runtime PM
Some power hungry sub-systems like VPU has its own MUs which also
use mailbox driver, current mailbox driver uses platform driver
model and MU's power will be ON after driver probed and left ON
there, it may cause the whole sub-system can NOT enter lower power
mode, take VPU driver for example, it has runtime PM support, but
due to its MU always ON, the VPU sub-system will be always ON and
consume many power during kernel idle.
To save power in kernel idle, mailbox driver needs to support
runtime PM in order to power off MU when it is unused. However,
the runtime suspend/resume can ONLY be implemented in mailbox's
.shutdown/.startup callback, so its consumer needs to call
mbox_request_channel()/mbox_free_channel() in consumer driver's
runtime PM callback, then the MU's power will be ON/OFF along with
consumer's runtime PM status.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-04-13 05:25:30 -07:00
|
|
|
pm_runtime_put_sync(priv->dev);
|
2018-08-02 22:29:19 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static const struct mbox_chan_ops imx_mu_ops = {
|
|
|
|
.send_data = imx_mu_send_data,
|
|
|
|
.startup = imx_mu_startup,
|
|
|
|
.shutdown = imx_mu_shutdown,
|
|
|
|
};
|
|
|
|
|
2021-10-22 03:18:56 -07:00
|
|
|
static struct mbox_chan *imx_mu_specific_xlate(struct mbox_controller *mbox,
|
|
|
|
const struct of_phandle_args *sp)
|
mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
|
|
|
{
|
|
|
|
u32 type, idx, chan;
|
|
|
|
|
|
|
|
if (sp->args_count != 2) {
|
|
|
|
dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
|
|
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
type = sp->args[0]; /* channel type */
|
|
|
|
idx = sp->args[1]; /* index */
|
|
|
|
|
|
|
|
switch (type) {
|
|
|
|
case IMX_MU_TYPE_TX:
|
|
|
|
case IMX_MU_TYPE_RX:
|
|
|
|
if (idx != 0)
|
|
|
|
dev_err(mbox->dev, "Invalid chan idx: %d\n", idx);
|
|
|
|
chan = type;
|
|
|
|
break;
|
|
|
|
case IMX_MU_TYPE_RXDB:
|
|
|
|
chan = 2 + idx;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_err(mbox->dev, "Invalid chan type: %d\n", type);
|
2020-04-07 02:27:53 -07:00
|
|
|
return ERR_PTR(-EINVAL);
|
mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
if (chan >= mbox->num_chans) {
|
|
|
|
dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
|
|
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
return &mbox->chans[chan];
|
|
|
|
}
|
|
|
|
|
2018-08-02 22:29:19 -07:00
|
|
|
static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,
|
|
|
|
const struct of_phandle_args *sp)
|
|
|
|
{
|
2023-09-17 05:43:51 -07:00
|
|
|
struct mbox_chan *p_chan;
|
2018-08-02 22:29:19 -07:00
|
|
|
u32 type, idx, chan;
|
|
|
|
|
|
|
|
if (sp->args_count != 2) {
|
|
|
|
dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
|
|
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
type = sp->args[0]; /* channel type */
|
|
|
|
idx = sp->args[1]; /* index */
|
|
|
|
|
2023-09-17 05:43:51 -07:00
|
|
|
/* RST only supports 1 channel */
|
|
|
|
if ((type == IMX_MU_TYPE_RST) && idx) {
|
|
|
|
dev_err(mbox->dev, "Invalid RST channel %d\n", idx);
|
|
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
chan = type * 4 + idx;
|
2018-08-02 22:29:19 -07:00
|
|
|
if (chan >= mbox->num_chans) {
|
|
|
|
dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
|
|
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
}
|
|
|
|
|
2023-09-17 05:43:51 -07:00
|
|
|
p_chan = &mbox->chans[chan];
|
|
|
|
|
|
|
|
if (type == IMX_MU_TYPE_TXDB_V2)
|
|
|
|
p_chan->txdone_method = TXDONE_BY_ACK;
|
|
|
|
|
|
|
|
return p_chan;
|
2018-08-02 22:29:19 -07:00
|
|
|
}
|
|
|
|
|
2022-02-06 18:52:11 -07:00
|
|
|
static struct mbox_chan *imx_mu_seco_xlate(struct mbox_controller *mbox,
|
|
|
|
const struct of_phandle_args *sp)
|
|
|
|
{
|
|
|
|
u32 type;
|
|
|
|
|
|
|
|
if (sp->args_count < 1) {
|
|
|
|
dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
|
|
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
type = sp->args[0]; /* channel type */
|
|
|
|
|
|
|
|
/* Only supports TXDB and RXDB */
|
|
|
|
if (type == IMX_MU_TYPE_TX || type == IMX_MU_TYPE_RX) {
|
|
|
|
dev_err(mbox->dev, "Invalid type: %d\n", type);
|
|
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
return imx_mu_xlate(mbox, sp);
|
|
|
|
}
|
|
|
|
|
2024-02-18 22:22:38 -07:00
|
|
|
static void imx_mu_get_tr_rr(struct imx_mu_priv *priv)
|
|
|
|
{
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
if (priv->dcfg->type & IMX_MU_V2) {
|
|
|
|
val = imx_mu_read(priv, IMX_MU_V2_PAR_OFF);
|
|
|
|
priv->num_tr = FIELD_GET(IMX_MU_V2_TR_MASK, val);
|
|
|
|
priv->num_rr = FIELD_GET(IMX_MU_V2_RR_MASK, val);
|
|
|
|
} else {
|
|
|
|
priv->num_tr = 4;
|
|
|
|
priv->num_rr = 4;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2024-02-18 22:22:37 -07:00
|
|
|
static int imx_mu_init_generic(struct imx_mu_priv *priv)
|
2018-08-02 22:29:19 -07:00
|
|
|
{
|
2020-03-19 00:49:51 -07:00
|
|
|
unsigned int i;
|
2022-08-03 00:53:26 -07:00
|
|
|
unsigned int val;
|
2020-03-19 00:49:51 -07:00
|
|
|
|
2024-02-18 22:22:38 -07:00
|
|
|
if (priv->num_rr > 4 || priv->num_tr > 4) {
|
|
|
|
WARN_ONCE(true, "%s not support TR/RR larger than 4\n", __func__);
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
}
|
|
|
|
|
2020-03-19 00:49:51 -07:00
|
|
|
for (i = 0; i < IMX_MU_CHANS; i++) {
|
|
|
|
struct imx_mu_con_priv *cp = &priv->con_priv[i];
|
|
|
|
|
|
|
|
cp->idx = i % 4;
|
|
|
|
cp->type = i >> 2;
|
|
|
|
cp->chan = &priv->mbox_chans[i];
|
|
|
|
priv->mbox_chans[i].con_priv = cp;
|
|
|
|
snprintf(cp->irq_desc, sizeof(cp->irq_desc),
|
2024-07-29 00:47:09 -07:00
|
|
|
"%s[%i-%i]", dev_name(priv->dev), cp->type, cp->idx);
|
2020-03-19 00:49:51 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
priv->mbox.num_chans = IMX_MU_CHANS;
|
|
|
|
priv->mbox.of_xlate = imx_mu_xlate;
|
|
|
|
|
2018-08-02 22:29:19 -07:00
|
|
|
if (priv->side_b)
|
2024-02-18 22:22:37 -07:00
|
|
|
return 0;
|
2018-08-02 22:29:19 -07:00
|
|
|
|
|
|
|
/* Set default MU configuration */
|
2021-05-28 03:06:02 -07:00
|
|
|
for (i = 0; i < IMX_MU_xCR_MAX; i++)
|
|
|
|
imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
|
2022-08-03 00:53:26 -07:00
|
|
|
|
|
|
|
/* Clear any pending GIP */
|
|
|
|
val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);
|
|
|
|
imx_mu_write(priv, val, priv->dcfg->xSR[IMX_MU_GSR]);
|
|
|
|
|
|
|
|
/* Clear any pending RSR */
|
2024-02-18 22:22:38 -07:00
|
|
|
for (i = 0; i < priv->num_rr; i++)
|
|
|
|
imx_mu_read(priv, priv->dcfg->xRR + i * 4);
|
2024-02-18 22:22:37 -07:00
|
|
|
|
|
|
|
return 0;
|
2018-08-02 22:29:19 -07:00
|
|
|
}
|
|
|
|
|
2024-02-18 22:22:37 -07:00
|
|
|
static int imx_mu_init_specific(struct imx_mu_priv *priv)
|
mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
|
|
|
{
|
|
|
|
unsigned int i;
|
2021-10-22 03:18:56 -07:00
|
|
|
int num_chans = priv->dcfg->type & IMX_MU_V2_S4 ? IMX_MU_S4_CHANS : IMX_MU_SCU_CHANS;
|
mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
|
|
|
|
2021-10-22 03:18:56 -07:00
|
|
|
for (i = 0; i < num_chans; i++) {
|
mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
|
|
|
struct imx_mu_con_priv *cp = &priv->con_priv[i];
|
|
|
|
|
|
|
|
cp->idx = i < 2 ? 0 : i - 2;
|
|
|
|
cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB;
|
|
|
|
cp->chan = &priv->mbox_chans[i];
|
|
|
|
priv->mbox_chans[i].con_priv = cp;
|
|
|
|
snprintf(cp->irq_desc, sizeof(cp->irq_desc),
|
2024-07-29 00:47:09 -07:00
|
|
|
"%s[%i-%i]", dev_name(priv->dev), cp->type, cp->idx);
|
mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
|
|
|
}
|
|
|
|
|
2021-10-22 03:18:56 -07:00
|
|
|
priv->mbox.num_chans = num_chans;
|
|
|
|
priv->mbox.of_xlate = imx_mu_specific_xlate;
|
mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
|
|
|
|
|
|
|
/* Set default MU configuration */
|
2021-05-28 03:06:02 -07:00
|
|
|
for (i = 0; i < IMX_MU_xCR_MAX; i++)
|
|
|
|
imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
|
2024-02-18 22:22:37 -07:00
|
|
|
|
|
|
|
return 0;
|
mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
|
|
|
}
|
|
|
|
|
2024-02-18 22:22:37 -07:00
|
|
|
static int imx_mu_init_seco(struct imx_mu_priv *priv)
|
2022-02-06 18:52:11 -07:00
|
|
|
{
|
2024-02-18 22:22:37 -07:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = imx_mu_init_generic(priv);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2022-02-06 18:52:11 -07:00
|
|
|
priv->mbox.of_xlate = imx_mu_seco_xlate;
|
2024-02-18 22:22:37 -07:00
|
|
|
|
|
|
|
return 0;
|
2022-02-06 18:52:11 -07:00
|
|
|
}
|
|
|
|
|
2018-08-02 22:29:19 -07:00
|
|
|
static int imx_mu_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
struct device_node *np = dev->of_node;
|
|
|
|
struct imx_mu_priv *priv;
|
2019-10-09 01:07:21 -07:00
|
|
|
const struct imx_mu_dcfg *dcfg;
|
2022-03-09 03:03:44 -07:00
|
|
|
int i, ret;
|
2021-10-22 03:18:56 -07:00
|
|
|
u32 size;
|
2018-08-02 22:29:19 -07:00
|
|
|
|
|
|
|
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
|
|
|
if (!priv)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
priv->dev = dev;
|
|
|
|
|
2019-03-31 22:15:24 -07:00
|
|
|
priv->base = devm_platform_ioremap_resource(pdev, 0);
|
2018-08-02 22:29:19 -07:00
|
|
|
if (IS_ERR(priv->base))
|
|
|
|
return PTR_ERR(priv->base);
|
|
|
|
|
2019-10-09 01:07:21 -07:00
|
|
|
dcfg = of_device_get_match_data(dev);
|
|
|
|
if (!dcfg)
|
|
|
|
return -EINVAL;
|
|
|
|
priv->dcfg = dcfg;
|
2022-03-09 03:03:44 -07:00
|
|
|
if (priv->dcfg->type & IMX_MU_V2_IRQ) {
|
|
|
|
priv->irq[IMX_MU_TYPE_TX] = platform_get_irq_byname(pdev, "tx");
|
|
|
|
if (priv->irq[IMX_MU_TYPE_TX] < 0)
|
|
|
|
return priv->irq[IMX_MU_TYPE_TX];
|
|
|
|
priv->irq[IMX_MU_TYPE_RX] = platform_get_irq_byname(pdev, "rx");
|
|
|
|
if (priv->irq[IMX_MU_TYPE_RX] < 0)
|
|
|
|
return priv->irq[IMX_MU_TYPE_RX];
|
|
|
|
} else {
|
|
|
|
ret = platform_get_irq(pdev, 0);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
for (i = 0; i < IMX_MU_CHANS; i++)
|
|
|
|
priv->irq[i] = ret;
|
|
|
|
}
|
2019-10-09 01:07:21 -07:00
|
|
|
|
2021-10-22 03:18:56 -07:00
|
|
|
if (priv->dcfg->type & IMX_MU_V2_S4)
|
|
|
|
size = sizeof(struct imx_s4_rpc_msg_max);
|
|
|
|
else
|
|
|
|
size = sizeof(struct imx_sc_rpc_msg_max);
|
|
|
|
|
|
|
|
priv->msg = devm_kzalloc(dev, size, GFP_KERNEL);
|
2021-11-24 07:51:26 -07:00
|
|
|
if (!priv->msg)
|
|
|
|
return -ENOMEM;
|
2021-10-22 03:18:56 -07:00
|
|
|
|
2018-08-02 22:29:19 -07:00
|
|
|
priv->clk = devm_clk_get(dev, NULL);
|
|
|
|
if (IS_ERR(priv->clk)) {
|
|
|
|
if (PTR_ERR(priv->clk) != -ENOENT)
|
|
|
|
return PTR_ERR(priv->clk);
|
|
|
|
|
|
|
|
priv->clk = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = clk_prepare_enable(priv->clk);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Failed to enable clock\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2024-02-18 22:22:38 -07:00
|
|
|
imx_mu_get_tr_rr(priv);
|
|
|
|
|
2018-08-02 22:29:19 -07:00
|
|
|
priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");
|
|
|
|
|
2024-02-18 22:22:37 -07:00
|
|
|
ret = priv->dcfg->init(priv);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Failed to init MU\n");
|
|
|
|
goto disable_clk;
|
|
|
|
}
|
2020-03-19 00:49:51 -07:00
|
|
|
|
2018-08-02 22:29:19 -07:00
|
|
|
spin_lock_init(&priv->xcr_lock);
|
|
|
|
|
|
|
|
priv->mbox.dev = dev;
|
|
|
|
priv->mbox.ops = &imx_mu_ops;
|
|
|
|
priv->mbox.chans = priv->mbox_chans;
|
|
|
|
priv->mbox.txdone_irq = true;
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, priv);
|
|
|
|
|
mailbox: imx: Support runtime PM
Some power hungry sub-systems like VPU has its own MUs which also
use mailbox driver, current mailbox driver uses platform driver
model and MU's power will be ON after driver probed and left ON
there, it may cause the whole sub-system can NOT enter lower power
mode, take VPU driver for example, it has runtime PM support, but
due to its MU always ON, the VPU sub-system will be always ON and
consume many power during kernel idle.
To save power in kernel idle, mailbox driver needs to support
runtime PM in order to power off MU when it is unused. However,
the runtime suspend/resume can ONLY be implemented in mailbox's
.shutdown/.startup callback, so its consumer needs to call
mbox_request_channel()/mbox_free_channel() in consumer driver's
runtime PM callback, then the MU's power will be ON/OFF along with
consumer's runtime PM status.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-04-13 05:25:30 -07:00
|
|
|
ret = devm_mbox_controller_register(dev, &priv->mbox);
|
2024-02-18 22:22:37 -07:00
|
|
|
if (ret)
|
|
|
|
goto disable_clk;
|
mailbox: imx: Support runtime PM
Some power hungry sub-systems like VPU has its own MUs which also
use mailbox driver, current mailbox driver uses platform driver
model and MU's power will be ON after driver probed and left ON
there, it may cause the whole sub-system can NOT enter lower power
mode, take VPU driver for example, it has runtime PM support, but
due to its MU always ON, the VPU sub-system will be always ON and
consume many power during kernel idle.
To save power in kernel idle, mailbox driver needs to support
runtime PM in order to power off MU when it is unused. However,
the runtime suspend/resume can ONLY be implemented in mailbox's
.shutdown/.startup callback, so its consumer needs to call
mbox_request_channel()/mbox_free_channel() in consumer driver's
runtime PM callback, then the MU's power will be ON/OFF along with
consumer's runtime PM status.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-04-13 05:25:30 -07:00
|
|
|
|
2024-02-18 22:22:39 -07:00
|
|
|
of_platform_populate(dev->of_node, NULL, NULL, dev);
|
|
|
|
|
mailbox: imx: Support runtime PM
Some power hungry sub-systems like VPU has its own MUs which also
use mailbox driver, current mailbox driver uses platform driver
model and MU's power will be ON after driver probed and left ON
there, it may cause the whole sub-system can NOT enter lower power
mode, take VPU driver for example, it has runtime PM support, but
due to its MU always ON, the VPU sub-system will be always ON and
consume many power during kernel idle.
To save power in kernel idle, mailbox driver needs to support
runtime PM in order to power off MU when it is unused. However,
the runtime suspend/resume can ONLY be implemented in mailbox's
.shutdown/.startup callback, so its consumer needs to call
mbox_request_channel()/mbox_free_channel() in consumer driver's
runtime PM callback, then the MU's power will be ON/OFF along with
consumer's runtime PM status.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-04-13 05:25:30 -07:00
|
|
|
pm_runtime_enable(dev);
|
|
|
|
|
2022-04-26 22:41:00 -07:00
|
|
|
ret = pm_runtime_resume_and_get(dev);
|
|
|
|
if (ret < 0)
|
mailbox: imx: Support runtime PM
Some power hungry sub-systems like VPU has its own MUs which also
use mailbox driver, current mailbox driver uses platform driver
model and MU's power will be ON after driver probed and left ON
there, it may cause the whole sub-system can NOT enter lower power
mode, take VPU driver for example, it has runtime PM support, but
due to its MU always ON, the VPU sub-system will be always ON and
consume many power during kernel idle.
To save power in kernel idle, mailbox driver needs to support
runtime PM in order to power off MU when it is unused. However,
the runtime suspend/resume can ONLY be implemented in mailbox's
.shutdown/.startup callback, so its consumer needs to call
mbox_request_channel()/mbox_free_channel() in consumer driver's
runtime PM callback, then the MU's power will be ON/OFF along with
consumer's runtime PM status.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-04-13 05:25:30 -07:00
|
|
|
goto disable_runtime_pm;
|
|
|
|
|
|
|
|
ret = pm_runtime_put_sync(dev);
|
|
|
|
if (ret < 0)
|
|
|
|
goto disable_runtime_pm;
|
|
|
|
|
mailbox: imx: Add runtime PM callback to handle MU clocks
Some of i.MX8M SoCs have MU clock, they need to be managed in runtime
to make sure the MU clock can be off in runtime, add runtime PM callback
to handle MU clock.
And on i.MX8MP, the MU clock is combined with power domain and runtime
PM is enabled for the clock driver, during noirq suspend/resume phase,
runtime PM is disabled by device suspend, but the MU context save/restore
needs to enable MU clock for register access, calling clock prepare/enable
will trigger runtime resume failure and lead to system suspend failed.
Actually, the MU context save/restore is ONLY necessary for SCU IPC MU,
other MUs especially on i.MX8MP platforms which have MU clock assigned,
they need to runtime request/free mailbox channel in the consumer driver,
so no need to save/restore MU context for them, hence it can avoid this
issue, so the MU context save/restore is ONLY applied to i.MX platforms
MU instance without clock present.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-06-02 22:15:43 -07:00
|
|
|
clk_disable_unprepare(priv->clk);
|
|
|
|
|
mailbox: imx: Support runtime PM
Some power hungry sub-systems like VPU has its own MUs which also
use mailbox driver, current mailbox driver uses platform driver
model and MU's power will be ON after driver probed and left ON
there, it may cause the whole sub-system can NOT enter lower power
mode, take VPU driver for example, it has runtime PM support, but
due to its MU always ON, the VPU sub-system will be always ON and
consume many power during kernel idle.
To save power in kernel idle, mailbox driver needs to support
runtime PM in order to power off MU when it is unused. However,
the runtime suspend/resume can ONLY be implemented in mailbox's
.shutdown/.startup callback, so its consumer needs to call
mbox_request_channel()/mbox_free_channel() in consumer driver's
runtime PM callback, then the MU's power will be ON/OFF along with
consumer's runtime PM status.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-04-13 05:25:30 -07:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
disable_runtime_pm:
|
|
|
|
pm_runtime_disable(dev);
|
2024-02-18 22:22:37 -07:00
|
|
|
disable_clk:
|
mailbox: imx: Add runtime PM callback to handle MU clocks
Some of i.MX8M SoCs have MU clock, they need to be managed in runtime
to make sure the MU clock can be off in runtime, add runtime PM callback
to handle MU clock.
And on i.MX8MP, the MU clock is combined with power domain and runtime
PM is enabled for the clock driver, during noirq suspend/resume phase,
runtime PM is disabled by device suspend, but the MU context save/restore
needs to enable MU clock for register access, calling clock prepare/enable
will trigger runtime resume failure and lead to system suspend failed.
Actually, the MU context save/restore is ONLY necessary for SCU IPC MU,
other MUs especially on i.MX8MP platforms which have MU clock assigned,
they need to runtime request/free mailbox channel in the consumer driver,
so no need to save/restore MU context for them, hence it can avoid this
issue, so the MU context save/restore is ONLY applied to i.MX platforms
MU instance without clock present.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-06-02 22:15:43 -07:00
|
|
|
clk_disable_unprepare(priv->clk);
|
mailbox: imx: Support runtime PM
Some power hungry sub-systems like VPU has its own MUs which also
use mailbox driver, current mailbox driver uses platform driver
model and MU's power will be ON after driver probed and left ON
there, it may cause the whole sub-system can NOT enter lower power
mode, take VPU driver for example, it has runtime PM support, but
due to its MU always ON, the VPU sub-system will be always ON and
consume many power during kernel idle.
To save power in kernel idle, mailbox driver needs to support
runtime PM in order to power off MU when it is unused. However,
the runtime suspend/resume can ONLY be implemented in mailbox's
.shutdown/.startup callback, so its consumer needs to call
mbox_request_channel()/mbox_free_channel() in consumer driver's
runtime PM callback, then the MU's power will be ON/OFF along with
consumer's runtime PM status.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-04-13 05:25:30 -07:00
|
|
|
return ret;
|
2018-08-02 22:29:19 -07:00
|
|
|
}
|
|
|
|
|
2023-12-27 14:02:31 -07:00
|
|
|
static void imx_mu_remove(struct platform_device *pdev)
|
2018-08-02 22:29:19 -07:00
|
|
|
{
|
|
|
|
struct imx_mu_priv *priv = platform_get_drvdata(pdev);
|
|
|
|
|
mailbox: imx: Support runtime PM
Some power hungry sub-systems like VPU has its own MUs which also
use mailbox driver, current mailbox driver uses platform driver
model and MU's power will be ON after driver probed and left ON
there, it may cause the whole sub-system can NOT enter lower power
mode, take VPU driver for example, it has runtime PM support, but
due to its MU always ON, the VPU sub-system will be always ON and
consume many power during kernel idle.
To save power in kernel idle, mailbox driver needs to support
runtime PM in order to power off MU when it is unused. However,
the runtime suspend/resume can ONLY be implemented in mailbox's
.shutdown/.startup callback, so its consumer needs to call
mbox_request_channel()/mbox_free_channel() in consumer driver's
runtime PM callback, then the MU's power will be ON/OFF along with
consumer's runtime PM status.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-04-13 05:25:30 -07:00
|
|
|
pm_runtime_disable(priv->dev);
|
2018-08-02 22:29:19 -07:00
|
|
|
}
|
|
|
|
|
2020-03-19 00:49:51 -07:00
|
|
|
static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
|
|
|
|
.tx = imx_mu_generic_tx,
|
|
|
|
.rx = imx_mu_generic_rx,
|
2022-02-06 18:52:10 -07:00
|
|
|
.rxdb = imx_mu_generic_rxdb,
|
2020-03-19 00:49:51 -07:00
|
|
|
.init = imx_mu_init_generic,
|
2021-05-28 03:06:01 -07:00
|
|
|
.xTR = 0x0,
|
|
|
|
.xRR = 0x10,
|
2021-05-28 03:06:02 -07:00
|
|
|
.xSR = {0x20, 0x20, 0x20, 0x20},
|
2022-06-15 06:00:09 -07:00
|
|
|
.xCR = {0x24, 0x24, 0x24, 0x24, 0x24},
|
2020-03-19 00:49:51 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
|
|
|
|
.tx = imx_mu_generic_tx,
|
|
|
|
.rx = imx_mu_generic_rx,
|
2022-02-06 18:52:10 -07:00
|
|
|
.rxdb = imx_mu_generic_rxdb,
|
2020-03-19 00:49:51 -07:00
|
|
|
.init = imx_mu_init_generic,
|
2021-05-28 03:06:01 -07:00
|
|
|
.xTR = 0x20,
|
|
|
|
.xRR = 0x40,
|
2021-05-28 03:06:02 -07:00
|
|
|
.xSR = {0x60, 0x60, 0x60, 0x60},
|
2022-09-18 20:01:36 -07:00
|
|
|
.xCR = {0x64, 0x64, 0x64, 0x64, 0x64},
|
2020-03-19 00:49:51 -07:00
|
|
|
};
|
|
|
|
|
2021-05-28 03:06:03 -07:00
|
|
|
static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = {
|
|
|
|
.tx = imx_mu_generic_tx,
|
|
|
|
.rx = imx_mu_generic_rx,
|
2022-02-06 18:52:10 -07:00
|
|
|
.rxdb = imx_mu_generic_rxdb,
|
2021-05-28 03:06:03 -07:00
|
|
|
.init = imx_mu_init_generic,
|
|
|
|
.type = IMX_MU_V2,
|
|
|
|
.xTR = 0x200,
|
|
|
|
.xRR = 0x280,
|
|
|
|
.xSR = {0xC, 0x118, 0x124, 0x12C},
|
2022-06-15 06:00:09 -07:00
|
|
|
.xCR = {0x8, 0x110, 0x114, 0x120, 0x128},
|
2021-05-28 03:06:03 -07:00
|
|
|
};
|
|
|
|
|
2021-10-22 03:18:56 -07:00
|
|
|
static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp_s4 = {
|
|
|
|
.tx = imx_mu_specific_tx,
|
|
|
|
.rx = imx_mu_specific_rx,
|
|
|
|
.init = imx_mu_init_specific,
|
|
|
|
.type = IMX_MU_V2 | IMX_MU_V2_S4,
|
|
|
|
.xTR = 0x200,
|
|
|
|
.xRR = 0x280,
|
|
|
|
.xSR = {0xC, 0x118, 0x124, 0x12C},
|
2022-09-18 20:01:36 -07:00
|
|
|
.xCR = {0x8, 0x110, 0x114, 0x120, 0x128},
|
2021-10-22 03:18:56 -07:00
|
|
|
};
|
|
|
|
|
2022-03-09 03:03:45 -07:00
|
|
|
static const struct imx_mu_dcfg imx_mu_cfg_imx93_s4 = {
|
|
|
|
.tx = imx_mu_specific_tx,
|
|
|
|
.rx = imx_mu_specific_rx,
|
|
|
|
.init = imx_mu_init_specific,
|
|
|
|
.type = IMX_MU_V2 | IMX_MU_V2_S4 | IMX_MU_V2_IRQ,
|
|
|
|
.xTR = 0x200,
|
|
|
|
.xRR = 0x280,
|
|
|
|
.xSR = {0xC, 0x118, 0x124, 0x12C},
|
2022-09-18 20:01:36 -07:00
|
|
|
.xCR = {0x8, 0x110, 0x114, 0x120, 0x128},
|
2022-03-09 03:03:45 -07:00
|
|
|
};
|
|
|
|
|
mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
|
|
|
static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
|
2021-10-22 03:18:56 -07:00
|
|
|
.tx = imx_mu_specific_tx,
|
|
|
|
.rx = imx_mu_specific_rx,
|
|
|
|
.init = imx_mu_init_specific,
|
2022-02-06 18:52:10 -07:00
|
|
|
.rxdb = imx_mu_generic_rxdb,
|
2021-05-28 03:06:03 -07:00
|
|
|
.xTR = 0x0,
|
|
|
|
.xRR = 0x10,
|
2021-05-28 03:06:02 -07:00
|
|
|
.xSR = {0x20, 0x20, 0x20, 0x20},
|
2022-09-18 20:01:36 -07:00
|
|
|
.xCR = {0x24, 0x24, 0x24, 0x24, 0x24},
|
mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
|
|
|
};
|
|
|
|
|
2022-02-06 18:52:11 -07:00
|
|
|
static const struct imx_mu_dcfg imx_mu_cfg_imx8_seco = {
|
|
|
|
.tx = imx_mu_seco_tx,
|
|
|
|
.rx = imx_mu_generic_rx,
|
|
|
|
.rxdb = imx_mu_seco_rxdb,
|
|
|
|
.init = imx_mu_init_seco,
|
|
|
|
.xTR = 0x0,
|
|
|
|
.xRR = 0x10,
|
|
|
|
.xSR = {0x20, 0x20, 0x20, 0x20},
|
2022-09-18 20:01:36 -07:00
|
|
|
.xCR = {0x24, 0x24, 0x24, 0x24, 0x24},
|
2022-02-06 18:52:11 -07:00
|
|
|
};
|
|
|
|
|
2018-08-02 22:29:19 -07:00
|
|
|
static const struct of_device_id imx_mu_dt_ids[] = {
|
2019-10-09 01:07:21 -07:00
|
|
|
{ .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
|
|
|
|
{ .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
|
2021-05-28 03:06:03 -07:00
|
|
|
{ .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp },
|
2021-10-22 03:18:56 -07:00
|
|
|
{ .compatible = "fsl,imx8ulp-mu-s4", .data = &imx_mu_cfg_imx8ulp_s4 },
|
2022-03-09 03:03:45 -07:00
|
|
|
{ .compatible = "fsl,imx93-mu-s4", .data = &imx_mu_cfg_imx93_s4 },
|
2024-02-18 22:22:40 -07:00
|
|
|
{ .compatible = "fsl,imx95-mu", .data = &imx_mu_cfg_imx8ulp },
|
|
|
|
{ .compatible = "fsl,imx95-mu-ele", .data = &imx_mu_cfg_imx8ulp_s4 },
|
|
|
|
{ .compatible = "fsl,imx95-mu-v2x", .data = &imx_mu_cfg_imx8ulp_s4 },
|
mailbox: imx: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.
Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example, when
a four-word message is desired, only one of the registers needs to
have its corresponding interrupt enable bit set at the receiver side;
the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other
register (which triggers an interrupt at the receiver side).
i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.
To make SCU MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg larger than 4 u32 words.
- Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19 00:49:52 -07:00
|
|
|
{ .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
|
2022-02-06 18:52:11 -07:00
|
|
|
{ .compatible = "fsl,imx8-mu-seco", .data = &imx_mu_cfg_imx8_seco },
|
2018-08-02 22:29:19 -07:00
|
|
|
{ },
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);
|
|
|
|
|
2020-06-22 18:04:03 -07:00
|
|
|
static int __maybe_unused imx_mu_suspend_noirq(struct device *dev)
|
2020-06-02 22:15:42 -07:00
|
|
|
{
|
|
|
|
struct imx_mu_priv *priv = dev_get_drvdata(dev);
|
2021-05-28 03:06:02 -07:00
|
|
|
int i;
|
2020-06-02 22:15:42 -07:00
|
|
|
|
2021-05-28 03:06:02 -07:00
|
|
|
if (!priv->clk) {
|
|
|
|
for (i = 0; i < IMX_MU_xCR_MAX; i++)
|
|
|
|
priv->xcr[i] = imx_mu_read(priv, priv->dcfg->xCR[i]);
|
|
|
|
}
|
2020-06-02 22:15:42 -07:00
|
|
|
|
2022-02-06 18:52:06 -07:00
|
|
|
priv->suspend = true;
|
|
|
|
|
2020-06-02 22:15:42 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-06-22 18:04:03 -07:00
|
|
|
static int __maybe_unused imx_mu_resume_noirq(struct device *dev)
|
2020-06-02 22:15:42 -07:00
|
|
|
{
|
|
|
|
struct imx_mu_priv *priv = dev_get_drvdata(dev);
|
2021-05-28 03:06:02 -07:00
|
|
|
int i;
|
2020-06-02 22:15:42 -07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* ONLY restore MU when context lost, the TIE could
|
|
|
|
* be set during noirq resume as there is MU data
|
|
|
|
* communication going on, and restore the saved
|
|
|
|
* value will overwrite the TIE and cause MU data
|
|
|
|
* send failed, may lead to system freeze. This issue
|
|
|
|
* is observed by testing freeze mode suspend.
|
|
|
|
*/
|
2022-02-06 18:52:07 -07:00
|
|
|
if (!priv->clk && !imx_mu_read(priv, priv->dcfg->xCR[0])) {
|
2021-05-28 03:06:02 -07:00
|
|
|
for (i = 0; i < IMX_MU_xCR_MAX; i++)
|
|
|
|
imx_mu_write(priv, priv->xcr[i], priv->dcfg->xCR[i]);
|
|
|
|
}
|
2020-06-02 22:15:42 -07:00
|
|
|
|
2022-02-06 18:52:06 -07:00
|
|
|
priv->suspend = false;
|
|
|
|
|
2020-06-02 22:15:42 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-06-22 18:04:03 -07:00
|
|
|
static int __maybe_unused imx_mu_runtime_suspend(struct device *dev)
|
mailbox: imx: Add runtime PM callback to handle MU clocks
Some of i.MX8M SoCs have MU clock, they need to be managed in runtime
to make sure the MU clock can be off in runtime, add runtime PM callback
to handle MU clock.
And on i.MX8MP, the MU clock is combined with power domain and runtime
PM is enabled for the clock driver, during noirq suspend/resume phase,
runtime PM is disabled by device suspend, but the MU context save/restore
needs to enable MU clock for register access, calling clock prepare/enable
will trigger runtime resume failure and lead to system suspend failed.
Actually, the MU context save/restore is ONLY necessary for SCU IPC MU,
other MUs especially on i.MX8MP platforms which have MU clock assigned,
they need to runtime request/free mailbox channel in the consumer driver,
so no need to save/restore MU context for them, hence it can avoid this
issue, so the MU context save/restore is ONLY applied to i.MX platforms
MU instance without clock present.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-06-02 22:15:43 -07:00
|
|
|
{
|
|
|
|
struct imx_mu_priv *priv = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
clk_disable_unprepare(priv->clk);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-06-22 18:04:03 -07:00
|
|
|
static int __maybe_unused imx_mu_runtime_resume(struct device *dev)
|
mailbox: imx: Add runtime PM callback to handle MU clocks
Some of i.MX8M SoCs have MU clock, they need to be managed in runtime
to make sure the MU clock can be off in runtime, add runtime PM callback
to handle MU clock.
And on i.MX8MP, the MU clock is combined with power domain and runtime
PM is enabled for the clock driver, during noirq suspend/resume phase,
runtime PM is disabled by device suspend, but the MU context save/restore
needs to enable MU clock for register access, calling clock prepare/enable
will trigger runtime resume failure and lead to system suspend failed.
Actually, the MU context save/restore is ONLY necessary for SCU IPC MU,
other MUs especially on i.MX8MP platforms which have MU clock assigned,
they need to runtime request/free mailbox channel in the consumer driver,
so no need to save/restore MU context for them, hence it can avoid this
issue, so the MU context save/restore is ONLY applied to i.MX platforms
MU instance without clock present.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-06-02 22:15:43 -07:00
|
|
|
{
|
|
|
|
struct imx_mu_priv *priv = dev_get_drvdata(dev);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = clk_prepare_enable(priv->clk);
|
|
|
|
if (ret)
|
|
|
|
dev_err(dev, "failed to enable clock\n");
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2020-06-02 22:15:42 -07:00
|
|
|
static const struct dev_pm_ops imx_mu_pm_ops = {
|
|
|
|
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_mu_suspend_noirq,
|
|
|
|
imx_mu_resume_noirq)
|
mailbox: imx: Add runtime PM callback to handle MU clocks
Some of i.MX8M SoCs have MU clock, they need to be managed in runtime
to make sure the MU clock can be off in runtime, add runtime PM callback
to handle MU clock.
And on i.MX8MP, the MU clock is combined with power domain and runtime
PM is enabled for the clock driver, during noirq suspend/resume phase,
runtime PM is disabled by device suspend, but the MU context save/restore
needs to enable MU clock for register access, calling clock prepare/enable
will trigger runtime resume failure and lead to system suspend failed.
Actually, the MU context save/restore is ONLY necessary for SCU IPC MU,
other MUs especially on i.MX8MP platforms which have MU clock assigned,
they need to runtime request/free mailbox channel in the consumer driver,
so no need to save/restore MU context for them, hence it can avoid this
issue, so the MU context save/restore is ONLY applied to i.MX platforms
MU instance without clock present.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-06-02 22:15:43 -07:00
|
|
|
SET_RUNTIME_PM_OPS(imx_mu_runtime_suspend,
|
|
|
|
imx_mu_runtime_resume, NULL)
|
2020-06-02 22:15:42 -07:00
|
|
|
};
|
|
|
|
|
2018-08-02 22:29:19 -07:00
|
|
|
static struct platform_driver imx_mu_driver = {
|
|
|
|
.probe = imx_mu_probe,
|
2023-12-27 14:02:31 -07:00
|
|
|
.remove_new = imx_mu_remove,
|
2018-08-02 22:29:19 -07:00
|
|
|
.driver = {
|
|
|
|
.name = "imx_mu",
|
|
|
|
.of_match_table = imx_mu_dt_ids,
|
2020-06-02 22:15:42 -07:00
|
|
|
.pm = &imx_mu_pm_ops,
|
2018-08-02 22:29:19 -07:00
|
|
|
},
|
|
|
|
};
|
|
|
|
module_platform_driver(imx_mu_driver);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>");
|
|
|
|
MODULE_DESCRIPTION("Message Unit driver for i.MX");
|
|
|
|
MODULE_LICENSE("GPL v2");
|