2019-06-01 01:08:55 -07:00
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// SPDX-License-Identifier: GPL-2.0-only
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2008-02-04 23:28:26 -07:00
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/*
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2014-02-07 15:35:48 -07:00
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* PCA953x 4/8/16/24/40 bit I/O ports
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2008-02-04 23:28:26 -07:00
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*
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* Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
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* Copyright (C) 2007 Marvell International Ltd.
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*
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* Derived from drivers/i2c/chips/pca9539.c
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*/
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2023-09-01 06:40:41 -07:00
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#include <linux/atomic.h>
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2019-12-04 17:53:37 -07:00
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#include <linux/bitmap.h>
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2023-09-01 06:40:36 -07:00
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#include <linux/cleanup.h>
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2023-09-01 06:40:41 -07:00
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#include <linux/device.h>
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#include <linux/errno.h>
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2008-02-04 23:28:26 -07:00
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#include <linux/i2c.h>
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2017-03-22 07:11:12 -07:00
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#include <linux/init.h>
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#include <linux/interrupt.h>
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2023-09-01 06:40:41 -07:00
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#include <linux/irq.h>
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#include <linux/mod_devicetable.h>
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2017-03-22 07:11:12 -07:00
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#include <linux/module.h>
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2023-09-01 06:40:41 -07:00
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#include <linux/mutex.h>
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#include <linux/pm.h>
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2018-12-11 18:39:58 -07:00
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#include <linux/regmap.h>
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2017-03-22 07:11:12 -07:00
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#include <linux/regulator/consumer.h>
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2022-10-07 06:44:44 -07:00
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#include <linux/seq_file.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 01:04:11 -07:00
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#include <linux/slab.h>
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2017-03-22 07:11:12 -07:00
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2023-09-01 06:40:41 -07:00
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#include <linux/gpio/consumer.h>
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#include <linux/gpio/driver.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/platform_data/pca953x.h>
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2008-02-04 23:28:26 -07:00
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2018-04-28 09:31:31 -07:00
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#define PCA953X_INPUT 0x00
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#define PCA953X_OUTPUT 0x01
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#define PCA953X_INVERT 0x02
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#define PCA953X_DIRECTION 0x03
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2011-04-18 07:12:46 -07:00
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2019-08-01 10:39:36 -07:00
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#define REG_ADDR_MASK GENMASK(5, 0)
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#define REG_ADDR_EXT BIT(6)
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#define REG_ADDR_AI BIT(7)
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2012-05-09 00:46:17 -07:00
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2018-04-28 09:31:31 -07:00
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#define PCA957X_IN 0x00
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#define PCA957X_INVRT 0x01
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#define PCA957X_BKEN 0x02
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#define PCA957X_PUPD 0x03
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#define PCA957X_CFG 0x04
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#define PCA957X_OUT 0x05
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#define PCA957X_MSK 0x06
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#define PCA957X_INTS 0x07
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2011-04-18 07:12:46 -07:00
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2018-04-28 09:31:32 -07:00
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#define PCAL953X_OUT_STRENGTH 0x20
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2018-04-28 09:31:31 -07:00
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#define PCAL953X_IN_LATCH 0x22
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2018-04-28 09:31:32 -07:00
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#define PCAL953X_PULL_EN 0x23
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#define PCAL953X_PULL_SEL 0x24
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2018-04-28 09:31:31 -07:00
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#define PCAL953X_INT_MASK 0x25
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#define PCAL953X_INT_STAT 0x26
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2018-04-28 09:31:32 -07:00
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#define PCAL953X_OUT_CONF 0x27
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2016-04-06 21:56:32 -07:00
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2018-04-28 09:31:33 -07:00
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#define PCAL6524_INT_EDGE 0x28
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#define PCAL6524_INT_CLR 0x2a
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#define PCAL6524_IN_STATUS 0x2b
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#define PCAL6524_OUT_INDCONF 0x2c
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#define PCAL6524_DEBOUNCE 0x2d
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2019-08-01 10:39:36 -07:00
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#define PCA_GPIO_MASK GENMASK(7, 0)
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2018-05-16 21:59:48 -07:00
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2019-08-01 10:39:36 -07:00
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#define PCAL_GPIO_MASK GENMASK(4, 0)
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#define PCAL_PINCTRL_MASK GENMASK(6, 5)
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2018-05-16 21:59:48 -07:00
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2019-08-01 10:39:36 -07:00
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#define PCA_INT BIT(8)
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#define PCA_PCAL BIT(9)
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2019-03-05 02:13:46 -07:00
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#define PCA_LATCH_INT (PCA_PCAL | PCA_INT)
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2019-08-01 10:39:36 -07:00
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#define PCA953X_TYPE BIT(12)
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#define PCA957X_TYPE BIT(13)
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2022-09-14 08:15:57 -07:00
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#define PCAL653X_TYPE BIT(14)
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2019-08-01 10:39:36 -07:00
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#define PCA_TYPE_MASK GENMASK(15, 12)
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2015-10-01 04:20:27 -07:00
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#define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
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2010-03-05 14:44:36 -07:00
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2008-04-29 14:11:40 -07:00
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static const struct i2c_device_id pca953x_id[] = {
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2022-05-04 15:29:16 -07:00
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{ "pca6408", 8 | PCA953X_TYPE | PCA_INT, },
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2019-04-09 05:35:46 -07:00
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{ "pca6416", 16 | PCA953X_TYPE | PCA_INT, },
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2013-01-22 14:10:24 -07:00
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{ "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
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2021-01-15 09:46:56 -07:00
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{ "pca9506", 40 | PCA953X_TYPE | PCA_INT, },
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2011-04-18 07:12:46 -07:00
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{ "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
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{ "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
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{ "pca9536", 4 | PCA953X_TYPE, },
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{ "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
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{ "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
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{ "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
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{ "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
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{ "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
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{ "pca9556", 8 | PCA953X_TYPE, },
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{ "pca9557", 8 | PCA953X_TYPE, },
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{ "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
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{ "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
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2014-02-13 05:59:23 -07:00
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{ "pca9698", 40 | PCA953X_TYPE, },
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2011-04-18 07:12:46 -07:00
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2022-09-13 11:24:36 -07:00
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{ "pcal6408", 8 | PCA953X_TYPE | PCA_LATCH_INT, },
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2019-03-05 02:13:46 -07:00
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{ "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
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{ "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, },
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2022-09-14 08:15:57 -07:00
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{ "pcal6534", 34 | PCAL653X_TYPE | PCA_LATCH_INT, },
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2020-06-15 06:22:29 -07:00
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{ "pcal9535", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
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2020-09-30 02:20:53 -07:00
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{ "pcal9554b", 8 | PCA953X_TYPE | PCA_LATCH_INT, },
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2019-03-05 02:13:46 -07:00
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{ "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
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2016-06-14 15:57:56 -07:00
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2011-04-18 07:12:46 -07:00
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{ "max7310", 8 | PCA953X_TYPE, },
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{ "max7312", 16 | PCA953X_TYPE | PCA_INT, },
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{ "max7313", 16 | PCA953X_TYPE | PCA_INT, },
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{ "max7315", 8 | PCA953X_TYPE | PCA_INT, },
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2016-10-17 09:36:49 -07:00
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{ "max7318", 16 | PCA953X_TYPE | PCA_INT, },
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2011-04-18 07:12:46 -07:00
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{ "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
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{ "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
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{ "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
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2012-05-09 00:46:17 -07:00
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{ "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
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2023-08-24 16:16:25 -07:00
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{ "tca9538", 8 | PCA953X_TYPE | PCA_INT, },
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2015-09-29 03:55:44 -07:00
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{ "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
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2017-04-21 05:46:30 -07:00
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{ "tca9554", 8 | PCA953X_TYPE | PCA_INT, },
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2014-02-07 15:36:21 -07:00
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{ "xra1202", 8 | PCA953X_TYPE },
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2008-04-29 14:11:40 -07:00
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{ }
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2008-02-06 02:39:04 -07:00
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};
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2008-04-29 14:11:40 -07:00
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MODULE_DEVICE_TABLE(i2c, pca953x_id);
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2008-02-04 23:28:26 -07:00
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2020-06-05 06:40:34 -07:00
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#ifdef CONFIG_GPIO_PCA953X_IRQ
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2023-09-01 06:40:41 -07:00
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#include <linux/acpi.h>
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2020-06-05 06:40:34 -07:00
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#include <linux/dmi.h>
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2021-02-25 09:33:20 -07:00
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static const struct acpi_gpio_params pca953x_irq_gpios = { 0, 0, true };
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static const struct acpi_gpio_mapping pca953x_acpi_irq_gpios[] = {
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{ "irq-gpios", &pca953x_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER },
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{ }
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};
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static int pca953x_acpi_get_irq(struct device *dev)
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{
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int ret;
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ret = devm_acpi_dev_add_driver_gpios(dev, pca953x_acpi_irq_gpios);
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if (ret)
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dev_warn(dev, "can't add GPIO ACPI mapping\n");
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2024-04-11 10:22:32 -07:00
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ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq", 0);
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2021-02-25 09:33:20 -07:00
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if (ret < 0)
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return ret;
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dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret);
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return ret;
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}
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2020-06-05 06:40:34 -07:00
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static const struct dmi_system_id pca953x_dmi_acpi_irq_info[] = {
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{
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/*
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* On Intel Galileo Gen 2 board the IRQ pin of one of
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* the I²C GPIO expanders, which has GpioInt() resource,
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* is provided as an absolute number instead of being
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* relative. Since first controller (gpio-sch.c) and
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* second (gpio-dwapb.c) are at the fixed bases, we may
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* safely refer to the number in the global space to get
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* an IRQ out of it.
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*/
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.matches = {
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DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),
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},
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},
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{}
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};
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#endif
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2015-10-01 04:20:28 -07:00
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static const struct acpi_device_id pca953x_acpi_ids[] = {
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2019-03-05 02:13:46 -07:00
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{ "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
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2015-10-01 04:20:28 -07:00
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{ }
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};
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MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);
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2013-01-22 14:10:23 -07:00
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#define MAX_BANK 5
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#define BANK_SZ 8
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2019-12-04 17:53:37 -07:00
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#define MAX_LINE (MAX_BANK * BANK_SZ)
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2013-01-22 14:10:23 -07:00
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2016-06-08 22:32:04 -07:00
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#define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)
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2013-01-22 14:10:23 -07:00
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2016-09-09 02:17:34 -07:00
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struct pca953x_reg_config {
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int direction;
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int output;
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int input;
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2018-12-11 18:39:55 -07:00
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int invert;
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2016-09-09 02:17:34 -07:00
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};
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static const struct pca953x_reg_config pca953x_regs = {
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.direction = PCA953X_DIRECTION,
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.output = PCA953X_OUTPUT,
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.input = PCA953X_INPUT,
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2018-12-11 18:39:55 -07:00
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.invert = PCA953X_INVERT,
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2016-09-09 02:17:34 -07:00
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};
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static const struct pca953x_reg_config pca957x_regs = {
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.direction = PCA957X_CFG,
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.output = PCA957X_OUT,
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.input = PCA957X_IN,
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2018-12-11 18:39:55 -07:00
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.invert = PCA957X_INVRT,
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2016-09-09 02:17:34 -07:00
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};
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2008-02-06 02:39:03 -07:00
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struct pca953x_chip {
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2008-02-04 23:28:26 -07:00
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unsigned gpio_start;
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2011-02-10 16:01:23 -07:00
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struct mutex i2c_lock;
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2018-12-11 18:39:58 -07:00
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struct regmap *regmap;
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2008-02-04 23:28:26 -07:00
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2010-03-05 14:44:36 -07:00
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#ifdef CONFIG_GPIO_PCA953X_IRQ
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struct mutex irq_lock;
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2019-12-04 17:53:37 -07:00
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DECLARE_BITMAP(irq_mask, MAX_LINE);
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DECLARE_BITMAP(irq_stat, MAX_LINE);
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DECLARE_BITMAP(irq_trig_raise, MAX_LINE);
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DECLARE_BITMAP(irq_trig_fall, MAX_LINE);
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2010-03-05 14:44:36 -07:00
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#endif
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2019-03-20 03:39:27 -07:00
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atomic_t wakeup_path;
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2010-03-05 14:44:36 -07:00
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2008-02-04 23:28:26 -07:00
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struct i2c_client *client;
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|
struct gpio_chip gpio_chip;
|
2015-10-01 04:20:27 -07:00
|
|
|
unsigned long driver_data;
|
2016-07-28 20:39:55 -07:00
|
|
|
struct regulator *regulator;
|
2016-09-09 02:17:34 -07:00
|
|
|
|
|
|
|
const struct pca953x_reg_config *regs;
|
2022-09-14 08:15:57 -07:00
|
|
|
|
|
|
|
u8 (*recalc_addr)(struct pca953x_chip *chip, int reg, int off);
|
|
|
|
bool (*check_reg)(struct pca953x_chip *chip, unsigned int reg,
|
|
|
|
u32 checkbank);
|
2008-02-04 23:28:26 -07:00
|
|
|
};
|
|
|
|
|
2018-12-11 18:39:49 -07:00
|
|
|
static int pca953x_bank_shift(struct pca953x_chip *chip)
|
2013-01-22 14:10:23 -07:00
|
|
|
{
|
2018-12-11 18:39:49 -07:00
|
|
|
return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
|
|
|
|
}
|
2013-01-22 14:10:23 -07:00
|
|
|
|
2018-12-11 18:39:58 -07:00
|
|
|
#define PCA953x_BANK_INPUT BIT(0)
|
|
|
|
#define PCA953x_BANK_OUTPUT BIT(1)
|
|
|
|
#define PCA953x_BANK_POLARITY BIT(2)
|
|
|
|
#define PCA953x_BANK_CONFIG BIT(3)
|
2013-01-22 14:10:23 -07:00
|
|
|
|
2018-12-11 18:39:58 -07:00
|
|
|
#define PCA957x_BANK_INPUT BIT(0)
|
|
|
|
#define PCA957x_BANK_POLARITY BIT(1)
|
|
|
|
#define PCA957x_BANK_BUSHOLD BIT(2)
|
|
|
|
#define PCA957x_BANK_CONFIG BIT(4)
|
|
|
|
#define PCA957x_BANK_OUTPUT BIT(5)
|
|
|
|
|
|
|
|
#define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2)
|
2019-02-07 09:28:59 -07:00
|
|
|
#define PCAL9xxx_BANK_PULL_EN BIT(8 + 3)
|
|
|
|
#define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4)
|
2018-12-11 18:39:58 -07:00
|
|
|
#define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5)
|
|
|
|
#define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6)
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We care about the following registers:
|
|
|
|
* - Standard set, below 0x40, each port can be replicated up to 8 times
|
|
|
|
* - PCA953x standard
|
|
|
|
* Input port 0x00 + 0 * bank_size R
|
|
|
|
* Output port 0x00 + 1 * bank_size RW
|
|
|
|
* Polarity Inversion port 0x00 + 2 * bank_size RW
|
|
|
|
* Configuration port 0x00 + 3 * bank_size RW
|
|
|
|
* - PCA957x with mixed up registers
|
|
|
|
* Input port 0x00 + 0 * bank_size R
|
|
|
|
* Polarity Inversion port 0x00 + 1 * bank_size RW
|
|
|
|
* Bus hold port 0x00 + 2 * bank_size RW
|
|
|
|
* Configuration port 0x00 + 4 * bank_size RW
|
|
|
|
* Output port 0x00 + 5 * bank_size RW
|
|
|
|
*
|
|
|
|
* - Extended set, above 0x40, often chip specific.
|
|
|
|
* - PCAL6524/PCAL9555A with custom PCAL IRQ handling:
|
|
|
|
* Input latch register 0x40 + 2 * bank_size RW
|
2019-02-07 09:28:59 -07:00
|
|
|
* Pull-up/pull-down enable reg 0x40 + 3 * bank_size RW
|
|
|
|
* Pull-up/pull-down select reg 0x40 + 4 * bank_size RW
|
2018-12-11 18:39:58 -07:00
|
|
|
* Interrupt mask register 0x40 + 5 * bank_size RW
|
|
|
|
* Interrupt status register 0x40 + 6 * bank_size R
|
|
|
|
*
|
|
|
|
* - Registers with bit 0x80 set, the AI bit
|
|
|
|
* The bit is cleared and the registers fall into one of the
|
|
|
|
* categories above.
|
|
|
|
*/
|
|
|
|
|
|
|
|
static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg,
|
|
|
|
u32 checkbank)
|
|
|
|
{
|
|
|
|
int bank_shift = pca953x_bank_shift(chip);
|
|
|
|
int bank = (reg & REG_ADDR_MASK) >> bank_shift;
|
|
|
|
int offset = reg & (BIT(bank_shift) - 1);
|
|
|
|
|
|
|
|
/* Special PCAL extended register check. */
|
|
|
|
if (reg & REG_ADDR_EXT) {
|
|
|
|
if (!(chip->driver_data & PCA_PCAL))
|
|
|
|
return false;
|
|
|
|
bank += 8;
|
2013-01-22 14:10:23 -07:00
|
|
|
}
|
|
|
|
|
2018-12-11 18:39:58 -07:00
|
|
|
/* Register is not in the matching bank. */
|
|
|
|
if (!(BIT(bank) & checkbank))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
/* Register is not within allowed range of bank. */
|
|
|
|
if (offset >= NBANK(chip))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
2013-01-22 14:10:23 -07:00
|
|
|
}
|
|
|
|
|
2022-09-14 08:15:57 -07:00
|
|
|
/*
|
|
|
|
* Unfortunately, whilst the PCAL6534 chip (and compatibles) broadly follow the
|
|
|
|
* same register layout as the PCAL6524, the spacing of the registers has been
|
|
|
|
* fundamentally altered by compacting them and thus does not obey the same
|
|
|
|
* rules, including being able to use bit shifting to determine bank. These
|
|
|
|
* chips hence need special handling here.
|
|
|
|
*/
|
|
|
|
static bool pcal6534_check_register(struct pca953x_chip *chip, unsigned int reg,
|
|
|
|
u32 checkbank)
|
|
|
|
{
|
2022-12-10 15:06:00 -07:00
|
|
|
int bank_shift;
|
2022-09-14 08:15:57 -07:00
|
|
|
int bank;
|
|
|
|
int offset;
|
|
|
|
|
2022-12-10 15:05:59 -07:00
|
|
|
if (reg >= 0x54) {
|
2022-09-14 08:15:57 -07:00
|
|
|
/*
|
2022-12-10 15:05:59 -07:00
|
|
|
* Handle lack of reserved registers after output port
|
|
|
|
* configuration register to form a bank.
|
2022-09-14 08:15:57 -07:00
|
|
|
*/
|
2022-12-10 15:06:00 -07:00
|
|
|
reg -= 0x54;
|
|
|
|
bank_shift = 16;
|
2022-12-10 15:05:59 -07:00
|
|
|
} else if (reg >= 0x30) {
|
2022-09-14 08:15:57 -07:00
|
|
|
/*
|
2022-12-10 15:05:59 -07:00
|
|
|
* Reserved block between 14h and 2Fh does not align on
|
|
|
|
* expected bank boundaries like other devices.
|
2022-09-14 08:15:57 -07:00
|
|
|
*/
|
2022-12-10 15:06:00 -07:00
|
|
|
reg -= 0x30;
|
|
|
|
bank_shift = 8;
|
2022-09-14 08:15:57 -07:00
|
|
|
} else {
|
2022-12-10 15:06:00 -07:00
|
|
|
bank_shift = 0;
|
2022-09-14 08:15:57 -07:00
|
|
|
}
|
|
|
|
|
2022-12-10 15:06:00 -07:00
|
|
|
bank = bank_shift + reg / NBANK(chip);
|
|
|
|
offset = reg % NBANK(chip);
|
|
|
|
|
2022-09-14 08:15:57 -07:00
|
|
|
/* Register is not in the matching bank. */
|
|
|
|
if (!(BIT(bank) & checkbank))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
/* Register is not within allowed range of bank. */
|
|
|
|
if (offset >= NBANK(chip))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2018-12-11 18:39:58 -07:00
|
|
|
static bool pca953x_readable_register(struct device *dev, unsigned int reg)
|
2013-01-22 14:10:23 -07:00
|
|
|
{
|
2018-12-11 18:39:58 -07:00
|
|
|
struct pca953x_chip *chip = dev_get_drvdata(dev);
|
|
|
|
u32 bank;
|
2013-01-22 14:10:23 -07:00
|
|
|
|
2022-09-14 08:15:56 -07:00
|
|
|
if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
|
2018-12-11 18:39:58 -07:00
|
|
|
bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT |
|
|
|
|
PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG |
|
|
|
|
PCA957x_BANK_BUSHOLD;
|
2022-09-14 08:15:56 -07:00
|
|
|
} else {
|
|
|
|
bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT |
|
|
|
|
PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG;
|
2018-12-11 18:39:58 -07:00
|
|
|
}
|
2013-01-22 14:10:23 -07:00
|
|
|
|
2018-12-11 18:39:58 -07:00
|
|
|
if (chip->driver_data & PCA_PCAL) {
|
2019-02-07 09:28:59 -07:00
|
|
|
bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |
|
|
|
|
PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK |
|
2018-12-11 18:39:58 -07:00
|
|
|
PCAL9xxx_BANK_IRQ_STAT;
|
2013-01-22 14:10:23 -07:00
|
|
|
}
|
|
|
|
|
2022-09-14 08:15:57 -07:00
|
|
|
return chip->check_reg(chip, reg, bank);
|
2013-01-22 14:10:23 -07:00
|
|
|
}
|
|
|
|
|
2018-12-11 18:39:58 -07:00
|
|
|
static bool pca953x_writeable_register(struct device *dev, unsigned int reg)
|
2008-02-04 23:28:26 -07:00
|
|
|
{
|
2018-12-11 18:39:58 -07:00
|
|
|
struct pca953x_chip *chip = dev_get_drvdata(dev);
|
|
|
|
u32 bank;
|
2008-02-06 02:39:04 -07:00
|
|
|
|
2022-09-14 08:15:56 -07:00
|
|
|
if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
|
2018-12-11 18:39:58 -07:00
|
|
|
bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY |
|
|
|
|
PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD;
|
2022-09-14 08:15:56 -07:00
|
|
|
} else {
|
|
|
|
bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY |
|
|
|
|
PCA953x_BANK_CONFIG;
|
2018-12-11 18:39:58 -07:00
|
|
|
}
|
2016-05-31 12:03:43 -07:00
|
|
|
|
2018-12-11 18:39:58 -07:00
|
|
|
if (chip->driver_data & PCA_PCAL)
|
2019-02-07 09:28:59 -07:00
|
|
|
bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |
|
|
|
|
PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK;
|
2018-12-11 18:39:58 -07:00
|
|
|
|
2022-09-14 08:15:57 -07:00
|
|
|
return chip->check_reg(chip, reg, bank);
|
2016-09-09 02:17:35 -07:00
|
|
|
}
|
|
|
|
|
2018-12-11 18:39:58 -07:00
|
|
|
static bool pca953x_volatile_register(struct device *dev, unsigned int reg)
|
2016-09-09 02:17:35 -07:00
|
|
|
{
|
2018-12-11 18:39:58 -07:00
|
|
|
struct pca953x_chip *chip = dev_get_drvdata(dev);
|
|
|
|
u32 bank;
|
2016-09-09 02:17:35 -07:00
|
|
|
|
2022-09-14 08:15:56 -07:00
|
|
|
if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE)
|
2018-12-11 18:39:58 -07:00
|
|
|
bank = PCA957x_BANK_INPUT;
|
2022-09-14 08:15:56 -07:00
|
|
|
else
|
|
|
|
bank = PCA953x_BANK_INPUT;
|
2018-12-11 18:39:58 -07:00
|
|
|
|
|
|
|
if (chip->driver_data & PCA_PCAL)
|
|
|
|
bank |= PCAL9xxx_BANK_IRQ_STAT;
|
2016-09-09 02:17:35 -07:00
|
|
|
|
2022-09-14 08:15:57 -07:00
|
|
|
return chip->check_reg(chip, reg, bank);
|
2016-09-09 02:17:35 -07:00
|
|
|
}
|
2008-02-06 02:39:04 -07:00
|
|
|
|
2019-01-10 07:07:42 -07:00
|
|
|
static const struct regmap_config pca953x_i2c_regmap = {
|
2018-12-11 18:39:58 -07:00
|
|
|
.reg_bits = 8,
|
|
|
|
.val_bits = 8,
|
|
|
|
|
gpio: pca953x: only use single read/write for No AI mode
For the device use NO AI mode(not support auto address increment),
only use the single read/write when config the regmap.
We meet issue on PCA9557PW on i.MX8QXP/DXL evk board, this device
do not support AI mode, but when do the regmap sync, regmap will
sync 3 byte data to register 1, logically this means write first
data to register 1, write second data to register 2, write third data
to register 3. But this device do not support AI mode, finally, these
three data write only into register 1 one by one. the reault is the
value of register 1 alway equal to the latest data, here is the third
data, no operation happened on register 2 and register 3. This is
not what we expect.
Fixes: 49427232764d ("gpio: pca953x: Perform basic regmap conversion")
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
2022-07-18 01:31:41 -07:00
|
|
|
.use_single_read = true,
|
|
|
|
.use_single_write = true,
|
|
|
|
|
2018-12-11 18:39:58 -07:00
|
|
|
.readable_reg = pca953x_readable_register,
|
|
|
|
.writeable_reg = pca953x_writeable_register,
|
|
|
|
.volatile_reg = pca953x_volatile_register,
|
|
|
|
|
2020-04-07 08:42:45 -07:00
|
|
|
.disable_locking = true,
|
2023-09-29 05:24:13 -07:00
|
|
|
.cache_type = REGCACHE_MAPLE,
|
2020-04-20 10:27:51 -07:00
|
|
|
.max_register = 0x7f,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct regmap_config pca953x_ai_i2c_regmap = {
|
|
|
|
.reg_bits = 8,
|
|
|
|
.val_bits = 8,
|
|
|
|
|
|
|
|
.read_flag_mask = REG_ADDR_AI,
|
|
|
|
.write_flag_mask = REG_ADDR_AI,
|
|
|
|
|
|
|
|
.readable_reg = pca953x_readable_register,
|
|
|
|
.writeable_reg = pca953x_writeable_register,
|
|
|
|
.volatile_reg = pca953x_volatile_register,
|
|
|
|
|
2020-06-05 06:40:36 -07:00
|
|
|
.disable_locking = true,
|
2023-09-29 05:24:13 -07:00
|
|
|
.cache_type = REGCACHE_MAPLE,
|
2020-04-20 10:27:51 -07:00
|
|
|
.max_register = 0x7f,
|
2018-12-11 18:39:58 -07:00
|
|
|
};
|
|
|
|
|
2020-04-20 10:27:52 -07:00
|
|
|
static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off)
|
2016-09-09 02:17:35 -07:00
|
|
|
{
|
2018-12-11 18:39:57 -07:00
|
|
|
int bank_shift = pca953x_bank_shift(chip);
|
2018-05-16 21:59:49 -07:00
|
|
|
int addr = (reg & PCAL_GPIO_MASK) << bank_shift;
|
|
|
|
int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1;
|
2018-12-11 18:39:57 -07:00
|
|
|
u8 regaddr = pinctrl | addr | (off / BANK_SZ);
|
|
|
|
|
|
|
|
return regaddr;
|
2016-09-09 02:17:35 -07:00
|
|
|
}
|
|
|
|
|
2022-09-14 08:15:57 -07:00
|
|
|
/*
|
|
|
|
* The PCAL6534 and compatible chips have altered bank alignment that doesn't
|
|
|
|
* fit within the bit shifting scheme used for other devices.
|
|
|
|
*/
|
|
|
|
static u8 pcal6534_recalc_addr(struct pca953x_chip *chip, int reg, int off)
|
|
|
|
{
|
|
|
|
int addr;
|
|
|
|
int pinctrl;
|
|
|
|
|
|
|
|
addr = (reg & PCAL_GPIO_MASK) * NBANK(chip);
|
|
|
|
|
|
|
|
switch (reg) {
|
|
|
|
case PCAL953X_OUT_STRENGTH:
|
|
|
|
case PCAL953X_IN_LATCH:
|
|
|
|
case PCAL953X_PULL_EN:
|
|
|
|
case PCAL953X_PULL_SEL:
|
|
|
|
case PCAL953X_INT_MASK:
|
|
|
|
case PCAL953X_INT_STAT:
|
|
|
|
pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x20;
|
|
|
|
break;
|
|
|
|
case PCAL6524_INT_EDGE:
|
|
|
|
case PCAL6524_INT_CLR:
|
|
|
|
case PCAL6524_IN_STATUS:
|
|
|
|
case PCAL6524_OUT_INDCONF:
|
|
|
|
case PCAL6524_DEBOUNCE:
|
|
|
|
pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x1c;
|
|
|
|
break;
|
2022-12-10 15:05:58 -07:00
|
|
|
default:
|
|
|
|
pinctrl = 0;
|
|
|
|
break;
|
2022-09-14 08:15:57 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
return pinctrl + addr + (off / BANK_SZ);
|
|
|
|
}
|
|
|
|
|
2019-12-04 17:53:37 -07:00
|
|
|
static int pca953x_write_regs(struct pca953x_chip *chip, int reg, unsigned long *val)
|
2016-09-09 02:17:35 -07:00
|
|
|
{
|
2022-09-14 08:15:57 -07:00
|
|
|
u8 regaddr = chip->recalc_addr(chip, reg, 0);
|
2019-12-04 17:53:37 -07:00
|
|
|
u8 value[MAX_BANK];
|
|
|
|
int i, ret;
|
|
|
|
|
|
|
|
for (i = 0; i < NBANK(chip); i++)
|
|
|
|
value[i] = bitmap_get_value8(val, i * BANK_SZ);
|
2016-09-09 02:17:35 -07:00
|
|
|
|
2019-12-04 17:53:37 -07:00
|
|
|
ret = regmap_bulk_write(chip->regmap, regaddr, value, NBANK(chip));
|
2008-02-06 02:39:04 -07:00
|
|
|
if (ret < 0) {
|
2024-08-21 04:42:02 -07:00
|
|
|
dev_err(&chip->client->dev, "failed writing register: %d\n", ret);
|
2009-01-06 15:42:27 -07:00
|
|
|
return ret;
|
2008-02-06 02:39:04 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
2008-02-04 23:28:26 -07:00
|
|
|
}
|
|
|
|
|
2019-12-04 17:53:37 -07:00
|
|
|
static int pca953x_read_regs(struct pca953x_chip *chip, int reg, unsigned long *val)
|
2016-09-09 02:17:36 -07:00
|
|
|
{
|
2022-09-14 08:15:57 -07:00
|
|
|
u8 regaddr = chip->recalc_addr(chip, reg, 0);
|
2019-12-04 17:53:37 -07:00
|
|
|
u8 value[MAX_BANK];
|
|
|
|
int i, ret;
|
2016-09-09 02:17:36 -07:00
|
|
|
|
2019-12-04 17:53:37 -07:00
|
|
|
ret = regmap_bulk_read(chip->regmap, regaddr, value, NBANK(chip));
|
2008-02-04 23:28:26 -07:00
|
|
|
if (ret < 0) {
|
2024-08-21 04:42:02 -07:00
|
|
|
dev_err(&chip->client->dev, "failed reading register: %d\n", ret);
|
2009-01-06 15:42:27 -07:00
|
|
|
return ret;
|
2008-02-04 23:28:26 -07:00
|
|
|
}
|
|
|
|
|
2019-12-04 17:53:37 -07:00
|
|
|
for (i = 0; i < NBANK(chip); i++)
|
|
|
|
bitmap_set_value8(val, value[i], i * BANK_SZ);
|
|
|
|
|
2008-02-04 23:28:26 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-02-06 02:39:03 -07:00
|
|
|
static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
|
2008-02-04 23:28:26 -07:00
|
|
|
{
|
2015-12-07 03:20:54 -07:00
|
|
|
struct pca953x_chip *chip = gpiochip_get_data(gc);
|
2022-09-14 08:15:57 -07:00
|
|
|
u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off);
|
2018-12-11 18:39:59 -07:00
|
|
|
u8 bit = BIT(off % BANK_SZ);
|
2008-02-04 23:28:26 -07:00
|
|
|
|
2023-09-01 06:40:36 -07:00
|
|
|
guard(mutex)(&chip->i2c_lock);
|
|
|
|
|
|
|
|
return regmap_write_bits(chip->regmap, dirreg, bit, bit);
|
2008-02-04 23:28:26 -07:00
|
|
|
}
|
|
|
|
|
2008-02-06 02:39:03 -07:00
|
|
|
static int pca953x_gpio_direction_output(struct gpio_chip *gc,
|
2008-02-04 23:28:26 -07:00
|
|
|
unsigned off, int val)
|
|
|
|
{
|
2015-12-07 03:20:54 -07:00
|
|
|
struct pca953x_chip *chip = gpiochip_get_data(gc);
|
2022-09-14 08:15:57 -07:00
|
|
|
u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off);
|
|
|
|
u8 outreg = chip->recalc_addr(chip, chip->regs->output, off);
|
2018-12-11 18:39:59 -07:00
|
|
|
u8 bit = BIT(off % BANK_SZ);
|
2016-09-09 02:17:34 -07:00
|
|
|
int ret;
|
2008-02-04 23:28:26 -07:00
|
|
|
|
2023-09-01 06:40:36 -07:00
|
|
|
guard(mutex)(&chip->i2c_lock);
|
|
|
|
|
2008-02-04 23:28:26 -07:00
|
|
|
/* set output level */
|
2018-12-11 18:40:00 -07:00
|
|
|
ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
|
2008-02-04 23:28:26 -07:00
|
|
|
if (ret)
|
2023-09-01 06:40:36 -07:00
|
|
|
return ret;
|
2008-02-04 23:28:26 -07:00
|
|
|
|
|
|
|
/* then direction */
|
2023-09-01 06:40:36 -07:00
|
|
|
return regmap_write_bits(chip->regmap, dirreg, bit, 0);
|
2008-02-04 23:28:26 -07:00
|
|
|
}
|
|
|
|
|
2008-02-06 02:39:03 -07:00
|
|
|
static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
|
2008-02-04 23:28:26 -07:00
|
|
|
{
|
2015-12-07 03:20:54 -07:00
|
|
|
struct pca953x_chip *chip = gpiochip_get_data(gc);
|
2022-09-14 08:15:57 -07:00
|
|
|
u8 inreg = chip->recalc_addr(chip, chip->regs->input, off);
|
2018-12-11 18:40:01 -07:00
|
|
|
u8 bit = BIT(off % BANK_SZ);
|
2012-05-09 00:46:17 -07:00
|
|
|
u32 reg_val;
|
2016-09-09 02:17:34 -07:00
|
|
|
int ret;
|
2008-02-04 23:28:26 -07:00
|
|
|
|
2023-09-01 06:40:36 -07:00
|
|
|
scoped_guard(mutex, &chip->i2c_lock)
|
|
|
|
ret = regmap_read(chip->regmap, inreg, ®_val);
|
2021-09-23 10:22:16 -07:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2008-02-04 23:28:26 -07:00
|
|
|
|
2018-12-11 18:40:01 -07:00
|
|
|
return !!(reg_val & bit);
|
2008-02-04 23:28:26 -07:00
|
|
|
}
|
|
|
|
|
2008-02-06 02:39:03 -07:00
|
|
|
static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
|
2008-02-04 23:28:26 -07:00
|
|
|
{
|
2015-12-07 03:20:54 -07:00
|
|
|
struct pca953x_chip *chip = gpiochip_get_data(gc);
|
2022-09-14 08:15:57 -07:00
|
|
|
u8 outreg = chip->recalc_addr(chip, chip->regs->output, off);
|
2018-12-11 18:40:00 -07:00
|
|
|
u8 bit = BIT(off % BANK_SZ);
|
2008-02-04 23:28:26 -07:00
|
|
|
|
2023-09-01 06:40:36 -07:00
|
|
|
guard(mutex)(&chip->i2c_lock);
|
|
|
|
|
2018-12-11 18:40:00 -07:00
|
|
|
regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
|
2008-02-04 23:28:26 -07:00
|
|
|
}
|
|
|
|
|
2017-03-22 07:11:11 -07:00
|
|
|
static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off)
|
|
|
|
{
|
|
|
|
struct pca953x_chip *chip = gpiochip_get_data(gc);
|
2022-09-14 08:15:57 -07:00
|
|
|
u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off);
|
2018-12-11 18:39:59 -07:00
|
|
|
u8 bit = BIT(off % BANK_SZ);
|
2017-03-22 07:11:11 -07:00
|
|
|
u32 reg_val;
|
|
|
|
int ret;
|
|
|
|
|
2023-09-01 06:40:36 -07:00
|
|
|
scoped_guard(mutex, &chip->i2c_lock)
|
|
|
|
ret = regmap_read(chip->regmap, dirreg, ®_val);
|
2017-03-22 07:11:11 -07:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2019-11-06 01:54:12 -07:00
|
|
|
if (reg_val & bit)
|
|
|
|
return GPIO_LINE_DIRECTION_IN;
|
|
|
|
|
|
|
|
return GPIO_LINE_DIRECTION_OUT;
|
2017-03-22 07:11:11 -07:00
|
|
|
}
|
|
|
|
|
2020-04-14 08:28:42 -07:00
|
|
|
static int pca953x_gpio_get_multiple(struct gpio_chip *gc,
|
2020-04-20 10:27:50 -07:00
|
|
|
unsigned long *mask, unsigned long *bits)
|
2020-04-14 08:28:42 -07:00
|
|
|
{
|
|
|
|
struct pca953x_chip *chip = gpiochip_get_data(gc);
|
2020-04-20 10:27:50 -07:00
|
|
|
DECLARE_BITMAP(reg_val, MAX_LINE);
|
|
|
|
int ret;
|
|
|
|
|
2023-09-01 06:40:36 -07:00
|
|
|
scoped_guard(mutex, &chip->i2c_lock)
|
|
|
|
ret = pca953x_read_regs(chip, chip->regs->input, reg_val);
|
2020-04-20 10:27:50 -07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
bitmap_replace(bits, bits, reg_val, mask, gc->ngpio);
|
|
|
|
return 0;
|
2020-04-14 08:28:42 -07:00
|
|
|
}
|
|
|
|
|
2015-12-04 00:52:30 -07:00
|
|
|
static void pca953x_gpio_set_multiple(struct gpio_chip *gc,
|
2016-09-09 02:17:38 -07:00
|
|
|
unsigned long *mask, unsigned long *bits)
|
2015-12-04 00:52:30 -07:00
|
|
|
{
|
2015-12-07 03:20:54 -07:00
|
|
|
struct pca953x_chip *chip = gpiochip_get_data(gc);
|
2019-12-04 17:53:37 -07:00
|
|
|
DECLARE_BITMAP(reg_val, MAX_LINE);
|
2016-09-09 02:17:34 -07:00
|
|
|
int ret;
|
2016-09-09 02:17:38 -07:00
|
|
|
|
2023-09-01 06:40:36 -07:00
|
|
|
guard(mutex)(&chip->i2c_lock);
|
|
|
|
|
2018-12-11 18:40:00 -07:00
|
|
|
ret = pca953x_read_regs(chip, chip->regs->output, reg_val);
|
|
|
|
if (ret)
|
2023-09-01 06:40:36 -07:00
|
|
|
return;
|
2018-12-11 18:40:00 -07:00
|
|
|
|
2019-12-04 17:53:37 -07:00
|
|
|
bitmap_replace(reg_val, reg_val, bits, mask, gc->ngpio);
|
2016-09-09 02:17:38 -07:00
|
|
|
|
2018-12-11 18:40:00 -07:00
|
|
|
pca953x_write_regs(chip, chip->regs->output, reg_val);
|
2015-12-04 00:52:30 -07:00
|
|
|
}
|
|
|
|
|
2019-02-07 09:28:59 -07:00
|
|
|
static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip,
|
|
|
|
unsigned int offset,
|
|
|
|
unsigned long config)
|
|
|
|
{
|
2022-09-14 08:15:55 -07:00
|
|
|
enum pin_config_param param = pinconf_to_config_param(config);
|
2022-09-14 08:15:57 -07:00
|
|
|
u8 pull_en_reg = chip->recalc_addr(chip, PCAL953X_PULL_EN, offset);
|
|
|
|
u8 pull_sel_reg = chip->recalc_addr(chip, PCAL953X_PULL_SEL, offset);
|
2019-02-07 09:28:59 -07:00
|
|
|
u8 bit = BIT(offset % BANK_SZ);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* pull-up/pull-down configuration requires PCAL extended
|
|
|
|
* registers
|
|
|
|
*/
|
|
|
|
if (!(chip->driver_data & PCA_PCAL))
|
|
|
|
return -ENOTSUPP;
|
|
|
|
|
2023-09-01 06:40:36 -07:00
|
|
|
guard(mutex)(&chip->i2c_lock);
|
2019-02-07 09:28:59 -07:00
|
|
|
|
|
|
|
/* Configure pull-up/pull-down */
|
2022-09-14 08:15:55 -07:00
|
|
|
if (param == PIN_CONFIG_BIAS_PULL_UP)
|
2019-02-07 09:28:59 -07:00
|
|
|
ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, bit);
|
2022-09-14 08:15:55 -07:00
|
|
|
else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
|
2019-02-07 09:28:59 -07:00
|
|
|
ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, 0);
|
2021-09-23 15:46:40 -07:00
|
|
|
else
|
|
|
|
ret = 0;
|
2019-02-07 09:28:59 -07:00
|
|
|
if (ret)
|
2023-09-01 06:40:36 -07:00
|
|
|
return ret;
|
2019-02-07 09:28:59 -07:00
|
|
|
|
2021-09-23 15:46:40 -07:00
|
|
|
/* Disable/Enable pull-up/pull-down */
|
2022-09-14 08:15:55 -07:00
|
|
|
if (param == PIN_CONFIG_BIAS_DISABLE)
|
2023-09-01 06:40:36 -07:00
|
|
|
return regmap_write_bits(chip->regmap, pull_en_reg, bit, 0);
|
2021-09-23 15:46:40 -07:00
|
|
|
else
|
2023-09-01 06:40:36 -07:00
|
|
|
return regmap_write_bits(chip->regmap, pull_en_reg, bit, bit);
|
2019-02-07 09:28:59 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
|
|
|
|
unsigned long config)
|
|
|
|
{
|
|
|
|
struct pca953x_chip *chip = gpiochip_get_data(gc);
|
|
|
|
|
2020-04-11 18:33:52 -07:00
|
|
|
switch (pinconf_to_config_param(config)) {
|
2019-02-07 09:28:59 -07:00
|
|
|
case PIN_CONFIG_BIAS_PULL_UP:
|
2021-09-23 15:46:40 -07:00
|
|
|
case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
|
2019-02-07 09:28:59 -07:00
|
|
|
case PIN_CONFIG_BIAS_PULL_DOWN:
|
2021-09-23 15:46:40 -07:00
|
|
|
case PIN_CONFIG_BIAS_DISABLE:
|
2019-02-07 09:28:59 -07:00
|
|
|
return pca953x_gpio_set_pull_up_down(chip, offset, config);
|
|
|
|
default:
|
|
|
|
return -ENOTSUPP;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-02-06 02:39:04 -07:00
|
|
|
static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
|
2008-02-04 23:28:26 -07:00
|
|
|
{
|
2023-09-01 06:40:38 -07:00
|
|
|
struct gpio_chip *gc = &chip->gpio_chip;
|
2008-02-04 23:28:26 -07:00
|
|
|
|
2008-02-06 02:39:03 -07:00
|
|
|
gc->direction_input = pca953x_gpio_direction_input;
|
|
|
|
gc->direction_output = pca953x_gpio_direction_output;
|
|
|
|
gc->get = pca953x_gpio_get_value;
|
|
|
|
gc->set = pca953x_gpio_set_value;
|
2017-03-22 07:11:11 -07:00
|
|
|
gc->get_direction = pca953x_gpio_get_direction;
|
2020-04-14 08:28:42 -07:00
|
|
|
gc->get_multiple = pca953x_gpio_get_multiple;
|
2015-12-04 00:52:30 -07:00
|
|
|
gc->set_multiple = pca953x_gpio_set_multiple;
|
2019-02-07 09:28:59 -07:00
|
|
|
gc->set_config = pca953x_gpio_set_config;
|
2013-12-04 06:42:46 -07:00
|
|
|
gc->can_sleep = true;
|
2008-02-04 23:28:26 -07:00
|
|
|
|
|
|
|
gc->base = chip->gpio_start;
|
2008-02-06 02:39:04 -07:00
|
|
|
gc->ngpio = gpios;
|
2018-12-02 01:43:21 -07:00
|
|
|
gc->label = dev_name(&chip->client->dev);
|
2015-11-04 01:56:26 -07:00
|
|
|
gc->parent = &chip->client->dev;
|
2008-04-28 02:14:45 -07:00
|
|
|
gc->owner = THIS_MODULE;
|
2008-02-04 23:28:26 -07:00
|
|
|
}
|
|
|
|
|
2010-03-05 14:44:36 -07:00
|
|
|
#ifdef CONFIG_GPIO_PCA953X_IRQ
|
2011-01-12 18:00:15 -07:00
|
|
|
static void pca953x_irq_mask(struct irq_data *d)
|
2010-03-05 14:44:36 -07:00
|
|
|
{
|
2014-05-09 04:27:57 -07:00
|
|
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
2015-12-07 03:20:54 -07:00
|
|
|
struct pca953x_chip *chip = gpiochip_get_data(gc);
|
2019-12-09 05:35:44 -07:00
|
|
|
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
2010-03-05 14:44:36 -07:00
|
|
|
|
2019-12-09 05:35:44 -07:00
|
|
|
clear_bit(hwirq, chip->irq_mask);
|
2022-05-20 03:21:54 -07:00
|
|
|
gpiochip_disable_irq(gc, hwirq);
|
2010-03-05 14:44:36 -07:00
|
|
|
}
|
|
|
|
|
2011-01-12 18:00:15 -07:00
|
|
|
static void pca953x_irq_unmask(struct irq_data *d)
|
2010-03-05 14:44:36 -07:00
|
|
|
{
|
2014-05-09 04:27:57 -07:00
|
|
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
2015-12-07 03:20:54 -07:00
|
|
|
struct pca953x_chip *chip = gpiochip_get_data(gc);
|
2019-12-09 05:35:44 -07:00
|
|
|
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
2010-03-05 14:44:36 -07:00
|
|
|
|
2022-05-20 03:21:54 -07:00
|
|
|
gpiochip_enable_irq(gc, hwirq);
|
2019-12-09 05:35:44 -07:00
|
|
|
set_bit(hwirq, chip->irq_mask);
|
2010-03-05 14:44:36 -07:00
|
|
|
}
|
|
|
|
|
2019-02-13 06:15:03 -07:00
|
|
|
static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on)
|
|
|
|
{
|
|
|
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
|
|
|
struct pca953x_chip *chip = gpiochip_get_data(gc);
|
|
|
|
|
2019-03-20 03:39:27 -07:00
|
|
|
if (on)
|
|
|
|
atomic_inc(&chip->wakeup_path);
|
|
|
|
else
|
|
|
|
atomic_dec(&chip->wakeup_path);
|
|
|
|
|
2019-02-13 06:15:03 -07:00
|
|
|
return irq_set_irq_wake(chip->client->irq, on);
|
|
|
|
}
|
|
|
|
|
2011-01-12 18:00:15 -07:00
|
|
|
static void pca953x_irq_bus_lock(struct irq_data *d)
|
2010-03-05 14:44:36 -07:00
|
|
|
{
|
2014-05-09 04:27:57 -07:00
|
|
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
2015-12-07 03:20:54 -07:00
|
|
|
struct pca953x_chip *chip = gpiochip_get_data(gc);
|
2010-03-05 14:44:36 -07:00
|
|
|
|
|
|
|
mutex_lock(&chip->irq_lock);
|
|
|
|
}
|
|
|
|
|
2011-01-12 18:00:15 -07:00
|
|
|
static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
|
2010-03-05 14:44:36 -07:00
|
|
|
{
|
2014-05-09 04:27:57 -07:00
|
|
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
2015-12-07 03:20:54 -07:00
|
|
|
struct pca953x_chip *chip = gpiochip_get_data(gc);
|
2019-12-04 17:53:37 -07:00
|
|
|
DECLARE_BITMAP(irq_mask, MAX_LINE);
|
|
|
|
DECLARE_BITMAP(reg_direction, MAX_LINE);
|
|
|
|
int level;
|
2018-12-11 18:39:59 -07:00
|
|
|
|
2016-04-06 21:56:32 -07:00
|
|
|
if (chip->driver_data & PCA_PCAL) {
|
gpio: pca953x: fix pca953x_irq_bus_sync_unlock race
Ensure that `i2c_lock' is held when setting interrupt latch and mask in
pca953x_irq_bus_sync_unlock() in order to avoid races.
The other (non-probe) call site pca953x_gpio_set_multiple() ensures the
lock is held before calling pca953x_write_regs().
The problem occurred when a request raced against irq_bus_sync_unlock()
approximately once per thousand reboots on an i.MX8MP based system.
* Normal case
0-0022: write register AI|3a {03,02,00,00,01} Input latch P0
0-0022: write register AI|49 {fc,fd,ff,ff,fe} Interrupt mask P0
0-0022: write register AI|08 {ff,00,00,00,00} Output P3
0-0022: write register AI|12 {fc,00,00,00,00} Config P3
* Race case
0-0022: write register AI|08 {ff,00,00,00,00} Output P3
0-0022: write register AI|08 {03,02,00,00,01} *** Wrong register ***
0-0022: write register AI|12 {fc,00,00,00,00} Config P3
0-0022: write register AI|49 {fc,fd,ff,ff,fe} Interrupt mask P0
Signed-off-by: Ian Ray <ian.ray@gehealthcare.com>
Link: https://lore.kernel.org/r/20240620042915.2173-1-ian.ray@gehealthcare.com
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2024-06-19 21:29:15 -07:00
|
|
|
guard(mutex)(&chip->i2c_lock);
|
|
|
|
|
2016-04-06 21:56:32 -07:00
|
|
|
/* Enable latch on interrupt-enabled inputs */
|
|
|
|
pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask);
|
|
|
|
|
2019-12-04 17:53:37 -07:00
|
|
|
bitmap_complement(irq_mask, chip->irq_mask, gc->ngpio);
|
2016-04-06 21:56:32 -07:00
|
|
|
|
|
|
|
/* Unmask enabled interrupts */
|
2019-12-04 17:53:37 -07:00
|
|
|
pca953x_write_regs(chip, PCAL953X_INT_MASK, irq_mask);
|
2016-04-06 21:56:32 -07:00
|
|
|
}
|
2010-04-27 13:13:07 -07:00
|
|
|
|
2020-06-05 06:40:35 -07:00
|
|
|
/* Switch direction to input if needed */
|
|
|
|
pca953x_read_regs(chip, chip->regs->direction, reg_direction);
|
|
|
|
|
2019-12-04 17:53:37 -07:00
|
|
|
bitmap_or(irq_mask, chip->irq_trig_fall, chip->irq_trig_raise, gc->ngpio);
|
2020-06-05 06:40:35 -07:00
|
|
|
bitmap_complement(reg_direction, reg_direction, gc->ngpio);
|
2019-12-04 17:53:37 -07:00
|
|
|
bitmap_and(irq_mask, irq_mask, reg_direction, gc->ngpio);
|
|
|
|
|
2010-04-27 13:13:07 -07:00
|
|
|
/* Look for any newly setup interrupt */
|
2019-12-04 17:53:37 -07:00
|
|
|
for_each_set_bit(level, irq_mask, gc->ngpio)
|
|
|
|
pca953x_gpio_direction_input(&chip->gpio_chip, level);
|
2010-03-05 14:44:36 -07:00
|
|
|
|
|
|
|
mutex_unlock(&chip->irq_lock);
|
|
|
|
}
|
|
|
|
|
2011-01-12 18:00:15 -07:00
|
|
|
static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
|
2010-03-05 14:44:36 -07:00
|
|
|
{
|
2014-05-09 04:27:57 -07:00
|
|
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
2015-12-07 03:20:54 -07:00
|
|
|
struct pca953x_chip *chip = gpiochip_get_data(gc);
|
2023-09-01 06:40:37 -07:00
|
|
|
struct device *dev = &chip->client->dev;
|
2019-12-09 05:35:44 -07:00
|
|
|
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
2010-03-05 14:44:36 -07:00
|
|
|
|
|
|
|
if (!(type & IRQ_TYPE_EDGE_BOTH)) {
|
2023-09-01 06:40:37 -07:00
|
|
|
dev_err(dev, "irq %d: unsupported type %d\n", d->irq, type);
|
2010-03-05 14:44:36 -07:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2019-12-09 05:35:44 -07:00
|
|
|
assign_bit(hwirq, chip->irq_trig_fall, type & IRQ_TYPE_EDGE_FALLING);
|
|
|
|
assign_bit(hwirq, chip->irq_trig_raise, type & IRQ_TYPE_EDGE_RISING);
|
2010-03-05 14:44:36 -07:00
|
|
|
|
2010-04-27 13:13:07 -07:00
|
|
|
return 0;
|
2010-03-05 14:44:36 -07:00
|
|
|
}
|
|
|
|
|
2018-05-04 09:53:18 -07:00
|
|
|
static void pca953x_irq_shutdown(struct irq_data *d)
|
|
|
|
{
|
2019-02-28 08:46:36 -07:00
|
|
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
|
|
|
struct pca953x_chip *chip = gpiochip_get_data(gc);
|
2019-12-09 05:35:44 -07:00
|
|
|
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
2018-05-04 09:53:18 -07:00
|
|
|
|
2019-12-09 05:35:44 -07:00
|
|
|
clear_bit(hwirq, chip->irq_trig_raise);
|
|
|
|
clear_bit(hwirq, chip->irq_trig_fall);
|
2018-05-04 09:53:18 -07:00
|
|
|
}
|
|
|
|
|
2022-05-20 03:21:54 -07:00
|
|
|
static void pca953x_irq_print_chip(struct irq_data *data, struct seq_file *p)
|
|
|
|
{
|
|
|
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
|
|
|
|
|
|
|
|
seq_printf(p, dev_name(gc->parent));
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct irq_chip pca953x_irq_chip = {
|
|
|
|
.irq_mask = pca953x_irq_mask,
|
|
|
|
.irq_unmask = pca953x_irq_unmask,
|
|
|
|
.irq_set_wake = pca953x_irq_set_wake,
|
|
|
|
.irq_bus_lock = pca953x_irq_bus_lock,
|
|
|
|
.irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
|
|
|
|
.irq_set_type = pca953x_irq_set_type,
|
|
|
|
.irq_shutdown = pca953x_irq_shutdown,
|
|
|
|
.irq_print_chip = pca953x_irq_print_chip,
|
|
|
|
.flags = IRQCHIP_IMMUTABLE,
|
|
|
|
GPIOCHIP_IRQ_RESOURCE_HELPERS,
|
|
|
|
};
|
|
|
|
|
2019-12-04 17:53:37 -07:00
|
|
|
static bool pca953x_irq_pending(struct pca953x_chip *chip, unsigned long *pending)
|
2010-03-05 14:44:36 -07:00
|
|
|
{
|
2019-12-04 17:53:37 -07:00
|
|
|
struct gpio_chip *gc = &chip->gpio_chip;
|
|
|
|
DECLARE_BITMAP(reg_direction, MAX_LINE);
|
|
|
|
DECLARE_BITMAP(old_stat, MAX_LINE);
|
|
|
|
DECLARE_BITMAP(cur_stat, MAX_LINE);
|
|
|
|
DECLARE_BITMAP(new_stat, MAX_LINE);
|
|
|
|
DECLARE_BITMAP(trigger, MAX_LINE);
|
|
|
|
int ret;
|
2011-04-18 07:12:46 -07:00
|
|
|
|
2016-04-06 21:56:32 -07:00
|
|
|
if (chip->driver_data & PCA_PCAL) {
|
|
|
|
/* Read the current interrupt status from the device */
|
|
|
|
ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger);
|
|
|
|
if (ret)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
/* Check latched inputs and clear interrupt status */
|
2019-12-04 17:53:33 -07:00
|
|
|
ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
|
2016-04-06 21:56:32 -07:00
|
|
|
if (ret)
|
|
|
|
return false;
|
|
|
|
|
2019-12-04 17:53:37 -07:00
|
|
|
/* Apply filter for rising/falling edge selection */
|
|
|
|
bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise, cur_stat, gc->ngpio);
|
|
|
|
|
|
|
|
bitmap_and(pending, new_stat, trigger, gc->ngpio);
|
2016-04-06 21:56:32 -07:00
|
|
|
|
2019-12-04 17:53:37 -07:00
|
|
|
return !bitmap_empty(pending, gc->ngpio);
|
2016-04-06 21:56:32 -07:00
|
|
|
}
|
|
|
|
|
2016-09-09 02:17:34 -07:00
|
|
|
ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
|
2010-03-05 14:44:36 -07:00
|
|
|
if (ret)
|
2015-05-21 17:35:12 -07:00
|
|
|
return false;
|
2010-03-05 14:44:36 -07:00
|
|
|
|
|
|
|
/* Remove output pins from the equation */
|
2019-08-26 23:46:29 -07:00
|
|
|
pca953x_read_regs(chip, chip->regs->direction, reg_direction);
|
2010-03-05 14:44:36 -07:00
|
|
|
|
2019-12-04 17:53:37 -07:00
|
|
|
bitmap_copy(old_stat, chip->irq_stat, gc->ngpio);
|
2010-03-05 14:44:36 -07:00
|
|
|
|
2019-12-04 17:53:37 -07:00
|
|
|
bitmap_and(new_stat, cur_stat, reg_direction, gc->ngpio);
|
|
|
|
bitmap_xor(cur_stat, new_stat, old_stat, gc->ngpio);
|
|
|
|
bitmap_and(trigger, cur_stat, chip->irq_mask, gc->ngpio);
|
2013-01-22 14:10:23 -07:00
|
|
|
|
2022-05-06 01:06:30 -07:00
|
|
|
bitmap_copy(chip->irq_stat, new_stat, gc->ngpio);
|
|
|
|
|
2019-12-04 17:53:37 -07:00
|
|
|
if (bitmap_empty(trigger, gc->ngpio))
|
2015-05-21 17:35:12 -07:00
|
|
|
return false;
|
2010-03-05 14:44:36 -07:00
|
|
|
|
2019-12-04 17:53:37 -07:00
|
|
|
bitmap_and(cur_stat, chip->irq_trig_fall, old_stat, gc->ngpio);
|
|
|
|
bitmap_and(old_stat, chip->irq_trig_raise, new_stat, gc->ngpio);
|
|
|
|
bitmap_or(new_stat, old_stat, cur_stat, gc->ngpio);
|
|
|
|
bitmap_and(pending, new_stat, trigger, gc->ngpio);
|
2010-03-05 14:44:36 -07:00
|
|
|
|
2019-12-04 17:53:37 -07:00
|
|
|
return !bitmap_empty(pending, gc->ngpio);
|
2010-03-05 14:44:36 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t pca953x_irq_handler(int irq, void *devid)
|
|
|
|
{
|
|
|
|
struct pca953x_chip *chip = devid;
|
2019-12-04 17:53:37 -07:00
|
|
|
struct gpio_chip *gc = &chip->gpio_chip;
|
2020-09-30 07:20:12 -07:00
|
|
|
DECLARE_BITMAP(pending, MAX_LINE);
|
2019-12-04 17:53:37 -07:00
|
|
|
int level;
|
2020-06-05 06:40:33 -07:00
|
|
|
bool ret;
|
2010-03-05 14:44:36 -07:00
|
|
|
|
2020-09-30 07:20:12 -07:00
|
|
|
bitmap_zero(pending, MAX_LINE);
|
|
|
|
|
2023-09-01 06:40:36 -07:00
|
|
|
scoped_guard(mutex, &chip->i2c_lock)
|
|
|
|
ret = pca953x_irq_pending(chip, pending);
|
2020-10-05 07:02:17 -07:00
|
|
|
if (ret) {
|
|
|
|
ret = 0;
|
|
|
|
|
|
|
|
for_each_set_bit(level, pending, gc->ngpio) {
|
|
|
|
int nested_irq = irq_find_mapping(gc->irq.domain, level);
|
|
|
|
|
|
|
|
if (unlikely(nested_irq <= 0)) {
|
|
|
|
dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
handle_nested_irq(nested_irq);
|
|
|
|
ret = 1;
|
|
|
|
}
|
|
|
|
}
|
2010-03-05 14:44:36 -07:00
|
|
|
|
2020-06-05 06:40:33 -07:00
|
|
|
return IRQ_RETVAL(ret);
|
2010-03-05 14:44:36 -07:00
|
|
|
}
|
|
|
|
|
2019-12-04 17:53:40 -07:00
|
|
|
static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base)
|
2010-03-05 14:44:36 -07:00
|
|
|
{
|
|
|
|
struct i2c_client *client = chip->client;
|
2023-09-01 06:40:34 -07:00
|
|
|
struct device *dev = &client->dev;
|
2019-12-04 17:53:37 -07:00
|
|
|
DECLARE_BITMAP(reg_direction, MAX_LINE);
|
|
|
|
DECLARE_BITMAP(irq_stat, MAX_LINE);
|
2023-09-01 06:40:38 -07:00
|
|
|
struct gpio_chip *gc = &chip->gpio_chip;
|
2020-07-17 07:40:40 -07:00
|
|
|
struct gpio_irq_chip *girq;
|
2019-12-04 17:53:37 -07:00
|
|
|
int ret;
|
2010-03-05 14:44:36 -07:00
|
|
|
|
2020-06-05 06:40:34 -07:00
|
|
|
if (dmi_first_match(pca953x_dmi_acpi_irq_info)) {
|
2023-09-01 06:40:37 -07:00
|
|
|
ret = pca953x_acpi_get_irq(dev);
|
2020-06-05 06:40:34 -07:00
|
|
|
if (ret > 0)
|
|
|
|
client->irq = ret;
|
|
|
|
}
|
|
|
|
|
2019-01-16 02:31:57 -07:00
|
|
|
if (!client->irq)
|
|
|
|
return 0;
|
2010-03-05 14:44:36 -07:00
|
|
|
|
2019-01-16 02:31:57 -07:00
|
|
|
if (irq_base == -1)
|
|
|
|
return 0;
|
2010-03-05 14:44:36 -07:00
|
|
|
|
2019-01-16 02:31:57 -07:00
|
|
|
if (!(chip->driver_data & PCA_INT))
|
|
|
|
return 0;
|
2015-07-07 07:34:49 -07:00
|
|
|
|
2019-12-04 17:53:37 -07:00
|
|
|
ret = pca953x_read_regs(chip, chip->regs->input, irq_stat);
|
2019-01-16 02:31:57 -07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* There is no way to know which GPIO line generated the
|
|
|
|
* interrupt. We have to rely on the previous read for
|
|
|
|
* this purpose.
|
|
|
|
*/
|
2019-08-26 23:46:29 -07:00
|
|
|
pca953x_read_regs(chip, chip->regs->direction, reg_direction);
|
2023-09-01 06:40:38 -07:00
|
|
|
bitmap_and(chip->irq_stat, irq_stat, reg_direction, gc->ngpio);
|
2019-01-16 02:31:57 -07:00
|
|
|
mutex_init(&chip->irq_lock);
|
|
|
|
|
2020-07-17 07:40:40 -07:00
|
|
|
girq = &chip->gpio_chip.irq;
|
2022-05-20 03:21:54 -07:00
|
|
|
gpio_irq_chip_set_chip(girq, &pca953x_irq_chip);
|
2020-07-17 07:40:40 -07:00
|
|
|
/* This will let us handle the parent IRQ in the driver */
|
|
|
|
girq->parent_handler = NULL;
|
|
|
|
girq->num_parents = 0;
|
|
|
|
girq->parents = NULL;
|
|
|
|
girq->default_type = IRQ_TYPE_NONE;
|
|
|
|
girq->handler = handle_simple_irq;
|
|
|
|
girq->threaded = true;
|
|
|
|
girq->first = irq_base; /* FIXME: get rid of this */
|
2019-01-16 02:31:57 -07:00
|
|
|
|
2023-09-01 06:40:37 -07:00
|
|
|
ret = devm_request_threaded_irq(dev, client->irq, NULL, pca953x_irq_handler,
|
|
|
|
IRQF_ONESHOT | IRQF_SHARED, dev_name(dev),
|
|
|
|
chip);
|
2023-09-01 06:40:34 -07:00
|
|
|
if (ret)
|
|
|
|
return dev_err_probe(dev, client->irq, "failed to request irq\n");
|
2020-07-28 05:55:02 -07:00
|
|
|
|
2010-03-05 14:44:36 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#else /* CONFIG_GPIO_PCA953X_IRQ */
|
2023-09-01 06:40:37 -07:00
|
|
|
static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base)
|
2010-03-05 14:44:36 -07:00
|
|
|
{
|
|
|
|
struct i2c_client *client = chip->client;
|
2023-09-01 06:40:37 -07:00
|
|
|
struct device *dev = &client->dev;
|
2010-03-05 14:44:36 -07:00
|
|
|
|
2018-06-21 06:38:46 -07:00
|
|
|
if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT))
|
2023-09-01 06:40:37 -07:00
|
|
|
dev_warn(dev, "interrupt support not compiled in\n");
|
2010-03-05 14:44:36 -07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2023-09-01 06:40:32 -07:00
|
|
|
static int device_pca95xx_init(struct pca953x_chip *chip)
|
2011-04-18 07:12:46 -07:00
|
|
|
{
|
2019-12-04 17:53:37 -07:00
|
|
|
DECLARE_BITMAP(val, MAX_LINE);
|
2022-07-18 01:31:43 -07:00
|
|
|
u8 regaddr;
|
2011-04-18 07:12:46 -07:00
|
|
|
int ret;
|
|
|
|
|
2022-09-14 08:15:57 -07:00
|
|
|
regaddr = chip->recalc_addr(chip, chip->regs->output, 0);
|
2022-07-18 01:31:43 -07:00
|
|
|
ret = regcache_sync_region(chip->regmap, regaddr,
|
|
|
|
regaddr + NBANK(chip) - 1);
|
2019-08-01 10:39:37 -07:00
|
|
|
if (ret)
|
2023-09-01 06:40:40 -07:00
|
|
|
return ret;
|
2011-04-18 07:12:46 -07:00
|
|
|
|
2022-09-14 08:15:57 -07:00
|
|
|
regaddr = chip->recalc_addr(chip, chip->regs->direction, 0);
|
2022-07-18 01:31:43 -07:00
|
|
|
ret = regcache_sync_region(chip->regmap, regaddr,
|
|
|
|
regaddr + NBANK(chip) - 1);
|
2019-08-01 10:39:37 -07:00
|
|
|
if (ret)
|
2023-09-01 06:40:40 -07:00
|
|
|
return ret;
|
2011-04-18 07:12:46 -07:00
|
|
|
|
2023-09-01 06:40:32 -07:00
|
|
|
/* clear polarity inversion */
|
|
|
|
bitmap_zero(val, MAX_LINE);
|
2013-01-22 14:10:23 -07:00
|
|
|
|
2023-09-01 06:40:40 -07:00
|
|
|
return pca953x_write_regs(chip, chip->regs->invert, val);
|
2011-04-18 07:12:46 -07:00
|
|
|
}
|
|
|
|
|
2023-09-01 06:40:32 -07:00
|
|
|
static int device_pca957x_init(struct pca953x_chip *chip)
|
2011-04-18 07:12:46 -07:00
|
|
|
{
|
2019-12-04 17:53:37 -07:00
|
|
|
DECLARE_BITMAP(val, MAX_LINE);
|
2020-09-30 07:20:13 -07:00
|
|
|
unsigned int i;
|
2011-04-18 07:12:46 -07:00
|
|
|
int ret;
|
|
|
|
|
2023-09-01 06:40:32 -07:00
|
|
|
ret = device_pca95xx_init(chip);
|
2015-08-26 14:52:19 -07:00
|
|
|
if (ret)
|
2023-09-01 06:40:40 -07:00
|
|
|
return ret;
|
2011-04-18 07:12:46 -07:00
|
|
|
|
2015-05-18 11:41:43 -07:00
|
|
|
/* To enable register 6, 7 to control pull up and pull down */
|
2020-09-30 07:20:13 -07:00
|
|
|
for (i = 0; i < NBANK(chip); i++)
|
|
|
|
bitmap_set_value8(val, 0x02, i * BANK_SZ);
|
|
|
|
|
2023-09-01 06:40:40 -07:00
|
|
|
return pca953x_write_regs(chip, PCA957X_BKEN, val);
|
2011-04-18 07:12:46 -07:00
|
|
|
}
|
|
|
|
|
2023-09-01 06:40:33 -07:00
|
|
|
static void pca953x_disable_regulator(void *reg)
|
|
|
|
{
|
|
|
|
regulator_disable(reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int pca953x_get_and_enable_regulator(struct pca953x_chip *chip)
|
|
|
|
{
|
|
|
|
struct device *dev = &chip->client->dev;
|
|
|
|
struct regulator *reg = chip->regulator;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
reg = devm_regulator_get(dev, "vcc");
|
|
|
|
if (IS_ERR(reg))
|
|
|
|
return dev_err_probe(dev, PTR_ERR(reg), "reg get err\n");
|
|
|
|
|
|
|
|
ret = regulator_enable(reg);
|
|
|
|
if (ret)
|
|
|
|
return dev_err_probe(dev, ret, "reg en err\n");
|
|
|
|
|
|
|
|
ret = devm_add_action_or_reset(dev, pca953x_disable_regulator, reg);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
chip->regulator = reg;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2022-11-18 15:35:46 -07:00
|
|
|
static int pca953x_probe(struct i2c_client *client)
|
2008-02-04 23:28:26 -07:00
|
|
|
{
|
2023-09-01 06:40:33 -07:00
|
|
|
struct device *dev = &client->dev;
|
2008-02-06 02:39:03 -07:00
|
|
|
struct pca953x_platform_data *pdata;
|
|
|
|
struct pca953x_chip *chip;
|
2023-09-01 06:40:32 -07:00
|
|
|
int irq_base;
|
2011-10-14 06:32:00 -07:00
|
|
|
int ret;
|
2020-04-20 10:27:51 -07:00
|
|
|
const struct regmap_config *regmap_config;
|
2008-02-04 23:28:26 -07:00
|
|
|
|
2023-09-01 06:40:37 -07:00
|
|
|
chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
|
2009-06-17 16:26:17 -07:00
|
|
|
if (chip == NULL)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2023-09-01 06:40:37 -07:00
|
|
|
pdata = dev_get_platdata(dev);
|
2011-06-14 02:00:55 -07:00
|
|
|
if (pdata) {
|
|
|
|
irq_base = pdata->irq_base;
|
|
|
|
chip->gpio_start = pdata->gpio_base;
|
|
|
|
} else {
|
2017-01-10 12:29:51 -07:00
|
|
|
struct gpio_desc *reset_gpio;
|
|
|
|
|
2014-07-29 00:24:43 -07:00
|
|
|
chip->gpio_start = -1;
|
|
|
|
irq_base = 0;
|
2017-01-10 12:29:51 -07:00
|
|
|
|
2017-03-22 07:11:13 -07:00
|
|
|
/*
|
|
|
|
* See if we need to de-assert a reset pin.
|
|
|
|
*
|
|
|
|
* There is no known ACPI-enabled platforms that are
|
|
|
|
* using "reset" GPIO. Otherwise any of those platform
|
|
|
|
* must use _DSD method with corresponding property.
|
|
|
|
*/
|
2023-09-01 06:40:37 -07:00
|
|
|
reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
|
2017-01-10 12:29:51 -07:00
|
|
|
if (IS_ERR(reset_gpio))
|
|
|
|
return PTR_ERR(reset_gpio);
|
2009-06-17 16:26:17 -07:00
|
|
|
}
|
2008-02-04 23:28:26 -07:00
|
|
|
|
|
|
|
chip->client = client;
|
2023-08-24 09:00:17 -07:00
|
|
|
chip->driver_data = (uintptr_t)i2c_get_match_data(client);
|
|
|
|
if (!chip->driver_data)
|
|
|
|
return -ENODEV;
|
2008-02-04 23:28:26 -07:00
|
|
|
|
2023-09-01 06:40:33 -07:00
|
|
|
ret = pca953x_get_and_enable_regulator(chip);
|
|
|
|
if (ret)
|
2016-07-28 20:39:55 -07:00
|
|
|
return ret;
|
|
|
|
|
2018-12-11 18:39:58 -07:00
|
|
|
i2c_set_clientdata(client, chip);
|
|
|
|
|
2020-04-20 10:27:51 -07:00
|
|
|
pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
|
|
|
|
|
|
|
|
if (NBANK(chip) > 2 || PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
|
2023-09-01 06:40:37 -07:00
|
|
|
dev_info(dev, "using AI\n");
|
2020-04-20 10:27:51 -07:00
|
|
|
regmap_config = &pca953x_ai_i2c_regmap;
|
|
|
|
} else {
|
2023-09-01 06:40:37 -07:00
|
|
|
dev_info(dev, "using no AI\n");
|
2020-04-20 10:27:51 -07:00
|
|
|
regmap_config = &pca953x_i2c_regmap;
|
|
|
|
}
|
|
|
|
|
2022-09-14 08:15:57 -07:00
|
|
|
if (PCA_CHIP_TYPE(chip->driver_data) == PCAL653X_TYPE) {
|
|
|
|
chip->recalc_addr = pcal6534_recalc_addr;
|
|
|
|
chip->check_reg = pcal6534_check_register;
|
|
|
|
} else {
|
|
|
|
chip->recalc_addr = pca953x_recalc_addr;
|
|
|
|
chip->check_reg = pca953x_check_register;
|
|
|
|
}
|
|
|
|
|
2020-04-20 10:27:51 -07:00
|
|
|
chip->regmap = devm_regmap_init_i2c(client, regmap_config);
|
2023-09-01 06:40:33 -07:00
|
|
|
if (IS_ERR(chip->regmap))
|
|
|
|
return PTR_ERR(chip->regmap);
|
2018-12-11 18:39:58 -07:00
|
|
|
|
2018-12-11 18:39:59 -07:00
|
|
|
regcache_mark_dirty(chip->regmap);
|
|
|
|
|
2011-02-10 16:01:23 -07:00
|
|
|
mutex_init(&chip->i2c_lock);
|
2016-09-26 02:54:15 -07:00
|
|
|
/*
|
|
|
|
* In case we have an i2c-mux controlled by a GPIO provided by an
|
|
|
|
* expander using the same driver higher on the device tree, read the
|
|
|
|
* i2c adapter nesting depth and use the retrieved value as lockdep
|
|
|
|
* subclass for chip->i2c_lock.
|
|
|
|
*
|
|
|
|
* REVISIT: This solution is not complete. It protects us from lockdep
|
|
|
|
* false positives when the expander controlling the i2c-mux is on
|
|
|
|
* a different level on the device tree, but not when it's on the same
|
|
|
|
* level on a different branch (in which case the subclass number
|
|
|
|
* would be the same).
|
|
|
|
*
|
|
|
|
* TODO: Once a correct solution is developed, a similar fix should be
|
|
|
|
* applied to all other i2c-controlled GPIO expanders (and potentially
|
|
|
|
* regmap-i2c).
|
|
|
|
*/
|
2016-09-16 09:02:45 -07:00
|
|
|
lockdep_set_subclass(&chip->i2c_lock,
|
|
|
|
i2c_adapter_depth(client->adapter));
|
2011-02-10 16:01:23 -07:00
|
|
|
|
2008-02-04 23:28:26 -07:00
|
|
|
/* initialize cached registers from their original values.
|
|
|
|
* we can't share this chip with another i2c master.
|
|
|
|
*/
|
2022-09-14 08:15:56 -07:00
|
|
|
if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
|
2018-12-11 18:39:55 -07:00
|
|
|
chip->regs = &pca957x_regs;
|
2023-09-01 06:40:32 -07:00
|
|
|
ret = device_pca957x_init(chip);
|
2022-09-14 08:15:56 -07:00
|
|
|
} else {
|
|
|
|
chip->regs = &pca953x_regs;
|
2023-09-01 06:40:32 -07:00
|
|
|
ret = device_pca95xx_init(chip);
|
2018-12-11 18:39:55 -07:00
|
|
|
}
|
2011-10-14 06:32:00 -07:00
|
|
|
if (ret)
|
2023-09-01 06:40:33 -07:00
|
|
|
return ret;
|
2008-02-04 23:28:26 -07:00
|
|
|
|
2020-07-17 07:40:40 -07:00
|
|
|
ret = pca953x_irq_setup(chip, irq_base);
|
2010-03-05 14:44:36 -07:00
|
|
|
if (ret)
|
2023-09-01 06:40:33 -07:00
|
|
|
return ret;
|
2008-02-04 23:28:26 -07:00
|
|
|
|
2023-09-01 06:40:33 -07:00
|
|
|
return devm_gpiochip_add_data(dev, &chip->gpio_chip, chip);
|
2008-02-04 23:28:26 -07:00
|
|
|
}
|
|
|
|
|
2023-09-01 06:40:35 -07:00
|
|
|
static int pca953x_regcache_sync(struct pca953x_chip *chip)
|
2018-12-11 18:40:02 -07:00
|
|
|
{
|
2023-09-01 06:40:35 -07:00
|
|
|
struct device *dev = &chip->client->dev;
|
2018-12-11 18:40:02 -07:00
|
|
|
int ret;
|
2022-05-30 03:48:48 -07:00
|
|
|
u8 regaddr;
|
2018-12-11 18:40:02 -07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* The ordering between direction and output is important,
|
|
|
|
* sync these registers first and only then sync the rest.
|
|
|
|
*/
|
2022-09-14 08:15:57 -07:00
|
|
|
regaddr = chip->recalc_addr(chip, chip->regs->direction, 0);
|
2022-07-18 01:31:42 -07:00
|
|
|
ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1);
|
2019-08-01 10:39:37 -07:00
|
|
|
if (ret) {
|
2018-12-11 18:40:02 -07:00
|
|
|
dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2022-09-14 08:15:57 -07:00
|
|
|
regaddr = chip->recalc_addr(chip, chip->regs->output, 0);
|
2022-07-18 01:31:42 -07:00
|
|
|
ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1);
|
2019-08-01 10:39:37 -07:00
|
|
|
if (ret) {
|
2018-12-11 18:40:02 -07:00
|
|
|
dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_GPIO_PCA953X_IRQ
|
|
|
|
if (chip->driver_data & PCA_PCAL) {
|
2022-09-14 08:15:57 -07:00
|
|
|
regaddr = chip->recalc_addr(chip, PCAL953X_IN_LATCH, 0);
|
2022-05-30 03:48:48 -07:00
|
|
|
ret = regcache_sync_region(chip->regmap, regaddr,
|
2022-07-18 01:31:42 -07:00
|
|
|
regaddr + NBANK(chip) - 1);
|
2019-08-01 10:39:37 -07:00
|
|
|
if (ret) {
|
2018-12-11 18:40:02 -07:00
|
|
|
dev_err(dev, "Failed to sync INT latch registers: %d\n",
|
|
|
|
ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2022-09-14 08:15:57 -07:00
|
|
|
regaddr = chip->recalc_addr(chip, PCAL953X_INT_MASK, 0);
|
2022-05-30 03:48:48 -07:00
|
|
|
ret = regcache_sync_region(chip->regmap, regaddr,
|
2022-07-18 01:31:42 -07:00
|
|
|
regaddr + NBANK(chip) - 1);
|
2019-08-01 10:39:37 -07:00
|
|
|
if (ret) {
|
2018-12-11 18:40:02 -07:00
|
|
|
dev_err(dev, "Failed to sync INT mask registers: %d\n",
|
|
|
|
ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2023-09-01 06:40:35 -07:00
|
|
|
static int pca953x_restore_context(struct pca953x_chip *chip)
|
2018-12-11 18:40:02 -07:00
|
|
|
{
|
2023-09-01 06:40:35 -07:00
|
|
|
int ret;
|
|
|
|
|
2023-09-01 06:40:36 -07:00
|
|
|
guard(mutex)(&chip->i2c_lock);
|
2023-09-01 06:40:35 -07:00
|
|
|
|
|
|
|
regcache_cache_only(chip->regmap, false);
|
|
|
|
regcache_mark_dirty(chip->regmap);
|
|
|
|
ret = pca953x_regcache_sync(chip);
|
2023-09-01 06:40:36 -07:00
|
|
|
if (ret)
|
2023-09-01 06:40:35 -07:00
|
|
|
return ret;
|
|
|
|
|
2023-09-01 06:40:36 -07:00
|
|
|
return regcache_sync(chip->regmap);
|
2023-09-01 06:40:35 -07:00
|
|
|
}
|
2018-12-11 18:40:02 -07:00
|
|
|
|
2023-09-01 06:40:35 -07:00
|
|
|
static void pca953x_save_context(struct pca953x_chip *chip)
|
|
|
|
{
|
2023-09-01 06:40:36 -07:00
|
|
|
guard(mutex)(&chip->i2c_lock);
|
2018-12-11 18:40:02 -07:00
|
|
|
regcache_cache_only(chip->regmap, true);
|
2023-09-01 06:40:35 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int pca953x_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct pca953x_chip *chip = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
pca953x_save_context(chip);
|
2018-12-11 18:40:02 -07:00
|
|
|
|
2019-03-20 03:39:27 -07:00
|
|
|
if (atomic_read(&chip->wakeup_path))
|
|
|
|
device_set_wakeup_path(dev);
|
|
|
|
else
|
|
|
|
regulator_disable(chip->regulator);
|
2018-12-11 18:40:02 -07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int pca953x_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct pca953x_chip *chip = dev_get_drvdata(dev);
|
|
|
|
int ret;
|
|
|
|
|
2019-03-20 03:39:27 -07:00
|
|
|
if (!atomic_read(&chip->wakeup_path)) {
|
|
|
|
ret = regulator_enable(chip->regulator);
|
2019-08-01 10:39:37 -07:00
|
|
|
if (ret) {
|
2019-03-20 03:39:27 -07:00
|
|
|
dev_err(dev, "Failed to enable regulator: %d\n", ret);
|
|
|
|
return 0;
|
|
|
|
}
|
2018-12-11 18:40:02 -07:00
|
|
|
}
|
|
|
|
|
2023-09-01 06:40:35 -07:00
|
|
|
ret = pca953x_restore_context(chip);
|
2023-09-01 06:40:40 -07:00
|
|
|
if (ret)
|
2018-12-11 18:40:02 -07:00
|
|
|
dev_err(dev, "Failed to restore register map: %d\n", ret);
|
|
|
|
|
2023-09-01 06:40:40 -07:00
|
|
|
return ret;
|
2018-12-11 18:40:02 -07:00
|
|
|
}
|
2023-09-01 06:40:39 -07:00
|
|
|
|
|
|
|
static DEFINE_SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume);
|
2018-12-11 18:40:02 -07:00
|
|
|
|
2015-12-08 03:19:26 -07:00
|
|
|
/* convenience to stop overlong match-table lines */
|
2022-09-14 08:15:57 -07:00
|
|
|
#define OF_653X(__nrgpio, __int) ((void *)(__nrgpio | PCAL653X_TYPE | __int))
|
2015-12-08 03:19:26 -07:00
|
|
|
#define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int)
|
|
|
|
#define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int)
|
|
|
|
|
2012-11-08 10:01:52 -07:00
|
|
|
static const struct of_device_id pca953x_dt_ids[] = {
|
2022-05-04 15:29:16 -07:00
|
|
|
{ .compatible = "nxp,pca6408", .data = OF_953X(8, PCA_INT), },
|
2019-04-09 05:35:46 -07:00
|
|
|
{ .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), },
|
2015-12-08 03:19:26 -07:00
|
|
|
{ .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
|
2021-01-15 09:46:56 -07:00
|
|
|
{ .compatible = "nxp,pca9506", .data = OF_953X(40, PCA_INT), },
|
2015-12-08 03:19:26 -07:00
|
|
|
{ .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
|
|
|
|
{ .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
|
|
|
|
{ .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
|
|
|
|
{ .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },
|
|
|
|
{ .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },
|
|
|
|
{ .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
|
|
|
|
{ .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), },
|
|
|
|
{ .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
|
|
|
|
{ .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), },
|
|
|
|
{ .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), },
|
|
|
|
{ .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), },
|
|
|
|
{ .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
|
|
|
|
{ .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
|
|
|
|
|
2022-09-13 11:24:36 -07:00
|
|
|
{ .compatible = "nxp,pcal6408", .data = OF_953X(8, PCA_LATCH_INT), },
|
2019-04-09 03:25:17 -07:00
|
|
|
{ .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), },
|
2018-05-16 21:59:47 -07:00
|
|
|
{ .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), },
|
2022-09-14 08:15:57 -07:00
|
|
|
{ .compatible = "nxp,pcal6534", .data = OF_653X(34, PCA_LATCH_INT), },
|
2020-06-15 06:22:29 -07:00
|
|
|
{ .compatible = "nxp,pcal9535", .data = OF_953X(16, PCA_LATCH_INT), },
|
2020-09-30 02:20:53 -07:00
|
|
|
{ .compatible = "nxp,pcal9554b", .data = OF_953X( 8, PCA_LATCH_INT), },
|
2018-05-16 21:59:47 -07:00
|
|
|
{ .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), },
|
2018-03-10 04:00:01 -07:00
|
|
|
|
2015-12-08 03:19:26 -07:00
|
|
|
{ .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
|
|
|
|
{ .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
|
|
|
|
{ .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
|
|
|
|
{ .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), },
|
2016-10-17 09:36:49 -07:00
|
|
|
{ .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), },
|
2015-12-08 03:19:26 -07:00
|
|
|
|
|
|
|
{ .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), },
|
2016-05-18 23:47:29 -07:00
|
|
|
{ .compatible = "ti,pca9536", .data = OF_953X( 4, 0), },
|
2015-12-08 03:19:26 -07:00
|
|
|
{ .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },
|
|
|
|
{ .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
|
|
|
|
{ .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
|
2024-05-31 05:18:00 -07:00
|
|
|
{ .compatible = "ti,tca9535", .data = OF_953X(16, PCA_INT), },
|
2023-08-24 16:16:25 -07:00
|
|
|
{ .compatible = "ti,tca9538", .data = OF_953X( 8, PCA_INT), },
|
2019-06-01 00:12:18 -07:00
|
|
|
{ .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), },
|
2015-12-08 03:19:26 -07:00
|
|
|
|
2019-03-21 02:21:45 -07:00
|
|
|
{ .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), },
|
2017-11-16 13:18:32 -07:00
|
|
|
{ .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), },
|
2021-06-13 15:03:26 -07:00
|
|
|
{ .compatible = "onnn,pca9655", .data = OF_953X(16, PCA_INT), },
|
2015-12-08 03:19:26 -07:00
|
|
|
|
|
|
|
{ .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },
|
2012-11-08 10:01:52 -07:00
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
|
|
|
|
|
2008-02-06 02:39:03 -07:00
|
|
|
static struct i2c_driver pca953x_driver = {
|
2008-02-04 23:28:26 -07:00
|
|
|
.driver = {
|
2008-02-06 02:39:03 -07:00
|
|
|
.name = "pca953x",
|
2023-09-01 06:40:39 -07:00
|
|
|
.pm = pm_sleep_ptr(&pca953x_pm_ops),
|
2012-11-08 10:01:52 -07:00
|
|
|
.of_match_table = pca953x_dt_ids,
|
2020-05-20 14:19:14 -07:00
|
|
|
.acpi_match_table = pca953x_acpi_ids,
|
2008-02-04 23:28:26 -07:00
|
|
|
},
|
2023-05-20 10:47:35 -07:00
|
|
|
.probe = pca953x_probe,
|
2008-04-29 14:11:40 -07:00
|
|
|
.id_table = pca953x_id,
|
2008-02-04 23:28:26 -07:00
|
|
|
};
|
|
|
|
|
2008-02-06 02:39:03 -07:00
|
|
|
static int __init pca953x_init(void)
|
2008-02-04 23:28:26 -07:00
|
|
|
{
|
2008-02-06 02:39:03 -07:00
|
|
|
return i2c_add_driver(&pca953x_driver);
|
2008-02-04 23:28:26 -07:00
|
|
|
}
|
2008-10-15 22:03:13 -07:00
|
|
|
/* register after i2c postcore initcall and before
|
|
|
|
* subsys initcalls that may rely on these GPIOs
|
|
|
|
*/
|
|
|
|
subsys_initcall(pca953x_init);
|
2008-02-04 23:28:26 -07:00
|
|
|
|
2008-02-06 02:39:03 -07:00
|
|
|
static void __exit pca953x_exit(void)
|
2008-02-04 23:28:26 -07:00
|
|
|
{
|
2008-02-06 02:39:03 -07:00
|
|
|
i2c_del_driver(&pca953x_driver);
|
2008-02-04 23:28:26 -07:00
|
|
|
}
|
2008-02-06 02:39:03 -07:00
|
|
|
module_exit(pca953x_exit);
|
2008-02-04 23:28:26 -07:00
|
|
|
|
|
|
|
MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
|
2008-02-06 02:39:03 -07:00
|
|
|
MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
|
2008-02-04 23:28:26 -07:00
|
|
|
MODULE_LICENSE("GPL");
|