[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 12:14:41 -07:00
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#ifndef __ARCH_ORION_COMMON_H__
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#define __ARCH_ORION_COMMON_H__
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/*
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* Basic Orion init functions used early by machine-setup.
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*/
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2007-10-23 12:14:42 -07:00
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[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 12:14:41 -07:00
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void __init orion_map_io(void);
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2007-10-23 12:14:42 -07:00
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void __init orion_init_irq(void);
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2007-10-23 12:14:42 -07:00
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void __init orion_init(void);
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/*
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* Enumerations and functions for Orion windows mapping. Used by Orion core
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* functions to map its interfaces and by the machine-setup to map its on-
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* board devices. Details in /mach-orion/addr-map.c
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*/
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enum orion_target {
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ORION_DEV_BOOT = 0,
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ORION_DEV0,
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ORION_DEV1,
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ORION_DEV2,
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ORION_PCIE_MEM,
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ORION_PCIE_IO,
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ORION_PCI_MEM,
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ORION_PCI_IO,
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ORION_DDR,
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ORION_REGS,
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ORION_MAX_TARGETS
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};
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void orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap);
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void orion_setup_cpu_wins(void);
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void orion_setup_eth_wins(void);
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void orion_setup_usb_wins(void);
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void orion_setup_pci_wins(void);
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void orion_setup_pcie_wins(void);
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void orion_setup_sata_wins(void);
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[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 12:14:41 -07:00
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2007-10-23 12:14:42 -07:00
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/*
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* Shared code used internally by other Orion core functions.
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* (/mach-orion/pci.c)
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*/
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struct pci_sys_data;
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struct pci_bus;
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void orion_pcie_id(u32 *dev, u32 *rev);
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u32 orion_pcie_local_bus_nr(void);
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u32 orion_pci_local_bus_nr(void);
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u32 orion_pci_local_dev_nr(void);
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int orion_pci_sys_setup(int nr, struct pci_sys_data *sys);
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struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
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int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 *val);
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int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 val);
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2007-10-23 12:14:42 -07:00
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/*
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* Valid GPIO pins according to MPP setup, used by machine-setup.
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* (/mach-orion/gpio.c).
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*/
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void __init orion_gpio_set_valid_pins(u32 pins);
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void gpio_display(void); /* debug */
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2007-10-23 12:14:42 -07:00
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/*
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* Orion system timer (clocksource + clockevnt, /mach-orion/time.c)
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*/
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extern struct sys_timer orion_timer;
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[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 12:14:41 -07:00
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#endif /* __ARCH_ORION_COMMON_H__ */
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