2008-03-28 12:12:16 -07:00
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* SGI UV APIC functions (note: not an Intel compatible APIC)
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*
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* Copyright (C) 2007 Silicon Graphics, Inc. All rights reserved.
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*/
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#include <linux/threads.h>
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#include <linux/cpumask.h>
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#include <linux/string.h>
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#include <linux/kernel.h>
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#include <linux/ctype.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/bootmem.h>
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#include <linux/module.h>
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#include <asm/smp.h>
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#include <asm/ipi.h>
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#include <asm/genapic.h>
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#include <asm/uv/uv_mmrs.h>
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#include <asm/uv/uv_hub.h>
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DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
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EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
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struct uv_blade_info *uv_blade_info;
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EXPORT_SYMBOL_GPL(uv_blade_info);
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short *uv_node_to_blade;
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EXPORT_SYMBOL_GPL(uv_node_to_blade);
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short *uv_cpu_to_blade;
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EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
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short uv_possible_blades;
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EXPORT_SYMBOL_GPL(uv_possible_blades);
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/* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */
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static cpumask_t uv_target_cpus(void)
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{
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return cpumask_of_cpu(0);
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}
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static cpumask_t uv_vector_allocation_domain(int cpu)
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{
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cpumask_t domain = CPU_MASK_NONE;
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cpu_set(cpu, domain);
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return domain;
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}
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int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
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{
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unsigned long val;
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int nasid;
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nasid = uv_apicid_to_nasid(phys_apicid);
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val = (1UL << UVH_IPI_INT_SEND_SHFT) |
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(phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
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(((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
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2008-04-16 09:45:15 -07:00
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APIC_DM_INIT;
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uv_write_global_mmr64(nasid, UVH_IPI_INT, val);
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mdelay(10);
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val = (1UL << UVH_IPI_INT_SEND_SHFT) |
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(phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
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(((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
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APIC_DM_STARTUP;
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2008-03-28 12:12:16 -07:00
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uv_write_global_mmr64(nasid, UVH_IPI_INT, val);
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return 0;
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}
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static void uv_send_IPI_one(int cpu, int vector)
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{
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2008-04-16 09:45:15 -07:00
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unsigned long val, apicid, lapicid;
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2008-03-28 12:12:16 -07:00
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int nasid;
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apicid = per_cpu(x86_cpu_to_apicid, cpu); /* ZZZ - cache node-local ? */
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2008-04-16 09:45:15 -07:00
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lapicid = apicid & 0x3f; /* ZZZ macro needed */
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2008-03-28 12:12:16 -07:00
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nasid = uv_apicid_to_nasid(apicid);
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val =
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2008-04-16 09:45:15 -07:00
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(1UL << UVH_IPI_INT_SEND_SHFT) | (lapicid <<
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2008-03-28 12:12:16 -07:00
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UVH_IPI_INT_APIC_ID_SHFT) |
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(vector << UVH_IPI_INT_VECTOR_SHFT);
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uv_write_global_mmr64(nasid, UVH_IPI_INT, val);
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}
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static void uv_send_IPI_mask(cpumask_t mask, int vector)
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{
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unsigned int cpu;
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for (cpu = 0; cpu < NR_CPUS; ++cpu)
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if (cpu_isset(cpu, mask))
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uv_send_IPI_one(cpu, vector);
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}
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static void uv_send_IPI_allbutself(int vector)
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{
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cpumask_t mask = cpu_online_map;
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cpu_clear(smp_processor_id(), mask);
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if (!cpus_empty(mask))
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uv_send_IPI_mask(mask, vector);
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}
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static void uv_send_IPI_all(int vector)
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{
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uv_send_IPI_mask(cpu_online_map, vector);
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}
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static int uv_apic_id_registered(void)
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{
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return 1;
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}
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static unsigned int uv_cpu_mask_to_apicid(cpumask_t cpumask)
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{
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int cpu;
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/*
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* We're using fixed IRQ delivery, can only return one phys APIC ID.
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* May as well be the first.
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*/
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cpu = first_cpu(cpumask);
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if ((unsigned)cpu < NR_CPUS)
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return per_cpu(x86_cpu_to_apicid, cpu);
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else
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return BAD_APICID;
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}
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static unsigned int phys_pkg_id(int index_msb)
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{
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return GET_APIC_ID(read_apic_id()) >> index_msb;
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}
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#ifdef ZZZ /* Needs x2apic patch */
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static void uv_send_IPI_self(int vector)
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{
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apic_write(APIC_SELF_IPI, vector);
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}
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#endif
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struct genapic apic_x2apic_uv_x = {
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.name = "UV large system",
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.int_delivery_mode = dest_Fixed,
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.int_dest_mode = (APIC_DEST_PHYSICAL != 0),
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.target_cpus = uv_target_cpus,
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.vector_allocation_domain = uv_vector_allocation_domain,/* Fixme ZZZ */
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.apic_id_registered = uv_apic_id_registered,
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.send_IPI_all = uv_send_IPI_all,
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.send_IPI_allbutself = uv_send_IPI_allbutself,
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.send_IPI_mask = uv_send_IPI_mask,
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/* ZZZ.send_IPI_self = uv_send_IPI_self, */
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.cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
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.phys_pkg_id = phys_pkg_id, /* Fixme ZZZ */
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};
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static __cpuinit void set_x2apic_extra_bits(int nasid)
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{
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__get_cpu_var(x2apic_extra_bits) = ((nasid >> 1) << 6);
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}
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/*
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* Called on boot cpu.
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*/
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static __init void uv_system_init(void)
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{
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union uvh_si_addr_map_config_u m_n_config;
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int bytes, nid, cpu, lcpu, nasid, last_nasid, blade;
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unsigned long mmr_base;
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m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
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mmr_base =
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uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
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~UV_MMR_ENABLE;
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printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
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last_nasid = -1;
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for_each_possible_cpu(cpu) {
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nid = cpu_to_node(cpu);
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nasid = uv_apicid_to_nasid(per_cpu(x86_cpu_to_apicid, cpu));
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if (nasid != last_nasid)
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uv_possible_blades++;
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last_nasid = nasid;
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}
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printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
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bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
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uv_blade_info = alloc_bootmem_pages(bytes);
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bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
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uv_node_to_blade = alloc_bootmem_pages(bytes);
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memset(uv_node_to_blade, 255, bytes);
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bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
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uv_cpu_to_blade = alloc_bootmem_pages(bytes);
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memset(uv_cpu_to_blade, 255, bytes);
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last_nasid = -1;
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blade = -1;
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lcpu = -1;
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for_each_possible_cpu(cpu) {
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nid = cpu_to_node(cpu);
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nasid = uv_apicid_to_nasid(per_cpu(x86_cpu_to_apicid, cpu));
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if (nasid != last_nasid) {
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blade++;
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lcpu = -1;
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uv_blade_info[blade].nr_posible_cpus = 0;
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uv_blade_info[blade].nr_online_cpus = 0;
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}
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last_nasid = nasid;
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lcpu++;
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uv_cpu_hub_info(cpu)->m_val = m_n_config.s.m_skt;
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uv_cpu_hub_info(cpu)->n_val = m_n_config.s.n_skt;
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uv_cpu_hub_info(cpu)->numa_blade_id = blade;
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uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
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uv_cpu_hub_info(cpu)->local_nasid = nasid;
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uv_cpu_hub_info(cpu)->gnode_upper =
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nasid & ~((1 << uv_hub_info->n_val) - 1);
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uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
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uv_cpu_hub_info(cpu)->coherency_domain_number = 0;/* ZZZ */
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uv_blade_info[blade].nasid = nasid;
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uv_blade_info[blade].nr_posible_cpus++;
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uv_node_to_blade[nid] = blade;
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uv_cpu_to_blade[cpu] = blade;
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printk(KERN_DEBUG "UV cpu %d, apicid 0x%x, nasid %d, nid %d\n",
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cpu, per_cpu(x86_cpu_to_apicid, cpu), nasid, nid);
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printk(KERN_DEBUG "UV lcpu %d, blade %d\n", lcpu, blade);
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}
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}
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/*
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* Called on each cpu to initialize the per_cpu UV data area.
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*/
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void __cpuinit uv_cpu_init(void)
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{
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if (!uv_node_to_blade)
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uv_system_init();
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uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
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if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
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set_x2apic_extra_bits(uv_hub_info->local_nasid);
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}
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