2019-05-19 05:08:20 -07:00
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// SPDX-License-Identifier: GPL-2.0-only
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2006-08-29 15:12:40 -07:00
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/*
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* pata_optidma.c - Opti DMA PATA for new ATA layer
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* (C) 2006 Red Hat Inc
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*
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* The Opti DMA controllers are related to the older PIO PCI controllers
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* and indeed the VLB ones. The main differences are that the timing
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* numbers are now based off PCI clocks not VLB and differ, and that
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* MWDMA is supported.
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*
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* This driver should support Viper-N+, FireStar, FireStar Plus.
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*
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* These devices support virtual DMA for read (aka the CS5520). Later
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* chips support UDMA33, but only if the rest of the board logic does,
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* so you have to get this right. We don't support the virtual DMA
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* but we do handle UDMA.
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*
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* Bits that are worth knowing
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* Most control registers are shadowed into I/O registers
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* 0x1F5 bit 0 tells you if the PCI/VLB clock is 33 or 25Mhz
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* Virtual DMA registers *move* between rev 0x02 and rev 0x10
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* UDMA requires a 66MHz FSB
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "pata_optidma"
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2007-03-26 22:43:43 -07:00
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#define DRV_VERSION "0.3.2"
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2006-08-29 15:12:40 -07:00
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enum {
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READ_REG = 0, /* index of Read cycle timing register */
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WRITE_REG = 1, /* index of Write cycle timing register */
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CNTRL_REG = 3, /* index of Control register */
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STRAP_REG = 5, /* index of Strap register */
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MISC_REG = 6 /* index of Miscellaneous register */
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};
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static int pci_clock; /* 0 = 33 1 = 25 */
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/**
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* optidma_pre_reset - probe begin
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2007-08-06 02:36:23 -07:00
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* @link: ATA link
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libata: add deadline support to prereset and reset methods
Add @deadline to prereset and reset methods and make them honor it.
ata_wait_ready() which directly takes @deadline is implemented to be
used as the wait function. This patch is in preparation for EH timing
improvements.
* ata_wait_ready() never does busy sleep. It's only used from EH and
no wait in EH is that urgent. This function also prints 'be
patient' message automatically after 5 secs of waiting if more than
3 secs is remaining till deadline.
* ata_bus_post_reset() now fails with error code if any of its wait
fails. This is important because earlier reset tries will have
shorter timeout than the spec requires. If a device fails to
respond before the short timeout, reset should be retried with
longer timeout rather than silently ignoring the device.
There are three behavior differences.
1. Timeout is applied to both devices at once, not separately. This
is more consistent with what the spec says.
2. When a device passes devchk but fails to become ready before
deadline. Previouly, post_reset would just succeed and let
device classification remove the device. New code fails the
reset thus causing reset retry. After a few times, EH will give
up disabling the port.
3. When slave device passes devchk but fails to become accessible
(TF-wise) after reset. Original code disables dev1 after 30s
timeout and continues as if the device doesn't exist, while the
patched code fails reset. When this happens, new code fails
reset on whole port rather than proceeding with only the primary
device.
If the failing device is suffering transient problems, new code
retries reset which is a better behavior. If the failing device is
actually broken, the net effect is identical to it, but not to the
other device sharing the channel. In the previous code, reset would
have succeeded after 30s thus detecting the working one. In the new
code, reset fails and whole port gets disabled. IMO, it's a
pathological case anyway (broken device sharing bus with working
one) and doesn't really matter.
* ata_bus_softreset() is changed to return error code from
ata_bus_post_reset(). It used to return 0 unconditionally.
* Spin up waiting is to be removed and not converted to honor
deadline.
* To be on the safe side, deadline is set to 40s for the time being.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-02-02 00:50:52 -07:00
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* @deadline: deadline jiffies for the operation
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2006-08-29 15:12:40 -07:00
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*
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* Set up cable type and use generic probe init
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*/
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2006-08-30 21:03:49 -07:00
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2007-08-06 02:36:23 -07:00
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static int optidma_pre_reset(struct ata_link *link, unsigned long deadline)
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2006-08-29 15:12:40 -07:00
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{
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struct ata_port *ap = link->ap;
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2006-08-29 15:12:40 -07:00
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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2006-08-30 21:03:49 -07:00
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static const struct pci_bits optidma_enable_bits = {
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2006-08-29 15:12:40 -07:00
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0x40, 1, 0x08, 0x00
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};
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2006-09-26 09:53:38 -07:00
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if (ap->port_no && !pci_test_config_bits(pdev, &optidma_enable_bits))
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return -ENOENT;
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2008-04-07 06:47:16 -07:00
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return ata_sff_prereset(link, deadline);
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2006-08-29 15:12:40 -07:00
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}
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/**
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* optidma_unlock - unlock control registers
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* @ap: ATA port
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*
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* Unlock the control register block for this adapter. Registers must not
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* be unlocked in a situation where libata might look at them.
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*/
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2006-08-30 21:03:49 -07:00
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2006-08-29 15:12:40 -07:00
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static void optidma_unlock(struct ata_port *ap)
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{
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2007-01-31 23:06:36 -07:00
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void __iomem *regio = ap->ioaddr.cmd_addr;
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2006-08-30 21:03:49 -07:00
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2006-08-29 15:12:40 -07:00
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/* These 3 unlock the control register access */
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2007-01-31 23:06:36 -07:00
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ioread16(regio + 1);
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ioread16(regio + 1);
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iowrite8(3, regio + 2);
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2006-08-29 15:12:40 -07:00
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}
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/**
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* optidma_lock - issue temporary relock
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* @ap: ATA port
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*
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* Re-lock the configuration register settings.
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*/
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2006-08-30 21:03:49 -07:00
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2006-08-29 15:12:40 -07:00
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static void optidma_lock(struct ata_port *ap)
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{
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2007-01-31 23:06:36 -07:00
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void __iomem *regio = ap->ioaddr.cmd_addr;
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2006-08-30 21:03:49 -07:00
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2006-08-29 15:12:40 -07:00
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/* Relock */
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2007-01-31 23:06:36 -07:00
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iowrite8(0x83, regio + 2);
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2006-08-29 15:12:40 -07:00
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}
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/**
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2007-03-26 22:43:43 -07:00
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* optidma_mode_setup - set mode data
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2006-08-29 15:12:40 -07:00
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* @ap: ATA interface
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* @adev: ATA device
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* @mode: Mode to set
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*
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* Called to do the DMA or PIO mode setup. Timing numbers are all
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* pre computed to keep the code clean. There are two tables depending
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* on the hardware clock speed.
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*
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* WARNING: While we do this the IDE registers vanish. If we take an
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* IRQ here we depend on the host set locking to avoid catastrophe.
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*/
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2007-03-26 22:43:43 -07:00
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static void optidma_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode)
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{
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struct ata_device *pair = ata_dev_pair(adev);
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int pio = adev->pio_mode - XFER_PIO_0;
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int dma = adev->dma_mode - XFER_MW_DMA_0;
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2007-01-31 23:06:36 -07:00
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void __iomem *regio = ap->ioaddr.cmd_addr;
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2006-08-29 15:12:40 -07:00
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u8 addr;
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/* Address table precomputed with a DCLK of 2 */
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static const u8 addr_timing[2][5] = {
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{ 0x30, 0x20, 0x20, 0x10, 0x10 },
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{ 0x20, 0x20, 0x10, 0x10, 0x10 }
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};
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static const u8 data_rec_timing[2][5] = {
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{ 0x59, 0x46, 0x30, 0x20, 0x20 },
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{ 0x46, 0x32, 0x20, 0x20, 0x10 }
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};
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static const u8 dma_data_rec_timing[2][3] = {
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{ 0x76, 0x20, 0x20 },
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{ 0x54, 0x20, 0x10 }
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};
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/* Switch from IDE to control mode */
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optidma_unlock(ap);
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2006-08-30 21:03:49 -07:00
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2006-08-29 15:12:40 -07:00
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/*
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* As with many controllers the address setup time is shared
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* and must suit both devices if present. FIXME: Check if we
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* need to look at slowest of PIO/DMA mode of either device
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*/
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if (mode >= XFER_MW_DMA_0)
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addr = 0;
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else
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addr = addr_timing[pci_clock][pio];
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2006-08-30 21:03:49 -07:00
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2006-08-29 15:12:40 -07:00
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if (pair) {
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u8 pair_addr;
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/* Hardware constraint */
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2021-10-11 23:27:48 -07:00
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if (ata_dma_enabled(pair))
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2006-08-29 15:12:40 -07:00
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pair_addr = 0;
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else
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pair_addr = addr_timing[pci_clock][pair->pio_mode - XFER_PIO_0];
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if (pair_addr > addr)
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addr = pair_addr;
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}
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2006-08-30 21:03:49 -07:00
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2006-08-29 15:12:40 -07:00
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/* Commence primary programming sequence */
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/* First we load the device number into the timing select */
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2007-01-31 23:06:36 -07:00
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iowrite8(adev->devno, regio + MISC_REG);
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2006-08-29 15:12:40 -07:00
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/* Now we load the data timings into read data/write data */
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if (mode < XFER_MW_DMA_0) {
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2007-01-31 23:06:36 -07:00
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iowrite8(data_rec_timing[pci_clock][pio], regio + READ_REG);
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iowrite8(data_rec_timing[pci_clock][pio], regio + WRITE_REG);
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2006-08-29 15:12:40 -07:00
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} else if (mode < XFER_UDMA_0) {
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2007-01-31 23:06:36 -07:00
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iowrite8(dma_data_rec_timing[pci_clock][dma], regio + READ_REG);
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iowrite8(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG);
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2006-08-29 15:12:40 -07:00
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}
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/* Finally we load the address setup into the misc register */
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2007-01-31 23:06:36 -07:00
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iowrite8(addr | adev->devno, regio + MISC_REG);
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2006-08-29 15:12:40 -07:00
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/* Programming sequence complete, timing 0 dev 0, timing 1 dev 1 */
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2007-01-31 23:06:36 -07:00
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iowrite8(0x85, regio + CNTRL_REG);
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2006-08-30 21:03:49 -07:00
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2006-08-29 15:12:40 -07:00
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/* Switch back to IDE mode */
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optidma_lock(ap);
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2006-08-30 21:03:49 -07:00
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2006-08-29 15:12:40 -07:00
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/* Note: at this point our programming is incomplete. We are
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not supposed to program PCI 0x43 "things we hacked onto the chip"
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until we've done both sets of PIO/DMA timings */
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}
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/**
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2007-03-26 22:43:43 -07:00
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* optiplus_mode_setup - DMA setup for Firestar Plus
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2006-08-29 15:12:40 -07:00
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* @ap: ATA port
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* @adev: device
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* @mode: desired mode
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*
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* The Firestar plus has additional UDMA functionality for UDMA0-2 and
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* requires we do some additional work. Because the base work we must do
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* is mostly shared we wrap the Firestar setup functionality in this
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* one
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*/
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2007-03-26 22:43:43 -07:00
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static void optiplus_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode)
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2006-08-29 15:12:40 -07:00
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u8 udcfg;
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u8 udslave;
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int dev2 = 2 * adev->devno;
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int unit = 2 * ap->port_no + adev->devno;
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int udma = mode - XFER_UDMA_0;
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2006-08-30 21:03:49 -07:00
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2006-08-29 15:12:40 -07:00
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pci_read_config_byte(pdev, 0x44, &udcfg);
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if (mode <= XFER_UDMA_0) {
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udcfg &= ~(1 << unit);
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2007-03-26 22:43:43 -07:00
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optidma_mode_setup(ap, adev, adev->dma_mode);
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2006-08-29 15:12:40 -07:00
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} else {
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udcfg |= (1 << unit);
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if (ap->port_no) {
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pci_read_config_byte(pdev, 0x45, &udslave);
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udslave &= ~(0x03 << dev2);
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udslave |= (udma << dev2);
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pci_write_config_byte(pdev, 0x45, udslave);
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} else {
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udcfg &= ~(0x30 << dev2);
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udcfg |= (udma << dev2);
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}
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}
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pci_write_config_byte(pdev, 0x44, udcfg);
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}
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/**
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* optidma_set_pio_mode - PIO setup callback
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* @ap: ATA port
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* @adev: Device
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*
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* The libata core provides separate functions for handling PIO and
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* DMA programming. The architecture of the Firestar makes it easier
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* for us to have a common function so we provide wrappers
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*/
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2006-08-30 21:03:49 -07:00
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2006-08-29 15:12:40 -07:00
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static void optidma_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
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{
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2007-03-26 22:43:43 -07:00
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optidma_mode_setup(ap, adev, adev->pio_mode);
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2006-08-29 15:12:40 -07:00
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}
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/**
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* optidma_set_dma_mode - DMA setup callback
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* @ap: ATA port
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* @adev: Device
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*
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* The libata core provides separate functions for handling PIO and
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* DMA programming. The architecture of the Firestar makes it easier
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* for us to have a common function so we provide wrappers
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*/
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2006-08-30 21:03:49 -07:00
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2006-08-29 15:12:40 -07:00
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static void optidma_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
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{
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2007-03-26 22:43:43 -07:00
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optidma_mode_setup(ap, adev, adev->dma_mode);
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2006-08-29 15:12:40 -07:00
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}
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/**
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* optiplus_set_pio_mode - PIO setup callback
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* @ap: ATA port
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* @adev: Device
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*
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* The libata core provides separate functions for handling PIO and
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* DMA programming. The architecture of the Firestar makes it easier
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* for us to have a common function so we provide wrappers
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*/
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2006-08-30 21:03:49 -07:00
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2006-08-29 15:12:40 -07:00
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static void optiplus_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
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{
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2007-03-26 22:43:43 -07:00
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optiplus_mode_setup(ap, adev, adev->pio_mode);
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2006-08-29 15:12:40 -07:00
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}
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/**
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* optiplus_set_dma_mode - DMA setup callback
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* @ap: ATA port
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* @adev: Device
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*
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* The libata core provides separate functions for handling PIO and
|
|
|
|
* DMA programming. The architecture of the Firestar makes it easier
|
|
|
|
* for us to have a common function so we provide wrappers
|
|
|
|
*/
|
2006-08-30 21:03:49 -07:00
|
|
|
|
2006-08-29 15:12:40 -07:00
|
|
|
static void optiplus_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
|
|
|
|
{
|
2007-03-26 22:43:43 -07:00
|
|
|
optiplus_mode_setup(ap, adev, adev->dma_mode);
|
2006-08-29 15:12:40 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2021-02-01 07:39:39 -07:00
|
|
|
* optidma_make_bits43 - PCI setup helper
|
2006-08-29 15:12:40 -07:00
|
|
|
* @adev: ATA device
|
|
|
|
*
|
|
|
|
* Turn the ATA device setup into PCI configuration bits
|
|
|
|
* for register 0x43 and return the two bits needed.
|
|
|
|
*/
|
2006-08-30 21:03:49 -07:00
|
|
|
|
2006-08-29 15:12:40 -07:00
|
|
|
static u8 optidma_make_bits43(struct ata_device *adev)
|
|
|
|
{
|
|
|
|
static const u8 bits43[5] = {
|
|
|
|
0, 0, 0, 1, 2
|
|
|
|
};
|
|
|
|
if (!ata_dev_enabled(adev))
|
|
|
|
return 0;
|
2021-10-11 23:27:48 -07:00
|
|
|
if (ata_dma_enabled(adev))
|
2006-08-29 15:12:40 -07:00
|
|
|
return adev->dma_mode - XFER_MW_DMA_0;
|
|
|
|
return bits43[adev->pio_mode - XFER_PIO_0];
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2007-03-26 22:43:43 -07:00
|
|
|
* optidma_set_mode - mode setup
|
2007-08-06 02:36:23 -07:00
|
|
|
* @link: link to set up
|
2021-02-01 07:39:39 -07:00
|
|
|
* @r_failed: out parameter for failed device
|
2006-08-29 15:12:40 -07:00
|
|
|
*
|
2007-03-26 22:43:43 -07:00
|
|
|
* Use the standard setup to tune the chipset and then finalise the
|
|
|
|
* configuration by writing the nibble of extra bits of data into
|
|
|
|
* the chip.
|
2006-08-29 15:12:40 -07:00
|
|
|
*/
|
2006-08-30 21:03:49 -07:00
|
|
|
|
2007-08-06 02:36:23 -07:00
|
|
|
static int optidma_set_mode(struct ata_link *link, struct ata_device **r_failed)
|
2006-08-29 15:12:40 -07:00
|
|
|
{
|
2007-08-06 02:36:23 -07:00
|
|
|
struct ata_port *ap = link->ap;
|
2006-08-29 15:12:40 -07:00
|
|
|
u8 r;
|
|
|
|
int nybble = 4 * ap->port_no;
|
|
|
|
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
2007-08-06 02:36:23 -07:00
|
|
|
int rc = ata_do_set_mode(link, r_failed);
|
2007-03-26 22:43:43 -07:00
|
|
|
if (rc == 0) {
|
|
|
|
pci_read_config_byte(pdev, 0x43, &r);
|
|
|
|
|
|
|
|
r &= (0x0F << nybble);
|
2007-08-06 02:36:23 -07:00
|
|
|
r |= (optidma_make_bits43(&link->device[0]) +
|
|
|
|
(optidma_make_bits43(&link->device[0]) << 2)) << nybble;
|
2007-03-26 22:43:43 -07:00
|
|
|
pci_write_config_byte(pdev, 0x43, r);
|
|
|
|
}
|
|
|
|
return rc;
|
2006-08-29 15:12:40 -07:00
|
|
|
}
|
|
|
|
|
2023-03-22 12:53:59 -07:00
|
|
|
static const struct scsi_host_template optidma_sht = {
|
2008-03-24 20:22:49 -07:00
|
|
|
ATA_BMDMA_SHT(DRV_NAME),
|
2006-08-29 15:12:40 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct ata_port_operations optidma_port_ops = {
|
libata: implement and use ops inheritance
libata lets low level drivers build ata_port_operations table and
register it with libata core layer. This allows low level drivers
high level of flexibility but also burdens them with lots of
boilerplate entries.
This becomes worse for drivers which support related similar
controllers which differ slightly. They share most of the operations
except for a few. However, the driver still needs to list all
operations for each variant. This results in large number of
duplicate entries, which is not only inefficient but also error-prone
as it becomes very difficult to tell what the actual differences are.
This duplicate boilerplates all over the low level drivers also make
updating the core layer exteremely difficult and error-prone. When
compounded with multi-branched development model, it ends up
accumulating inconsistencies over time. Some of those inconsistencies
cause immediate problems and fixed. Others just remain there dormant
making maintenance increasingly difficult.
To rectify the problem, this patch implements ata_port_operations
inheritance. To allow LLDs to easily re-use their own ops tables
overriding only specific methods, this patch implements poor man's
class inheritance. An ops table has ->inherits field which can be set
to any ops table as long as it doesn't create a loop. When the host
is started, the inheritance chain is followed and any operation which
isn't specified is taken from the nearest ancestor which has it
specified. This operation is called finalization and done only once
per an ops table and the LLD doesn't have to do anything special about
it other than making the ops table non-const such that libata can
update it.
libata provides four base ops tables lower drivers can inherit from -
base, sata, pmp, sff and bmdma. To avoid overriding these ops
accidentaly, these ops are declared const and LLDs should always
inherit these instead of using them directly.
After finalization, all the ops table are identical before and after
the patch except for setting .irq_handler to ata_interrupt in drivers
which didn't use to. The .irq_handler doesn't have any actual effect
and the field will soon be removed by later patch.
* sata_sx4 is still using old style EH and currently doesn't take
advantage of ops inheritance.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-24 20:22:49 -07:00
|
|
|
.inherits = &ata_bmdma_port_ops,
|
|
|
|
.cable_detect = ata_cable_40wire,
|
2006-08-29 15:12:40 -07:00
|
|
|
.set_piomode = optidma_set_pio_mode,
|
|
|
|
.set_dmamode = optidma_set_dma_mode,
|
2007-03-26 22:43:43 -07:00
|
|
|
.set_mode = optidma_set_mode,
|
libata: make reset related methods proper port operations
Currently reset methods are not specified directly in the
ata_port_operations table. If a LLD wants to use custom reset
methods, it should construct and use a error_handler which uses those
reset methods. It's done this way for two reasons.
First, the ops table already contained too many methods and adding
four more of them would noticeably increase the amount of necessary
boilerplate code all over low level drivers.
Second, as ->error_handler uses those reset methods, it can get
confusing. ie. By overriding ->error_handler, those reset ops can be
made useless making layering a bit hazy.
Now that ops table uses inheritance, the first problem doesn't exist
anymore. The second isn't completely solved but is relieved by
providing default values - most drivers can just override what it has
implemented and don't have to concern itself about higher level
callbacks. In fact, there currently is no driver which actually
modifies error handling behavior. Drivers which override
->error_handler just wraps the standard error handler only to prepare
the controller for EH. I don't think making ops layering strict has
any noticeable benefit.
This patch makes ->prereset, ->softreset, ->hardreset, ->postreset and
their PMP counterparts propoer ops. Default ops are provided in the
base ops tables and drivers are converted to override individual reset
methods instead of creating custom error_handler.
* ata_std_error_handler() doesn't use sata_std_hardreset() if SCRs
aren't accessible. sata_promise doesn't need to use separate
error_handlers for PATA and SATA anymore.
* softreset is broken for sata_inic162x and sata_sx4. As libata now
always prefers hardreset, this doesn't really matter but the ops are
forced to NULL using ATA_OP_NULL for documentation purpose.
* pata_hpt374 needs to use different prereset for the first and second
PCI functions. This used to be done by branching from
hpt374_error_handler(). The proper way to do this is to use
separate ops and port_info tables for each function. Converted.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-24 20:22:50 -07:00
|
|
|
.prereset = optidma_pre_reset,
|
2006-08-29 15:12:40 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct ata_port_operations optiplus_port_ops = {
|
libata: implement and use ops inheritance
libata lets low level drivers build ata_port_operations table and
register it with libata core layer. This allows low level drivers
high level of flexibility but also burdens them with lots of
boilerplate entries.
This becomes worse for drivers which support related similar
controllers which differ slightly. They share most of the operations
except for a few. However, the driver still needs to list all
operations for each variant. This results in large number of
duplicate entries, which is not only inefficient but also error-prone
as it becomes very difficult to tell what the actual differences are.
This duplicate boilerplates all over the low level drivers also make
updating the core layer exteremely difficult and error-prone. When
compounded with multi-branched development model, it ends up
accumulating inconsistencies over time. Some of those inconsistencies
cause immediate problems and fixed. Others just remain there dormant
making maintenance increasingly difficult.
To rectify the problem, this patch implements ata_port_operations
inheritance. To allow LLDs to easily re-use their own ops tables
overriding only specific methods, this patch implements poor man's
class inheritance. An ops table has ->inherits field which can be set
to any ops table as long as it doesn't create a loop. When the host
is started, the inheritance chain is followed and any operation which
isn't specified is taken from the nearest ancestor which has it
specified. This operation is called finalization and done only once
per an ops table and the LLD doesn't have to do anything special about
it other than making the ops table non-const such that libata can
update it.
libata provides four base ops tables lower drivers can inherit from -
base, sata, pmp, sff and bmdma. To avoid overriding these ops
accidentaly, these ops are declared const and LLDs should always
inherit these instead of using them directly.
After finalization, all the ops table are identical before and after
the patch except for setting .irq_handler to ata_interrupt in drivers
which didn't use to. The .irq_handler doesn't have any actual effect
and the field will soon be removed by later patch.
* sata_sx4 is still using old style EH and currently doesn't take
advantage of ops inheritance.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-24 20:22:49 -07:00
|
|
|
.inherits = &optidma_port_ops,
|
2006-08-29 15:12:40 -07:00
|
|
|
.set_piomode = optiplus_set_pio_mode,
|
|
|
|
.set_dmamode = optiplus_set_dma_mode,
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* optiplus_with_udma - Look for UDMA capable setup
|
2021-02-01 07:39:39 -07:00
|
|
|
* @pdev: ATA controller
|
2006-08-29 15:12:40 -07:00
|
|
|
*/
|
2006-08-30 21:03:49 -07:00
|
|
|
|
2006-08-29 15:12:40 -07:00
|
|
|
static int optiplus_with_udma(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
u8 r;
|
|
|
|
int ret = 0;
|
|
|
|
int ioport = 0x22;
|
|
|
|
struct pci_dev *dev1;
|
2006-08-30 21:03:49 -07:00
|
|
|
|
2006-08-29 15:12:40 -07:00
|
|
|
/* Find function 1 */
|
|
|
|
dev1 = pci_get_device(0x1045, 0xC701, NULL);
|
2007-10-25 17:47:30 -07:00
|
|
|
if (dev1 == NULL)
|
2006-08-29 15:12:40 -07:00
|
|
|
return 0;
|
2006-08-30 21:03:49 -07:00
|
|
|
|
2006-08-29 15:12:40 -07:00
|
|
|
/* Rev must be >= 0x10 */
|
|
|
|
pci_read_config_byte(dev1, 0x08, &r);
|
|
|
|
if (r < 0x10)
|
|
|
|
goto done_nomsg;
|
|
|
|
/* Read the chipset system configuration to check our mode */
|
|
|
|
pci_read_config_byte(dev1, 0x5F, &r);
|
|
|
|
ioport |= (r << 8);
|
|
|
|
outb(0x10, ioport);
|
|
|
|
/* Must be 66Mhz sync */
|
|
|
|
if ((inb(ioport + 2) & 1) == 0)
|
|
|
|
goto done;
|
|
|
|
|
|
|
|
/* Check the ATA arbitration/timing is suitable */
|
|
|
|
pci_read_config_byte(pdev, 0x42, &r);
|
|
|
|
if ((r & 0x36) != 0x36)
|
|
|
|
goto done;
|
|
|
|
pci_read_config_byte(dev1, 0x52, &r);
|
|
|
|
if (r & 0x80) /* IDEDIR disabled */
|
|
|
|
ret = 1;
|
2006-08-30 21:03:49 -07:00
|
|
|
done:
|
2006-08-29 15:12:40 -07:00
|
|
|
printk(KERN_WARNING "UDMA not supported in this configuration.\n");
|
|
|
|
done_nomsg: /* Wrong chip revision */
|
|
|
|
pci_dev_put(dev1);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int optidma_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
|
|
|
{
|
2007-05-04 03:43:58 -07:00
|
|
|
static const struct ata_port_info info_82c700 = {
|
2007-05-28 03:59:48 -07:00
|
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
2009-03-14 13:38:24 -07:00
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
.mwdma_mask = ATA_MWDMA2,
|
2006-08-29 15:12:40 -07:00
|
|
|
.port_ops = &optidma_port_ops
|
|
|
|
};
|
2007-05-04 03:43:58 -07:00
|
|
|
static const struct ata_port_info info_82c700_udma = {
|
2007-05-28 03:59:48 -07:00
|
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
2009-03-14 13:38:24 -07:00
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
.mwdma_mask = ATA_MWDMA2,
|
|
|
|
.udma_mask = ATA_UDMA2,
|
2006-08-29 15:12:40 -07:00
|
|
|
.port_ops = &optiplus_port_ops
|
|
|
|
};
|
2007-05-04 03:43:58 -07:00
|
|
|
const struct ata_port_info *ppi[] = { &info_82c700, NULL };
|
2008-03-24 20:22:47 -07:00
|
|
|
int rc;
|
2006-08-29 15:12:40 -07:00
|
|
|
|
2011-04-15 15:52:00 -07:00
|
|
|
ata_print_version_once(&dev->dev, DRV_VERSION);
|
2006-08-29 15:12:40 -07:00
|
|
|
|
2008-03-24 20:22:47 -07:00
|
|
|
rc = pcim_enable_device(dev);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
2006-08-29 15:12:40 -07:00
|
|
|
/* Fixed location chipset magic */
|
|
|
|
inw(0x1F1);
|
|
|
|
inw(0x1F1);
|
|
|
|
pci_clock = inb(0x1F5) & 1; /* 0 = 33Mhz, 1 = 25Mhz */
|
2006-08-30 21:03:49 -07:00
|
|
|
|
2006-08-29 15:12:40 -07:00
|
|
|
if (optiplus_with_udma(dev))
|
2007-05-04 03:43:58 -07:00
|
|
|
ppi[0] = &info_82c700_udma;
|
2006-08-29 15:12:40 -07:00
|
|
|
|
2010-05-19 13:10:22 -07:00
|
|
|
return ata_pci_bmdma_init_one(dev, ppi, &optidma_sht, NULL, 0);
|
2006-08-29 15:12:40 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static const struct pci_device_id optidma[] = {
|
2006-09-28 17:21:59 -07:00
|
|
|
{ PCI_VDEVICE(OPTI, 0xD568), }, /* Opti 82C700 */
|
|
|
|
|
|
|
|
{ },
|
2006-08-29 15:12:40 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct pci_driver optidma_pci_driver = {
|
2006-09-28 17:21:59 -07:00
|
|
|
.name = DRV_NAME,
|
2006-08-29 15:12:40 -07:00
|
|
|
.id_table = optidma,
|
|
|
|
.probe = optidma_init_one,
|
2006-11-22 09:57:36 -07:00
|
|
|
.remove = ata_pci_remove_one,
|
2014-05-07 08:17:44 -07:00
|
|
|
#ifdef CONFIG_PM_SLEEP
|
2006-11-22 09:57:36 -07:00
|
|
|
.suspend = ata_pci_device_suspend,
|
|
|
|
.resume = ata_pci_device_resume,
|
2007-03-02 01:31:26 -07:00
|
|
|
#endif
|
2006-08-29 15:12:40 -07:00
|
|
|
};
|
|
|
|
|
2012-04-18 22:43:05 -07:00
|
|
|
module_pci_driver(optidma_pci_driver);
|
2006-08-29 15:12:40 -07:00
|
|
|
|
|
|
|
MODULE_AUTHOR("Alan Cox");
|
|
|
|
MODULE_DESCRIPTION("low-level driver for Opti Firestar/Firestar Plus");
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_DEVICE_TABLE(pci, optidma);
|
|
|
|
MODULE_VERSION(DRV_VERSION);
|