2024-02-17 00:40:43 -07:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Instruction binary disassembler based on capstone.
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*
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* Author(s): Changbin Du <changbin.du@huawei.com>
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*/
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2024-04-01 14:08:05 -07:00
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#include <inttypes.h>
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2024-02-17 00:40:43 -07:00
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#include <string.h>
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#include <stdbool.h>
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#include "debug.h"
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#include "sample.h"
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#include "symbol.h"
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#include "machine.h"
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#include "thread.h"
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#include "print_insn.h"
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perf script: Add capstone support for '-F +brstackdisasm'
Support capstone output for the '-F +brstackinsn' branch dump.
The new output is enabled with the new field 'brstackdisasm'.
This was possible before with --xed, but now also allow it for users
that don't have xed using the builtin capstone support.
Before:
perf record -b emacs -Q --batch '()'
perf script -F +brstackinsn
...
emacs 55778 1814366.755945: 151564 cycles:P: 7f0ab2d17192 intel_check_word.constprop.0+0x162 (/usr/lib64/ld-linux-x86-64.s> intel_check_word.constprop.0+237:
00007f0ab2d1711d insn: 75 e6 # PRED 3 cycles [3]
00007f0ab2d17105 insn: 73 51
00007f0ab2d17107 insn: 48 89 c1
00007f0ab2d1710a insn: 48 39 ca
00007f0ab2d1710d insn: 73 96
00007f0ab2d1710f insn: 48 8d 04 11
00007f0ab2d17113 insn: 48 d1 e8
00007f0ab2d17116 insn: 49 8d 34 c1
00007f0ab2d1711a insn: 44 3a 06
00007f0ab2d1711d insn: 75 e6 # PRED 3 cycles [6] 3.00 IPC
00007f0ab2d17105 insn: 73 51 # PRED 1 cycles [7] 1.00 IPC
00007f0ab2d17158 insn: 48 8d 50 01
00007f0ab2d1715c insn: eb 92 # PRED 1 cycles [8] 2.00 IPC
00007f0ab2d170f0 insn: 48 39 ca
00007f0ab2d170f3 insn: 73 b0 # PRED 1 cycles [9] 2.00 IPC
After (perf must be compiled with capstone):
perf script -F +brstackdisasm
...
emacs 55778 1814366.755945: 151564 cycles:P: 7f0ab2d17192 intel_check_word.constprop.0+0x162 (/usr/lib64/ld-linux-x86-64.s> intel_check_word.constprop.0+237:
00007f0ab2d1711d jne intel_check_word.constprop.0+0xd5 # PRED 3 cycles [3]
00007f0ab2d17105 jae intel_check_word.constprop.0+0x128
00007f0ab2d17107 movq %rax, %rcx
00007f0ab2d1710a cmpq %rcx, %rdx
00007f0ab2d1710d jae intel_check_word.constprop.0+0x75
00007f0ab2d1710f leaq (%rcx, %rdx), %rax
00007f0ab2d17113 shrq $1, %rax
00007f0ab2d17116 leaq (%r9, %rax, 8), %rsi
00007f0ab2d1711a cmpb (%rsi), %r8b
00007f0ab2d1711d jne intel_check_word.constprop.0+0xd5 # PRED 3 cycles [6] 3.00 IPC
00007f0ab2d17105 jae intel_check_word.constprop.0+0x128 # PRED 1 cycles [7] 1.00 IPC
00007f0ab2d17158 leaq 1(%rax), %rdx
00007f0ab2d1715c jmp intel_check_word.constprop.0+0xc0 # PRED 1 cycles [8] 2.00 IPC
00007f0ab2d170f0 cmpq %rcx, %rdx
00007f0ab2d170f3 jae intel_check_word.constprop.0+0x75 # PRED 1 cycles [9] 2.00 IPC
Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Link: https://lore.kernel.org/r/20240401210925.209671-3-ak@linux.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2024-04-01 14:08:04 -07:00
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#include "dump-insn.h"
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2024-04-01 14:08:03 -07:00
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#include "map.h"
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#include "dso.h"
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2024-02-17 00:40:43 -07:00
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size_t sample__fprintf_insn_raw(struct perf_sample *sample, FILE *fp)
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{
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int printed = 0;
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for (int i = 0; i < sample->insn_len; i++) {
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printed += fprintf(fp, "%02x", (unsigned char)sample->insn[i]);
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if (sample->insn_len - i > 1)
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printed += fprintf(fp, " ");
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}
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return printed;
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}
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#ifdef HAVE_LIBCAPSTONE_SUPPORT
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#include <capstone/capstone.h>
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2024-07-18 01:43:56 -07:00
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int capstone_init(struct machine *machine, csh *cs_handle, bool is64, bool disassembler_style);
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2024-07-18 01:43:55 -07:00
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int capstone_init(struct machine *machine, csh *cs_handle, bool is64, bool disassembler_style)
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{
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cs_arch arch;
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cs_mode mode;
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if (machine__is(machine, "x86_64") && is64) {
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arch = CS_ARCH_X86;
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mode = CS_MODE_64;
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} else if (machine__normalized_is(machine, "x86")) {
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arch = CS_ARCH_X86;
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mode = CS_MODE_32;
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} else if (machine__normalized_is(machine, "arm64")) {
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arch = CS_ARCH_ARM64;
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mode = CS_MODE_ARM;
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} else if (machine__normalized_is(machine, "arm")) {
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arch = CS_ARCH_ARM;
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mode = CS_MODE_ARM + CS_MODE_V8;
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} else if (machine__normalized_is(machine, "s390")) {
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arch = CS_ARCH_SYSZ;
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mode = CS_MODE_BIG_ENDIAN;
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} else {
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return -1;
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}
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if (cs_open(arch, mode, cs_handle) != CS_ERR_OK) {
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pr_warning_once("cs_open failed\n");
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return -1;
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}
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if (machine__normalized_is(machine, "x86")) {
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2024-07-18 01:43:55 -07:00
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/*
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* In case of using capstone_init while symbol__disassemble
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* setting CS_OPT_SYNTAX_ATT depends if disassembler_style opts
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* is set via annotation args
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*/
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if (disassembler_style)
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cs_option(*cs_handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_ATT);
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2024-02-17 00:40:43 -07:00
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/*
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* Resolving address operands to symbols is implemented
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* on x86 by investigating instruction details.
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*/
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cs_option(*cs_handle, CS_OPT_DETAIL, CS_OPT_ON);
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}
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return 0;
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}
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2024-04-01 14:08:05 -07:00
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static size_t print_insn_x86(struct thread *thread, u8 cpumode, cs_insn *insn,
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int print_opts, FILE *fp)
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{
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struct addr_location al;
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size_t printed = 0;
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if (insn->detail && insn->detail->x86.op_count == 1) {
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cs_x86_op *op = &insn->detail->x86.operands[0];
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addr_location__init(&al);
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if (op->type == X86_OP_IMM &&
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2024-04-01 14:08:05 -07:00
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thread__find_symbol(thread, cpumode, op->imm, &al)) {
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2024-02-17 00:40:43 -07:00
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printed += fprintf(fp, "%s ", insn[0].mnemonic);
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printed += symbol__fprintf_symname_offs(al.sym, &al, fp);
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2024-04-01 14:08:05 -07:00
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if (print_opts & PRINT_INSN_IMM_HEX)
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printed += fprintf(fp, " [%#" PRIx64 "]", op->imm);
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2024-02-17 00:40:43 -07:00
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addr_location__exit(&al);
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return printed;
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}
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addr_location__exit(&al);
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}
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printed += fprintf(fp, "%s %s", insn[0].mnemonic, insn[0].op_str);
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return printed;
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}
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2024-04-01 14:08:03 -07:00
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static bool is64bitip(struct machine *machine, struct addr_location *al)
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{
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const struct dso *dso = al->map ? map__dso(al->map) : NULL;
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if (dso)
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2024-05-04 14:38:01 -07:00
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return dso__is_64_bit(dso);
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2024-04-01 14:08:03 -07:00
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return machine__is(machine, "x86_64") ||
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machine__normalized_is(machine, "arm64") ||
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machine__normalized_is(machine, "s390");
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}
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2024-04-01 14:08:05 -07:00
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ssize_t fprintf_insn_asm(struct machine *machine, struct thread *thread, u8 cpumode,
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bool is64bit, const uint8_t *code, size_t code_size,
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uint64_t ip, int *lenp, int print_opts, FILE *fp)
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{
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size_t printed;
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2024-02-17 00:40:43 -07:00
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cs_insn *insn;
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csh cs_handle;
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size_t count;
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int ret;
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/* TODO: Try to initiate capstone only once but need a proper place. */
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2024-07-18 01:43:55 -07:00
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ret = capstone_init(machine, &cs_handle, is64bit, true);
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2024-04-01 14:08:05 -07:00
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if (ret < 0)
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return ret;
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2024-02-17 00:40:43 -07:00
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2024-04-01 14:08:05 -07:00
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count = cs_disasm(cs_handle, code, code_size, ip, 1, &insn);
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if (count > 0) {
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if (machine__normalized_is(machine, "x86"))
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2024-04-01 14:08:05 -07:00
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printed = print_insn_x86(thread, cpumode, &insn[0], print_opts, fp);
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2024-02-17 00:40:43 -07:00
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else
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2024-04-01 14:08:05 -07:00
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printed = fprintf(fp, "%s %s", insn[0].mnemonic, insn[0].op_str);
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if (lenp)
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*lenp = insn->size;
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2024-02-17 00:40:43 -07:00
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cs_free(insn, count);
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} else {
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2024-04-01 14:08:05 -07:00
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printed = -1;
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2024-02-17 00:40:43 -07:00
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}
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cs_close(&cs_handle);
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return printed;
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}
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2024-04-01 14:08:05 -07:00
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size_t sample__fprintf_insn_asm(struct perf_sample *sample, struct thread *thread,
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struct machine *machine, FILE *fp,
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struct addr_location *al)
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{
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bool is64bit = is64bitip(machine, al);
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ssize_t printed;
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printed = fprintf_insn_asm(machine, thread, sample->cpumode, is64bit,
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(uint8_t *)sample->insn, sample->insn_len,
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sample->ip, NULL, 0, fp);
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if (printed < 0)
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return sample__fprintf_insn_raw(sample, fp);
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return printed;
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}
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2024-02-17 00:40:43 -07:00
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#else
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size_t sample__fprintf_insn_asm(struct perf_sample *sample __maybe_unused,
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struct thread *thread __maybe_unused,
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struct machine *machine __maybe_unused,
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FILE *fp __maybe_unused,
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struct addr_location *al __maybe_unused)
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{
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return 0;
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}
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#endif
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