1
linux/drivers/platform/mips/cpu_hwmon.c

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// SPDX-License-Identifier: GPL-2.0-only
#include <linux/err.h>
#include <linux/module.h>
#include <linux/reboot.h>
#include <linux/jiffies.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <loongson.h>
#include <boot_param.h>
#include <loongson_hwmon.h>
MIPS: Loongson: Add Loongson-3A R4 basic support All Loongson-3 CPU family: Code-name Brand-name PRId Loongson-3A R1 Loongson-3A1000 0x6305 Loongson-3A R2 Loongson-3A2000 0x6308 Loongson-3A R2.1 Loongson-3A2000 0x630c Loongson-3A R3 Loongson-3A3000 0x6309 Loongson-3A R3.1 Loongson-3A3000 0x630d Loongson-3A R4 Loongson-3A4000 0xc000 Loongson-3B R1 Loongson-3B1000 0x6306 Loongson-3B R2 Loongson-3B1500 0x6307 Features of R4 revision of Loongson-3A: - All R2/R3 features, including SFB, V-Cache, FTLB, RIXI, DSP, etc. - Support variable ASID bits. - Support MSA and VZ extensions. - Support CPUCFG (CPU config) and CSR (Control and Status Register) extensions. - 64 entries of VTLB (classic TLB), 2048 entries of FTLB (8-way set-associative). Now 64-bit Loongson processors has three types of PRID.IMP: 0x6300 is the classic one so we call it PRID_IMP_LOONGSON_64C (e.g., Loongson-2E/ 2F/3A1000/3B1000/3B1500/3A2000/3A3000), 0x6100 is for some processors which has reduced capabilities so we call it PRID_IMP_LOONGSON_64R (e.g., Loongson-2K), 0xc000 is supposed to cover all new processors in general (e.g., Loongson-3A4000+) so we call it PRID_IMP_LOONGSON_64G. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Cc: linux-mips@vger.kernel.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Huacai Chen <chenhuacai@gmail.com>
2019-09-21 06:50:27 -07:00
#include <loongson_regs.h>
MIPS: Loongson: Cleanup cpu_hwmon.c Fix the following checkpatch warnings and errors: ERROR: do not initialise statics to 0 +static int csr_temp_enable = 0; WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(name, S_IRUGO, get_hwmon_name, NULL, 0); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, get_cpu_temp, NULL, 1); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, cpu_temp_label, NULL, 1); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, get_cpu_temp, NULL, 2); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, cpu_temp_label, NULL, 2); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, get_cpu_temp, NULL, 3); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, cpu_temp_label, NULL, 3); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp4_input, S_IRUGO, get_cpu_temp, NULL, 4); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp4_label, S_IRUGO, cpu_temp_label, NULL, 4); WARNING: Missing a blank line after declarations + int id = (to_sensor_dev_attr(attr))->index - 1; + return sprintf(buf, "CPU %d Temperature\n", id); WARNING: Missing a blank line after declarations + int value = loongson3_cpu_temp(id); + return sprintf(buf, "%d\n", value); ERROR: spaces required around that '=' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '<' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '=' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '<' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '=' (ctx:VxV) + for (i=0; i<nr_packages; i++) { ^ ERROR: spaces required around that '<' (ctx:VxV) + for (i=0; i<nr_packages; i++) { ^ WARNING: line over 80 characters + csr_temp_enable = csr_readl(LOONGSON_CSR_FEATURES) & LOONGSON_CSRF_TEMP; Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Zhi Li <lizhi01@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-07-08 20:55:19 -07:00
static int csr_temp_enable;
/*
* Loongson-3 series cpu has two sensors inside,
* each of them from 0 to 255,
* if more than 127, that is dangerous.
* here only provide sensor1 data, because it always hot than sensor0
*/
int loongson3_cpu_temp(int cpu)
{
u32 reg, prid_rev;
MIPS: Loongson: Add Loongson-3A R4 basic support All Loongson-3 CPU family: Code-name Brand-name PRId Loongson-3A R1 Loongson-3A1000 0x6305 Loongson-3A R2 Loongson-3A2000 0x6308 Loongson-3A R2.1 Loongson-3A2000 0x630c Loongson-3A R3 Loongson-3A3000 0x6309 Loongson-3A R3.1 Loongson-3A3000 0x630d Loongson-3A R4 Loongson-3A4000 0xc000 Loongson-3B R1 Loongson-3B1000 0x6306 Loongson-3B R2 Loongson-3B1500 0x6307 Features of R4 revision of Loongson-3A: - All R2/R3 features, including SFB, V-Cache, FTLB, RIXI, DSP, etc. - Support variable ASID bits. - Support MSA and VZ extensions. - Support CPUCFG (CPU config) and CSR (Control and Status Register) extensions. - 64 entries of VTLB (classic TLB), 2048 entries of FTLB (8-way set-associative). Now 64-bit Loongson processors has three types of PRID.IMP: 0x6300 is the classic one so we call it PRID_IMP_LOONGSON_64C (e.g., Loongson-2E/ 2F/3A1000/3B1000/3B1500/3A2000/3A3000), 0x6100 is for some processors which has reduced capabilities so we call it PRID_IMP_LOONGSON_64R (e.g., Loongson-2K), 0xc000 is supposed to cover all new processors in general (e.g., Loongson-3A4000+) so we call it PRID_IMP_LOONGSON_64G. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Cc: linux-mips@vger.kernel.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Huacai Chen <chenhuacai@gmail.com>
2019-09-21 06:50:27 -07:00
if (csr_temp_enable) {
reg = (csr_readl(LOONGSON_CSR_CPUTEMP) & 0xff);
goto out;
}
reg = LOONGSON_CHIPTEMP(cpu);
prid_rev = read_c0_prid() & PRID_REV_MASK;
MIPS: Loongson: Add Loongson-3A R4 basic support All Loongson-3 CPU family: Code-name Brand-name PRId Loongson-3A R1 Loongson-3A1000 0x6305 Loongson-3A R2 Loongson-3A2000 0x6308 Loongson-3A R2.1 Loongson-3A2000 0x630c Loongson-3A R3 Loongson-3A3000 0x6309 Loongson-3A R3.1 Loongson-3A3000 0x630d Loongson-3A R4 Loongson-3A4000 0xc000 Loongson-3B R1 Loongson-3B1000 0x6306 Loongson-3B R2 Loongson-3B1500 0x6307 Features of R4 revision of Loongson-3A: - All R2/R3 features, including SFB, V-Cache, FTLB, RIXI, DSP, etc. - Support variable ASID bits. - Support MSA and VZ extensions. - Support CPUCFG (CPU config) and CSR (Control and Status Register) extensions. - 64 entries of VTLB (classic TLB), 2048 entries of FTLB (8-way set-associative). Now 64-bit Loongson processors has three types of PRID.IMP: 0x6300 is the classic one so we call it PRID_IMP_LOONGSON_64C (e.g., Loongson-2E/ 2F/3A1000/3B1000/3B1500/3A2000/3A3000), 0x6100 is for some processors which has reduced capabilities so we call it PRID_IMP_LOONGSON_64R (e.g., Loongson-2K), 0xc000 is supposed to cover all new processors in general (e.g., Loongson-3A4000+) so we call it PRID_IMP_LOONGSON_64G. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Cc: linux-mips@vger.kernel.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Huacai Chen <chenhuacai@gmail.com>
2019-09-21 06:50:27 -07:00
switch (prid_rev) {
case PRID_REV_LOONGSON3A_R1:
reg = (reg >> 8) & 0xff;
break;
case PRID_REV_LOONGSON3B_R1:
case PRID_REV_LOONGSON3B_R2:
case PRID_REV_LOONGSON3A_R2_0:
case PRID_REV_LOONGSON3A_R2_1:
reg = ((reg >> 8) & 0xff) - 100;
break;
case PRID_REV_LOONGSON3A_R3_0:
case PRID_REV_LOONGSON3A_R3_1:
MIPS: Loongson: Add Loongson-3A R4 basic support All Loongson-3 CPU family: Code-name Brand-name PRId Loongson-3A R1 Loongson-3A1000 0x6305 Loongson-3A R2 Loongson-3A2000 0x6308 Loongson-3A R2.1 Loongson-3A2000 0x630c Loongson-3A R3 Loongson-3A3000 0x6309 Loongson-3A R3.1 Loongson-3A3000 0x630d Loongson-3A R4 Loongson-3A4000 0xc000 Loongson-3B R1 Loongson-3B1000 0x6306 Loongson-3B R2 Loongson-3B1500 0x6307 Features of R4 revision of Loongson-3A: - All R2/R3 features, including SFB, V-Cache, FTLB, RIXI, DSP, etc. - Support variable ASID bits. - Support MSA and VZ extensions. - Support CPUCFG (CPU config) and CSR (Control and Status Register) extensions. - 64 entries of VTLB (classic TLB), 2048 entries of FTLB (8-way set-associative). Now 64-bit Loongson processors has three types of PRID.IMP: 0x6300 is the classic one so we call it PRID_IMP_LOONGSON_64C (e.g., Loongson-2E/ 2F/3A1000/3B1000/3B1500/3A2000/3A3000), 0x6100 is for some processors which has reduced capabilities so we call it PRID_IMP_LOONGSON_64R (e.g., Loongson-2K), 0xc000 is supposed to cover all new processors in general (e.g., Loongson-3A4000+) so we call it PRID_IMP_LOONGSON_64G. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Cc: linux-mips@vger.kernel.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Huacai Chen <chenhuacai@gmail.com>
2019-09-21 06:50:27 -07:00
default:
MIPS: Loongson: Cleanup cpu_hwmon.c Fix the following checkpatch warnings and errors: ERROR: do not initialise statics to 0 +static int csr_temp_enable = 0; WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(name, S_IRUGO, get_hwmon_name, NULL, 0); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, get_cpu_temp, NULL, 1); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, cpu_temp_label, NULL, 1); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, get_cpu_temp, NULL, 2); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, cpu_temp_label, NULL, 2); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, get_cpu_temp, NULL, 3); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, cpu_temp_label, NULL, 3); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp4_input, S_IRUGO, get_cpu_temp, NULL, 4); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp4_label, S_IRUGO, cpu_temp_label, NULL, 4); WARNING: Missing a blank line after declarations + int id = (to_sensor_dev_attr(attr))->index - 1; + return sprintf(buf, "CPU %d Temperature\n", id); WARNING: Missing a blank line after declarations + int value = loongson3_cpu_temp(id); + return sprintf(buf, "%d\n", value); ERROR: spaces required around that '=' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '<' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '=' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '<' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '=' (ctx:VxV) + for (i=0; i<nr_packages; i++) { ^ ERROR: spaces required around that '<' (ctx:VxV) + for (i=0; i<nr_packages; i++) { ^ WARNING: line over 80 characters + csr_temp_enable = csr_readl(LOONGSON_CSR_FEATURES) & LOONGSON_CSRF_TEMP; Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Zhi Li <lizhi01@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-07-08 20:55:19 -07:00
reg = (reg & 0xffff) * 731 / 0x4000 - 273;
break;
}
MIPS: Loongson: Add Loongson-3A R4 basic support All Loongson-3 CPU family: Code-name Brand-name PRId Loongson-3A R1 Loongson-3A1000 0x6305 Loongson-3A R2 Loongson-3A2000 0x6308 Loongson-3A R2.1 Loongson-3A2000 0x630c Loongson-3A R3 Loongson-3A3000 0x6309 Loongson-3A R3.1 Loongson-3A3000 0x630d Loongson-3A R4 Loongson-3A4000 0xc000 Loongson-3B R1 Loongson-3B1000 0x6306 Loongson-3B R2 Loongson-3B1500 0x6307 Features of R4 revision of Loongson-3A: - All R2/R3 features, including SFB, V-Cache, FTLB, RIXI, DSP, etc. - Support variable ASID bits. - Support MSA and VZ extensions. - Support CPUCFG (CPU config) and CSR (Control and Status Register) extensions. - 64 entries of VTLB (classic TLB), 2048 entries of FTLB (8-way set-associative). Now 64-bit Loongson processors has three types of PRID.IMP: 0x6300 is the classic one so we call it PRID_IMP_LOONGSON_64C (e.g., Loongson-2E/ 2F/3A1000/3B1000/3B1500/3A2000/3A3000), 0x6100 is for some processors which has reduced capabilities so we call it PRID_IMP_LOONGSON_64R (e.g., Loongson-2K), 0xc000 is supposed to cover all new processors in general (e.g., Loongson-3A4000+) so we call it PRID_IMP_LOONGSON_64G. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Cc: linux-mips@vger.kernel.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Huacai Chen <chenhuacai@gmail.com>
2019-09-21 06:50:27 -07:00
out:
return (int)reg * 1000;
}
static int nr_packages;
static struct device *cpu_hwmon_dev;
static ssize_t cpu_temp_label(struct device *dev,
struct device_attribute *attr, char *buf)
{
int id = (to_sensor_dev_attr(attr))->index - 1;
MIPS: Loongson: Cleanup cpu_hwmon.c Fix the following checkpatch warnings and errors: ERROR: do not initialise statics to 0 +static int csr_temp_enable = 0; WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(name, S_IRUGO, get_hwmon_name, NULL, 0); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, get_cpu_temp, NULL, 1); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, cpu_temp_label, NULL, 1); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, get_cpu_temp, NULL, 2); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, cpu_temp_label, NULL, 2); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, get_cpu_temp, NULL, 3); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, cpu_temp_label, NULL, 3); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp4_input, S_IRUGO, get_cpu_temp, NULL, 4); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp4_label, S_IRUGO, cpu_temp_label, NULL, 4); WARNING: Missing a blank line after declarations + int id = (to_sensor_dev_attr(attr))->index - 1; + return sprintf(buf, "CPU %d Temperature\n", id); WARNING: Missing a blank line after declarations + int value = loongson3_cpu_temp(id); + return sprintf(buf, "%d\n", value); ERROR: spaces required around that '=' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '<' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '=' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '<' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '=' (ctx:VxV) + for (i=0; i<nr_packages; i++) { ^ ERROR: spaces required around that '<' (ctx:VxV) + for (i=0; i<nr_packages; i++) { ^ WARNING: line over 80 characters + csr_temp_enable = csr_readl(LOONGSON_CSR_FEATURES) & LOONGSON_CSRF_TEMP; Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Zhi Li <lizhi01@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-07-08 20:55:19 -07:00
return sprintf(buf, "CPU %d Temperature\n", id);
}
static ssize_t get_cpu_temp(struct device *dev,
struct device_attribute *attr, char *buf)
{
int id = (to_sensor_dev_attr(attr))->index - 1;
int value = loongson3_cpu_temp(id);
MIPS: Loongson: Cleanup cpu_hwmon.c Fix the following checkpatch warnings and errors: ERROR: do not initialise statics to 0 +static int csr_temp_enable = 0; WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(name, S_IRUGO, get_hwmon_name, NULL, 0); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, get_cpu_temp, NULL, 1); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, cpu_temp_label, NULL, 1); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, get_cpu_temp, NULL, 2); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, cpu_temp_label, NULL, 2); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, get_cpu_temp, NULL, 3); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, cpu_temp_label, NULL, 3); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp4_input, S_IRUGO, get_cpu_temp, NULL, 4); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp4_label, S_IRUGO, cpu_temp_label, NULL, 4); WARNING: Missing a blank line after declarations + int id = (to_sensor_dev_attr(attr))->index - 1; + return sprintf(buf, "CPU %d Temperature\n", id); WARNING: Missing a blank line after declarations + int value = loongson3_cpu_temp(id); + return sprintf(buf, "%d\n", value); ERROR: spaces required around that '=' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '<' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '=' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '<' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '=' (ctx:VxV) + for (i=0; i<nr_packages; i++) { ^ ERROR: spaces required around that '<' (ctx:VxV) + for (i=0; i<nr_packages; i++) { ^ WARNING: line over 80 characters + csr_temp_enable = csr_readl(LOONGSON_CSR_FEATURES) & LOONGSON_CSRF_TEMP; Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Zhi Li <lizhi01@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-07-08 20:55:19 -07:00
return sprintf(buf, "%d\n", value);
}
static SENSOR_DEVICE_ATTR(temp1_input, 0444, get_cpu_temp, NULL, 1);
static SENSOR_DEVICE_ATTR(temp1_label, 0444, cpu_temp_label, NULL, 1);
static SENSOR_DEVICE_ATTR(temp2_input, 0444, get_cpu_temp, NULL, 2);
static SENSOR_DEVICE_ATTR(temp2_label, 0444, cpu_temp_label, NULL, 2);
static SENSOR_DEVICE_ATTR(temp3_input, 0444, get_cpu_temp, NULL, 3);
static SENSOR_DEVICE_ATTR(temp3_label, 0444, cpu_temp_label, NULL, 3);
static SENSOR_DEVICE_ATTR(temp4_input, 0444, get_cpu_temp, NULL, 4);
static SENSOR_DEVICE_ATTR(temp4_label, 0444, cpu_temp_label, NULL, 4);
static struct attribute *cpu_hwmon_attributes[] = {
&sensor_dev_attr_temp1_input.dev_attr.attr,
&sensor_dev_attr_temp1_label.dev_attr.attr,
&sensor_dev_attr_temp2_input.dev_attr.attr,
&sensor_dev_attr_temp2_label.dev_attr.attr,
&sensor_dev_attr_temp3_input.dev_attr.attr,
&sensor_dev_attr_temp3_label.dev_attr.attr,
&sensor_dev_attr_temp4_input.dev_attr.attr,
&sensor_dev_attr_temp4_label.dev_attr.attr,
NULL
};
static umode_t cpu_hwmon_is_visible(struct kobject *kobj,
struct attribute *attr, int i)
{
int id = i / 2;
if (id < nr_packages)
return attr->mode;
return 0;
}
static struct attribute_group cpu_hwmon_group = {
.attrs = cpu_hwmon_attributes,
.is_visible = cpu_hwmon_is_visible,
};
static const struct attribute_group *cpu_hwmon_groups[] = {
&cpu_hwmon_group,
NULL
};
#define CPU_THERMAL_THRESHOLD 90000
static struct delayed_work thermal_work;
static void do_thermal_timer(struct work_struct *work)
{
int i, value;
MIPS: Loongson: Cleanup cpu_hwmon.c Fix the following checkpatch warnings and errors: ERROR: do not initialise statics to 0 +static int csr_temp_enable = 0; WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(name, S_IRUGO, get_hwmon_name, NULL, 0); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, get_cpu_temp, NULL, 1); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, cpu_temp_label, NULL, 1); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, get_cpu_temp, NULL, 2); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, cpu_temp_label, NULL, 2); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, get_cpu_temp, NULL, 3); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, cpu_temp_label, NULL, 3); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp4_input, S_IRUGO, get_cpu_temp, NULL, 4); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp4_label, S_IRUGO, cpu_temp_label, NULL, 4); WARNING: Missing a blank line after declarations + int id = (to_sensor_dev_attr(attr))->index - 1; + return sprintf(buf, "CPU %d Temperature\n", id); WARNING: Missing a blank line after declarations + int value = loongson3_cpu_temp(id); + return sprintf(buf, "%d\n", value); ERROR: spaces required around that '=' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '<' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '=' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '<' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '=' (ctx:VxV) + for (i=0; i<nr_packages; i++) { ^ ERROR: spaces required around that '<' (ctx:VxV) + for (i=0; i<nr_packages; i++) { ^ WARNING: line over 80 characters + csr_temp_enable = csr_readl(LOONGSON_CSR_FEATURES) & LOONGSON_CSRF_TEMP; Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Zhi Li <lizhi01@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-07-08 20:55:19 -07:00
for (i = 0; i < nr_packages; i++) {
value = loongson3_cpu_temp(i);
if (value > CPU_THERMAL_THRESHOLD) {
pr_emerg("Power off due to high temp: %d\n", value);
orderly_poweroff(true);
}
}
schedule_delayed_work(&thermal_work, msecs_to_jiffies(5000));
}
static int __init loongson_hwmon_init(void)
{
pr_info("Loongson Hwmon Enter...\n");
MIPS: Loongson: Add Loongson-3A R4 basic support All Loongson-3 CPU family: Code-name Brand-name PRId Loongson-3A R1 Loongson-3A1000 0x6305 Loongson-3A R2 Loongson-3A2000 0x6308 Loongson-3A R2.1 Loongson-3A2000 0x630c Loongson-3A R3 Loongson-3A3000 0x6309 Loongson-3A R3.1 Loongson-3A3000 0x630d Loongson-3A R4 Loongson-3A4000 0xc000 Loongson-3B R1 Loongson-3B1000 0x6306 Loongson-3B R2 Loongson-3B1500 0x6307 Features of R4 revision of Loongson-3A: - All R2/R3 features, including SFB, V-Cache, FTLB, RIXI, DSP, etc. - Support variable ASID bits. - Support MSA and VZ extensions. - Support CPUCFG (CPU config) and CSR (Control and Status Register) extensions. - 64 entries of VTLB (classic TLB), 2048 entries of FTLB (8-way set-associative). Now 64-bit Loongson processors has three types of PRID.IMP: 0x6300 is the classic one so we call it PRID_IMP_LOONGSON_64C (e.g., Loongson-2E/ 2F/3A1000/3B1000/3B1500/3A2000/3A3000), 0x6100 is for some processors which has reduced capabilities so we call it PRID_IMP_LOONGSON_64R (e.g., Loongson-2K), 0xc000 is supposed to cover all new processors in general (e.g., Loongson-3A4000+) so we call it PRID_IMP_LOONGSON_64G. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Cc: linux-mips@vger.kernel.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Huacai Chen <chenhuacai@gmail.com>
2019-09-21 06:50:27 -07:00
if (cpu_has_csr())
MIPS: Loongson: Cleanup cpu_hwmon.c Fix the following checkpatch warnings and errors: ERROR: do not initialise statics to 0 +static int csr_temp_enable = 0; WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(name, S_IRUGO, get_hwmon_name, NULL, 0); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, get_cpu_temp, NULL, 1); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, cpu_temp_label, NULL, 1); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, get_cpu_temp, NULL, 2); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, cpu_temp_label, NULL, 2); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, get_cpu_temp, NULL, 3); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, cpu_temp_label, NULL, 3); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp4_input, S_IRUGO, get_cpu_temp, NULL, 4); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp4_label, S_IRUGO, cpu_temp_label, NULL, 4); WARNING: Missing a blank line after declarations + int id = (to_sensor_dev_attr(attr))->index - 1; + return sprintf(buf, "CPU %d Temperature\n", id); WARNING: Missing a blank line after declarations + int value = loongson3_cpu_temp(id); + return sprintf(buf, "%d\n", value); ERROR: spaces required around that '=' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '<' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '=' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '<' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '=' (ctx:VxV) + for (i=0; i<nr_packages; i++) { ^ ERROR: spaces required around that '<' (ctx:VxV) + for (i=0; i<nr_packages; i++) { ^ WARNING: line over 80 characters + csr_temp_enable = csr_readl(LOONGSON_CSR_FEATURES) & LOONGSON_CSRF_TEMP; Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Zhi Li <lizhi01@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-07-08 20:55:19 -07:00
csr_temp_enable = csr_readl(LOONGSON_CSR_FEATURES) &
LOONGSON_CSRF_TEMP;
MIPS: Loongson: Add Loongson-3A R4 basic support All Loongson-3 CPU family: Code-name Brand-name PRId Loongson-3A R1 Loongson-3A1000 0x6305 Loongson-3A R2 Loongson-3A2000 0x6308 Loongson-3A R2.1 Loongson-3A2000 0x630c Loongson-3A R3 Loongson-3A3000 0x6309 Loongson-3A R3.1 Loongson-3A3000 0x630d Loongson-3A R4 Loongson-3A4000 0xc000 Loongson-3B R1 Loongson-3B1000 0x6306 Loongson-3B R2 Loongson-3B1500 0x6307 Features of R4 revision of Loongson-3A: - All R2/R3 features, including SFB, V-Cache, FTLB, RIXI, DSP, etc. - Support variable ASID bits. - Support MSA and VZ extensions. - Support CPUCFG (CPU config) and CSR (Control and Status Register) extensions. - 64 entries of VTLB (classic TLB), 2048 entries of FTLB (8-way set-associative). Now 64-bit Loongson processors has three types of PRID.IMP: 0x6300 is the classic one so we call it PRID_IMP_LOONGSON_64C (e.g., Loongson-2E/ 2F/3A1000/3B1000/3B1500/3A2000/3A3000), 0x6100 is for some processors which has reduced capabilities so we call it PRID_IMP_LOONGSON_64R (e.g., Loongson-2K), 0xc000 is supposed to cover all new processors in general (e.g., Loongson-3A4000+) so we call it PRID_IMP_LOONGSON_64G. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Cc: linux-mips@vger.kernel.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Huacai Chen <chenhuacai@gmail.com>
2019-09-21 06:50:27 -07:00
if (!csr_temp_enable && !loongson_chiptemp[0])
return -ENODEV;
nr_packages = loongson_sysconf.nr_cpus /
loongson_sysconf.cores_per_package;
cpu_hwmon_dev = hwmon_device_register_with_groups(NULL, "cpu_hwmon",
NULL, cpu_hwmon_groups);
if (IS_ERR(cpu_hwmon_dev)) {
pr_err("hwmon_device_register fail!\n");
return PTR_ERR(cpu_hwmon_dev);
}
INIT_DEFERRABLE_WORK(&thermal_work, do_thermal_timer);
schedule_delayed_work(&thermal_work, msecs_to_jiffies(20000));
return 0;
}
static void __exit loongson_hwmon_exit(void)
{
cancel_delayed_work_sync(&thermal_work);
hwmon_device_unregister(cpu_hwmon_dev);
}
module_init(loongson_hwmon_init);
module_exit(loongson_hwmon_exit);
MODULE_AUTHOR("Yu Xiang <xiangy@lemote.com>");
MODULE_AUTHOR("Huacai Chen <chenhc@lemote.com>");
MODULE_DESCRIPTION("Loongson CPU Hwmon driver");
MODULE_LICENSE("GPL");