2013-01-18 14:30:34 -07:00
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/*
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* Allwinner A1X SoCs pinctrl driver.
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*
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* Copyright (C) 2012 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __PINCTRL_SUNXI_H
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#define __PINCTRL_SUNXI_H
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#include <linux/kernel.h>
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2013-08-04 03:38:48 -07:00
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#include <linux/spinlock.h>
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2013-01-18 14:30:34 -07:00
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#define PA_BASE 0
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#define PB_BASE 32
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#define PC_BASE 64
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#define PD_BASE 96
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#define PE_BASE 128
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#define PF_BASE 160
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#define PG_BASE 192
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2013-01-26 07:36:53 -07:00
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#define PH_BASE 224
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#define PI_BASE 256
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2014-04-10 06:52:42 -07:00
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#define PL_BASE 352
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#define PM_BASE 384
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2014-10-28 14:41:26 -07:00
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#define PN_BASE 416
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2013-01-18 14:30:34 -07:00
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2014-04-24 07:06:52 -07:00
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#define SUNXI_PINCTRL_PIN(bank, pin) \
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PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
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2014-04-10 06:52:42 -07:00
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2013-01-28 13:33:12 -07:00
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#define SUNXI_PIN_NAME_MAX_LEN 5
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2013-01-18 14:30:34 -07:00
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#define BANK_MEM_SIZE 0x24
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#define MUX_REGS_OFFSET 0x0
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2022-07-12 19:52:31 -07:00
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#define MUX_FIELD_WIDTH 4
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2013-01-28 13:33:12 -07:00
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#define DATA_REGS_OFFSET 0x10
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2022-07-12 19:52:31 -07:00
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#define DATA_FIELD_WIDTH 1
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2013-01-18 14:30:34 -07:00
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#define DLEVEL_REGS_OFFSET 0x14
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2022-07-12 19:52:31 -07:00
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#define DLEVEL_FIELD_WIDTH 2
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2013-01-18 14:30:34 -07:00
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#define PULL_REGS_OFFSET 0x1c
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2022-07-12 19:52:31 -07:00
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#define PULL_FIELD_WIDTH 2
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2013-01-18 14:30:34 -07:00
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2022-07-12 19:52:33 -07:00
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#define D1_BANK_MEM_SIZE 0x30
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#define D1_DLEVEL_FIELD_WIDTH 4
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#define D1_PULL_REGS_OFFSET 0x24
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2013-01-18 14:30:34 -07:00
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#define PINS_PER_BANK 32
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2014-06-05 06:26:04 -07:00
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#define IRQ_PER_BANK 32
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2013-06-08 03:05:44 -07:00
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#define IRQ_CFG_REG 0x200
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#define IRQ_CFG_IRQ_PER_REG 8
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#define IRQ_CFG_IRQ_BITS 4
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#define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)
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#define IRQ_CTRL_REG 0x210
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#define IRQ_CTRL_IRQ_PER_REG 32
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#define IRQ_CTRL_IRQ_BITS 1
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#define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)
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#define IRQ_STATUS_REG 0x214
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#define IRQ_STATUS_IRQ_PER_REG 32
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#define IRQ_STATUS_IRQ_BITS 1
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#define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
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2016-11-14 13:53:03 -07:00
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#define IRQ_DEBOUNCE_REG 0x218
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2014-06-05 06:26:04 -07:00
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#define IRQ_MEM_SIZE 0x20
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2013-06-08 03:05:44 -07:00
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#define IRQ_EDGE_RISING 0x00
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#define IRQ_EDGE_FALLING 0x01
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#define IRQ_LEVEL_HIGH 0x02
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#define IRQ_LEVEL_LOW 0x03
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#define IRQ_EDGE_BOTH 0x04
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2019-02-05 20:32:31 -07:00
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#define GRP_CFG_REG 0x300
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#define IO_BIAS_MASK GENMASK(3, 0)
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2015-03-08 14:13:57 -07:00
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#define SUN4I_FUNC_INPUT 0
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#define SUN4I_FUNC_IRQ 6
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2017-01-08 14:31:16 -07:00
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#define PINCTRL_SUN5I_A10S BIT(1)
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#define PINCTRL_SUN5I_A13 BIT(2)
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#define PINCTRL_SUN5I_GR8 BIT(3)
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2017-02-01 09:25:46 -07:00
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#define PINCTRL_SUN6I_A31 BIT(4)
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#define PINCTRL_SUN6I_A31S BIT(5)
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2017-05-27 03:23:00 -07:00
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#define PINCTRL_SUN4I_A10 BIT(6)
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#define PINCTRL_SUN7I_A20 BIT(7)
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#define PINCTRL_SUN8I_R40 BIT(8)
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2019-07-27 20:12:22 -07:00
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#define PINCTRL_SUN8I_V3 BIT(9)
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#define PINCTRL_SUN8I_V3S BIT(10)
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2022-07-12 19:52:33 -07:00
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/* Variants below here have an updated register layout. */
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#define PINCTRL_SUN20I_D1 BIT(11)
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2017-01-08 14:31:16 -07:00
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2019-04-13 09:54:13 -07:00
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#define PIO_POW_MOD_SEL_REG 0x340
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2022-07-12 19:52:30 -07:00
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#define PIO_POW_MOD_CTL_REG 0x344
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2019-04-13 09:54:13 -07:00
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2019-04-13 09:54:12 -07:00
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enum sunxi_desc_bias_voltage {
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BIAS_VOLTAGE_NONE,
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/*
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* Bias voltage configuration is done through
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* Pn_GRP_CONFIG registers, as seen on A80 SoC.
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*/
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BIAS_VOLTAGE_GRP_CONFIG,
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2019-04-13 09:54:13 -07:00
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/*
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* Bias voltage is set through PIO_POW_MOD_SEL_REG
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* register, as seen on H6 SoC, for example.
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*/
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BIAS_VOLTAGE_PIO_POW_MODE_SEL,
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2022-07-12 19:52:30 -07:00
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/*
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* Bias voltage is set through PIO_POW_MOD_SEL_REG
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* and PIO_POW_MOD_CTL_REG register, as seen on
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* A100 and D1 SoC, for example.
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*/
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BIAS_VOLTAGE_PIO_POW_MODE_CTL,
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2019-04-13 09:54:12 -07:00
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};
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2013-01-18 14:30:34 -07:00
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struct sunxi_desc_function {
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2017-01-08 14:31:15 -07:00
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unsigned long variant;
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2013-01-18 14:30:34 -07:00
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const char *name;
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u8 muxval;
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2014-06-05 06:26:01 -07:00
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u8 irqbank;
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2013-06-08 03:05:44 -07:00
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u8 irqnum;
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2013-01-18 14:30:34 -07:00
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};
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struct sunxi_desc_pin {
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struct pinctrl_pin_desc pin;
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2017-01-08 14:31:15 -07:00
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unsigned long variant;
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2013-01-18 14:30:34 -07:00
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struct sunxi_desc_function *functions;
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};
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struct sunxi_pinctrl_desc {
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const struct sunxi_desc_pin *pins;
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int npins;
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2014-04-10 06:52:43 -07:00
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unsigned pin_base;
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2014-06-05 06:26:02 -07:00
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unsigned irq_banks;
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2018-03-16 07:02:09 -07:00
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const unsigned int *irq_bank_map;
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2015-03-08 14:13:57 -07:00
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bool irq_read_needs_mux;
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2017-10-09 13:53:37 -07:00
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bool disable_strict_mode;
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2019-04-13 09:54:12 -07:00
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enum sunxi_desc_bias_voltage io_bias_cfg_variant;
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2013-01-18 14:30:34 -07:00
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};
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struct sunxi_pinctrl_function {
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const char *name;
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const char **groups;
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unsigned ngroups;
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};
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struct sunxi_pinctrl_group {
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const char *name;
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unsigned pin;
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};
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pinctrl: sunxi: Deal with per-bank regulators
The Allwinner SoCs have on most of their GPIO banks a regulator input.
This issue was mainly ignored so far because either the regulator was a
static regulator that would be providing power anyway, or the bank was used
for a feature unsupported so far (CSI). For the odd cases, enabling it in
the bootloader was the preferred option.
However, now that we are starting to support those features, and that we
can't really rely on the bootloader for this, we need to model those
regulators as such in the DT.
This is slightly more complicated than what it looks like, since some
regulators will be tied to the PMIC, and in order to have access to the
PMIC bus, you need to mux its pins, which will need the pinctrl driver,
that needs the regulator driver to be registered. And this is how you get a
circular dependency.
In practice however, the hardware cannot fall into this case since it would
result in a completely unusable bus. In order to avoid that circular
dependency, we can thus get and enable the regulators at pin_request time.
We'll then need to account for the references of all the pins of a
particular branch to know when to put the reference, but it works pretty
nicely once implemented.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-12-06 07:02:03 -07:00
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struct sunxi_pinctrl_regulator {
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struct regulator *regulator;
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refcount_t refcount;
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};
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2013-01-18 14:30:34 -07:00
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struct sunxi_pinctrl {
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void __iomem *membase;
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2013-01-28 13:33:12 -07:00
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struct gpio_chip *chip;
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2014-04-18 10:34:07 -07:00
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const struct sunxi_pinctrl_desc *desc;
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2013-01-18 14:30:34 -07:00
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struct device *dev;
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pinctrl: sunxi: Consider pin_base when calculating regulator array index
On most newer Allwinner SoCs, there are two pinctrl devices, the PIO and
R_PIO. PIO covers pin-banks PA to PI (PJ and PK have not been seen),
while R_PIO covers PL to PN. The regulator array only has space for 12
entries, which was designed to cover PA to PL. On the A80, the pin banks
go up to PN, which would be the 14th entry in the regulator array.
However since the driver only needs to track regulators for its own pin
banks, the array only needs to have 9 entries, and also take in to
account the value of pin_base, such that the regulator for the first
pin-bank of the pinctrl device, be it "PA" or "PL" uses the first entry
of the array.
Base the regulator array index on pin_base, such that "PA" for PIO and
"PL" for R_PIO both take the first element within their respective
device's regulator array.
Also decrease the size of the regulator array to 9, just enough to cover
"PA" to "PI".
Fixes: 9a2a566adb00 ("pinctrl: sunxi: Deal with per-bank regulators")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-01-13 02:57:23 -07:00
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struct sunxi_pinctrl_regulator regulators[9];
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2013-06-08 03:05:44 -07:00
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struct irq_domain *domain;
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2013-01-18 14:30:34 -07:00
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struct sunxi_pinctrl_function *functions;
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unsigned nfunctions;
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struct sunxi_pinctrl_group *groups;
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unsigned ngroups;
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2014-06-05 06:26:04 -07:00
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int *irq;
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unsigned *irq_array;
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2017-03-09 09:22:06 -07:00
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raw_spinlock_t lock;
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2013-01-18 14:30:34 -07:00
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struct pinctrl_dev *pctl_dev;
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2017-01-08 14:31:15 -07:00
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unsigned long variant;
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2022-07-12 19:52:32 -07:00
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u32 bank_mem_size;
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u32 pull_regs_offset;
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u32 dlevel_field_width;
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2013-01-18 14:30:34 -07:00
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};
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#define SUNXI_PIN(_pin, ...) \
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{ \
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.pin = _pin, \
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.functions = (struct sunxi_desc_function[]){ \
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__VA_ARGS__, { } }, \
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}
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2017-01-08 14:31:15 -07:00
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#define SUNXI_PIN_VARIANT(_pin, _variant, ...) \
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{ \
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.pin = _pin, \
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.variant = _variant, \
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.functions = (struct sunxi_desc_function[]){ \
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__VA_ARGS__, { } }, \
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}
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2013-01-18 14:30:34 -07:00
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#define SUNXI_FUNCTION(_val, _name) \
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{ \
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.name = _name, \
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.muxval = _val, \
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}
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2017-01-08 14:31:15 -07:00
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#define SUNXI_FUNCTION_VARIANT(_val, _name, _variant) \
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{ \
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.name = _name, \
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.muxval = _val, \
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.variant = _variant, \
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}
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2013-06-08 03:05:44 -07:00
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#define SUNXI_FUNCTION_IRQ(_val, _irq) \
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{ \
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.name = "irq", \
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.muxval = _val, \
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.irqnum = _irq, \
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}
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2014-06-05 06:26:01 -07:00
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#define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \
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{ \
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.name = "irq", \
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.muxval = _val, \
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.irqbank = _bank, \
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.irqnum = _irq, \
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}
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2018-03-16 07:02:08 -07:00
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static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank)
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{
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2018-03-16 07:02:09 -07:00
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if (!desc->irq_bank_map)
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return bank;
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else
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return desc->irq_bank_map[bank];
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2018-03-16 07:02:08 -07:00
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}
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2018-03-16 07:02:07 -07:00
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static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc *desc,
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u16 irq)
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2013-06-08 03:05:44 -07:00
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{
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2014-06-05 06:26:04 -07:00
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u8 bank = irq / IRQ_PER_BANK;
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u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;
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2018-03-16 07:02:08 -07:00
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return IRQ_CFG_REG +
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sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg;
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2013-06-08 03:05:44 -07:00
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}
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static inline u32 sunxi_irq_cfg_offset(u16 irq)
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{
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u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
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return irq_num * IRQ_CFG_IRQ_BITS;
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}
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2018-03-16 07:02:07 -07:00
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static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
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2014-06-05 06:26:04 -07:00
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{
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2018-03-16 07:02:08 -07:00
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return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
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2014-06-05 06:26:04 -07:00
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}
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2018-03-16 07:02:07 -07:00
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static inline u32 sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc *desc,
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u16 irq)
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2013-06-08 03:05:44 -07:00
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{
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2014-06-05 06:26:04 -07:00
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u8 bank = irq / IRQ_PER_BANK;
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2018-03-16 07:02:07 -07:00
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return sunxi_irq_ctrl_reg_from_bank(desc, bank);
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2013-06-08 03:05:44 -07:00
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}
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static inline u32 sunxi_irq_ctrl_offset(u16 irq)
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{
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u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
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return irq_num * IRQ_CTRL_IRQ_BITS;
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}
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2018-03-16 07:02:07 -07:00
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static inline u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
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2016-11-14 13:53:03 -07:00
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{
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2018-03-16 07:02:08 -07:00
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return IRQ_DEBOUNCE_REG +
|
|
|
|
sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
|
2016-11-14 13:53:03 -07:00
|
|
|
}
|
|
|
|
|
2018-03-16 07:02:07 -07:00
|
|
|
static inline u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
|
2014-06-05 06:26:04 -07:00
|
|
|
{
|
2018-03-16 07:02:08 -07:00
|
|
|
return IRQ_STATUS_REG +
|
|
|
|
sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
|
2014-06-05 06:26:04 -07:00
|
|
|
}
|
|
|
|
|
2018-03-16 07:02:07 -07:00
|
|
|
static inline u32 sunxi_irq_status_reg(const struct sunxi_pinctrl_desc *desc,
|
|
|
|
u16 irq)
|
2013-06-08 03:05:44 -07:00
|
|
|
{
|
2014-06-05 06:26:04 -07:00
|
|
|
u8 bank = irq / IRQ_PER_BANK;
|
|
|
|
|
2018-03-16 07:02:07 -07:00
|
|
|
return sunxi_irq_status_reg_from_bank(desc, bank);
|
2013-06-08 03:05:44 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline u32 sunxi_irq_status_offset(u16 irq)
|
|
|
|
{
|
|
|
|
u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
|
|
|
|
return irq_num * IRQ_STATUS_IRQ_BITS;
|
|
|
|
}
|
|
|
|
|
2019-02-05 20:32:31 -07:00
|
|
|
static inline u32 sunxi_grp_config_reg(u16 pin)
|
|
|
|
{
|
|
|
|
u8 bank = pin / PINS_PER_BANK;
|
|
|
|
|
|
|
|
return GRP_CFG_REG + bank * 0x4;
|
|
|
|
}
|
|
|
|
|
2017-01-08 14:31:15 -07:00
|
|
|
int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
|
|
|
|
const struct sunxi_pinctrl_desc *desc,
|
|
|
|
unsigned long variant);
|
|
|
|
|
|
|
|
#define sunxi_pinctrl_init(_dev, _desc) \
|
|
|
|
sunxi_pinctrl_init_with_variant(_dev, _desc, 0)
|
2014-04-18 11:10:41 -07:00
|
|
|
|
2013-01-18 14:30:34 -07:00
|
|
|
#endif /* __PINCTRL_SUNXI_H */
|