2018-05-19 11:43:54 -07:00
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// SPDX-License-Identifier: GPL-2.0
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//
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// Freescale imx7d pinctrl driver
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//
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// Author: Anson Huang <Anson.Huang@freescale.com>
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// Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
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2015-04-29 07:20:05 -07:00
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/of.h>
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2023-07-14 10:48:54 -07:00
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#include <linux/platform_device.h>
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2015-04-29 07:20:05 -07:00
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-imx.h"
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enum imx7d_pads {
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MX7D_PAD_RESERVE0 = 0,
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MX7D_PAD_RESERVE1 = 1,
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MX7D_PAD_RESERVE2 = 2,
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MX7D_PAD_RESERVE3 = 3,
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MX7D_PAD_RESERVE4 = 4,
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MX7D_PAD_GPIO1_IO08 = 5,
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MX7D_PAD_GPIO1_IO09 = 6,
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MX7D_PAD_GPIO1_IO10 = 7,
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MX7D_PAD_GPIO1_IO11 = 8,
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MX7D_PAD_GPIO1_IO12 = 9,
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MX7D_PAD_GPIO1_IO13 = 10,
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MX7D_PAD_GPIO1_IO14 = 11,
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MX7D_PAD_GPIO1_IO15 = 12,
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MX7D_PAD_EPDC_DATA00 = 13,
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MX7D_PAD_EPDC_DATA01 = 14,
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MX7D_PAD_EPDC_DATA02 = 15,
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MX7D_PAD_EPDC_DATA03 = 16,
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MX7D_PAD_EPDC_DATA04 = 17,
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MX7D_PAD_EPDC_DATA05 = 18,
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MX7D_PAD_EPDC_DATA06 = 19,
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MX7D_PAD_EPDC_DATA07 = 20,
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MX7D_PAD_EPDC_DATA08 = 21,
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MX7D_PAD_EPDC_DATA09 = 22,
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MX7D_PAD_EPDC_DATA10 = 23,
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MX7D_PAD_EPDC_DATA11 = 24,
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MX7D_PAD_EPDC_DATA12 = 25,
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MX7D_PAD_EPDC_DATA13 = 26,
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MX7D_PAD_EPDC_DATA14 = 27,
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MX7D_PAD_EPDC_DATA15 = 28,
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MX7D_PAD_EPDC_SDCLK = 29,
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MX7D_PAD_EPDC_SDLE = 30,
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MX7D_PAD_EPDC_SDOE = 31,
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MX7D_PAD_EPDC_SDSHR = 32,
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MX7D_PAD_EPDC_SDCE0 = 33,
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MX7D_PAD_EPDC_SDCE1 = 34,
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MX7D_PAD_EPDC_SDCE2 = 35,
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MX7D_PAD_EPDC_SDCE3 = 36,
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MX7D_PAD_EPDC_GDCLK = 37,
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MX7D_PAD_EPDC_GDOE = 38,
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MX7D_PAD_EPDC_GDRL = 39,
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MX7D_PAD_EPDC_GDSP = 40,
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MX7D_PAD_EPDC_BDR0 = 41,
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MX7D_PAD_EPDC_BDR1 = 42,
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MX7D_PAD_EPDC_PWR_COM = 43,
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MX7D_PAD_EPDC_PWR_STAT = 44,
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MX7D_PAD_LCD_CLK = 45,
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MX7D_PAD_LCD_ENABLE = 46,
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MX7D_PAD_LCD_HSYNC = 47,
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MX7D_PAD_LCD_VSYNC = 48,
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MX7D_PAD_LCD_RESET = 49,
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MX7D_PAD_LCD_DATA00 = 50,
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MX7D_PAD_LCD_DATA01 = 51,
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MX7D_PAD_LCD_DATA02 = 52,
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MX7D_PAD_LCD_DATA03 = 53,
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MX7D_PAD_LCD_DATA04 = 54,
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MX7D_PAD_LCD_DATA05 = 55,
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MX7D_PAD_LCD_DATA06 = 56,
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MX7D_PAD_LCD_DATA07 = 57,
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MX7D_PAD_LCD_DATA08 = 58,
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MX7D_PAD_LCD_DATA09 = 59,
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MX7D_PAD_LCD_DATA10 = 60,
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MX7D_PAD_LCD_DATA11 = 61,
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MX7D_PAD_LCD_DATA12 = 62,
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MX7D_PAD_LCD_DATA13 = 63,
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MX7D_PAD_LCD_DATA14 = 64,
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MX7D_PAD_LCD_DATA15 = 65,
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MX7D_PAD_LCD_DATA16 = 66,
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MX7D_PAD_LCD_DATA17 = 67,
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MX7D_PAD_LCD_DATA18 = 68,
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MX7D_PAD_LCD_DATA19 = 69,
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MX7D_PAD_LCD_DATA20 = 70,
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MX7D_PAD_LCD_DATA21 = 71,
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MX7D_PAD_LCD_DATA22 = 72,
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MX7D_PAD_LCD_DATA23 = 73,
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MX7D_PAD_UART1_RX_DATA = 74,
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MX7D_PAD_UART1_TX_DATA = 75,
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MX7D_PAD_UART2_RX_DATA = 76,
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MX7D_PAD_UART2_TX_DATA = 77,
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MX7D_PAD_UART3_RX_DATA = 78,
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MX7D_PAD_UART3_TX_DATA = 79,
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MX7D_PAD_UART3_RTS_B = 80,
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MX7D_PAD_UART3_CTS_B = 81,
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MX7D_PAD_I2C1_SCL = 82,
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MX7D_PAD_I2C1_SDA = 83,
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MX7D_PAD_I2C2_SCL = 84,
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MX7D_PAD_I2C2_SDA = 85,
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MX7D_PAD_I2C3_SCL = 86,
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MX7D_PAD_I2C3_SDA = 87,
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MX7D_PAD_I2C4_SCL = 88,
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MX7D_PAD_I2C4_SDA = 89,
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MX7D_PAD_ECSPI1_SCLK = 90,
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MX7D_PAD_ECSPI1_MOSI = 91,
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MX7D_PAD_ECSPI1_MISO = 92,
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MX7D_PAD_ECSPI1_SS0 = 93,
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MX7D_PAD_ECSPI2_SCLK = 94,
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MX7D_PAD_ECSPI2_MOSI = 95,
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MX7D_PAD_ECSPI2_MISO = 96,
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MX7D_PAD_ECSPI2_SS0 = 97,
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MX7D_PAD_SD1_CD_B = 98,
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MX7D_PAD_SD1_WP = 99,
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MX7D_PAD_SD1_RESET_B = 100,
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MX7D_PAD_SD1_CLK = 101,
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MX7D_PAD_SD1_CMD = 102,
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MX7D_PAD_SD1_DATA0 = 103,
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MX7D_PAD_SD1_DATA1 = 104,
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MX7D_PAD_SD1_DATA2 = 105,
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MX7D_PAD_SD1_DATA3 = 106,
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MX7D_PAD_SD2_CD_B = 107,
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MX7D_PAD_SD2_WP = 108,
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MX7D_PAD_SD2_RESET_B = 109,
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MX7D_PAD_SD2_CLK = 110,
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MX7D_PAD_SD2_CMD = 111,
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MX7D_PAD_SD2_DATA0 = 112,
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MX7D_PAD_SD2_DATA1 = 113,
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MX7D_PAD_SD2_DATA2 = 114,
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MX7D_PAD_SD2_DATA3 = 115,
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MX7D_PAD_SD3_CLK = 116,
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MX7D_PAD_SD3_CMD = 117,
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MX7D_PAD_SD3_DATA0 = 118,
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MX7D_PAD_SD3_DATA1 = 119,
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MX7D_PAD_SD3_DATA2 = 120,
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MX7D_PAD_SD3_DATA3 = 121,
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MX7D_PAD_SD3_DATA4 = 122,
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MX7D_PAD_SD3_DATA5 = 123,
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MX7D_PAD_SD3_DATA6 = 124,
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MX7D_PAD_SD3_DATA7 = 125,
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MX7D_PAD_SD3_STROBE = 126,
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MX7D_PAD_SD3_RESET_B = 127,
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MX7D_PAD_SAI1_RX_DATA = 128,
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MX7D_PAD_SAI1_TX_BCLK = 129,
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MX7D_PAD_SAI1_TX_SYNC = 130,
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MX7D_PAD_SAI1_TX_DATA = 131,
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MX7D_PAD_SAI1_RX_SYNC = 132,
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MX7D_PAD_SAI1_RX_BCLK = 133,
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MX7D_PAD_SAI1_MCLK = 134,
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MX7D_PAD_SAI2_TX_SYNC = 135,
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MX7D_PAD_SAI2_TX_BCLK = 136,
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MX7D_PAD_SAI2_RX_DATA = 137,
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MX7D_PAD_SAI2_TX_DATA = 138,
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MX7D_PAD_ENET1_RGMII_RD0 = 139,
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MX7D_PAD_ENET1_RGMII_RD1 = 140,
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MX7D_PAD_ENET1_RGMII_RD2 = 141,
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MX7D_PAD_ENET1_RGMII_RD3 = 142,
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MX7D_PAD_ENET1_RGMII_RX_CTL = 143,
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MX7D_PAD_ENET1_RGMII_RXC = 144,
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MX7D_PAD_ENET1_RGMII_TD0 = 145,
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MX7D_PAD_ENET1_RGMII_TD1 = 146,
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MX7D_PAD_ENET1_RGMII_TD2 = 147,
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MX7D_PAD_ENET1_RGMII_TD3 = 148,
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MX7D_PAD_ENET1_RGMII_TX_CTL = 149,
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MX7D_PAD_ENET1_RGMII_TXC = 150,
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MX7D_PAD_ENET1_TX_CLK = 151,
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MX7D_PAD_ENET1_RX_CLK = 152,
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MX7D_PAD_ENET1_CRS = 153,
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MX7D_PAD_ENET1_COL = 154,
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};
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2015-09-30 09:11:08 -07:00
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enum imx7d_lpsr_pads {
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MX7D_PAD_GPIO1_IO00 = 0,
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MX7D_PAD_GPIO1_IO01 = 1,
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MX7D_PAD_GPIO1_IO02 = 2,
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MX7D_PAD_GPIO1_IO03 = 3,
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MX7D_PAD_GPIO1_IO04 = 4,
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MX7D_PAD_GPIO1_IO05 = 5,
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MX7D_PAD_GPIO1_IO06 = 6,
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MX7D_PAD_GPIO1_IO07 = 7,
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};
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2015-04-29 07:20:05 -07:00
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/* Pad names for the pinmux subsystem */
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static const struct pinctrl_pin_desc imx7d_pinctrl_pads[] = {
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IMX_PINCTRL_PIN(MX7D_PAD_RESERVE0),
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IMX_PINCTRL_PIN(MX7D_PAD_RESERVE1),
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IMX_PINCTRL_PIN(MX7D_PAD_RESERVE2),
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IMX_PINCTRL_PIN(MX7D_PAD_RESERVE3),
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IMX_PINCTRL_PIN(MX7D_PAD_RESERVE4),
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IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO08),
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IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO09),
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IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO10),
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IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO11),
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IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO12),
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IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO13),
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IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO14),
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IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO15),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA00),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA01),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA02),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA03),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA04),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA05),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA06),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA07),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA08),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA09),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA10),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA11),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA12),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA13),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA14),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA15),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCLK),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDLE),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDOE),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDSHR),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCE0),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCE1),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCE2),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCE3),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_GDCLK),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_GDOE),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_GDRL),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_GDSP),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_BDR0),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_BDR1),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_PWR_COM),
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IMX_PINCTRL_PIN(MX7D_PAD_EPDC_PWR_STAT),
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IMX_PINCTRL_PIN(MX7D_PAD_LCD_CLK),
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IMX_PINCTRL_PIN(MX7D_PAD_LCD_ENABLE),
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IMX_PINCTRL_PIN(MX7D_PAD_LCD_HSYNC),
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IMX_PINCTRL_PIN(MX7D_PAD_LCD_VSYNC),
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IMX_PINCTRL_PIN(MX7D_PAD_LCD_RESET),
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IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA00),
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IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA01),
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IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA02),
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IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA03),
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IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA04),
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IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA05),
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IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA06),
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IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA07),
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IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA08),
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IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA09),
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IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA10),
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IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA11),
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IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA12),
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IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA13),
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IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA14),
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IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA15),
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IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA16),
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IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA17),
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IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA18),
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IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA19),
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IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA20),
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IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA21),
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IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA22),
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IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA23),
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IMX_PINCTRL_PIN(MX7D_PAD_UART1_RX_DATA),
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IMX_PINCTRL_PIN(MX7D_PAD_UART1_TX_DATA),
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IMX_PINCTRL_PIN(MX7D_PAD_UART2_RX_DATA),
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IMX_PINCTRL_PIN(MX7D_PAD_UART2_TX_DATA),
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IMX_PINCTRL_PIN(MX7D_PAD_UART3_RX_DATA),
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IMX_PINCTRL_PIN(MX7D_PAD_UART3_TX_DATA),
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IMX_PINCTRL_PIN(MX7D_PAD_UART3_RTS_B),
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IMX_PINCTRL_PIN(MX7D_PAD_UART3_CTS_B),
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IMX_PINCTRL_PIN(MX7D_PAD_I2C1_SCL),
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IMX_PINCTRL_PIN(MX7D_PAD_I2C1_SDA),
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IMX_PINCTRL_PIN(MX7D_PAD_I2C2_SCL),
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IMX_PINCTRL_PIN(MX7D_PAD_I2C2_SDA),
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IMX_PINCTRL_PIN(MX7D_PAD_I2C3_SCL),
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IMX_PINCTRL_PIN(MX7D_PAD_I2C3_SDA),
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IMX_PINCTRL_PIN(MX7D_PAD_I2C4_SCL),
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IMX_PINCTRL_PIN(MX7D_PAD_I2C4_SDA),
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IMX_PINCTRL_PIN(MX7D_PAD_ECSPI1_SCLK),
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IMX_PINCTRL_PIN(MX7D_PAD_ECSPI1_MOSI),
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IMX_PINCTRL_PIN(MX7D_PAD_ECSPI1_MISO),
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IMX_PINCTRL_PIN(MX7D_PAD_ECSPI1_SS0),
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IMX_PINCTRL_PIN(MX7D_PAD_ECSPI2_SCLK),
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IMX_PINCTRL_PIN(MX7D_PAD_ECSPI2_MOSI),
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IMX_PINCTRL_PIN(MX7D_PAD_ECSPI2_MISO),
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IMX_PINCTRL_PIN(MX7D_PAD_ECSPI2_SS0),
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IMX_PINCTRL_PIN(MX7D_PAD_SD1_CD_B),
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IMX_PINCTRL_PIN(MX7D_PAD_SD1_WP),
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IMX_PINCTRL_PIN(MX7D_PAD_SD1_RESET_B),
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IMX_PINCTRL_PIN(MX7D_PAD_SD1_CLK),
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IMX_PINCTRL_PIN(MX7D_PAD_SD1_CMD),
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IMX_PINCTRL_PIN(MX7D_PAD_SD1_DATA0),
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IMX_PINCTRL_PIN(MX7D_PAD_SD1_DATA1),
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IMX_PINCTRL_PIN(MX7D_PAD_SD1_DATA2),
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IMX_PINCTRL_PIN(MX7D_PAD_SD1_DATA3),
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IMX_PINCTRL_PIN(MX7D_PAD_SD2_CD_B),
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IMX_PINCTRL_PIN(MX7D_PAD_SD2_WP),
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IMX_PINCTRL_PIN(MX7D_PAD_SD2_RESET_B),
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IMX_PINCTRL_PIN(MX7D_PAD_SD2_CLK),
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IMX_PINCTRL_PIN(MX7D_PAD_SD2_CMD),
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IMX_PINCTRL_PIN(MX7D_PAD_SD2_DATA0),
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IMX_PINCTRL_PIN(MX7D_PAD_SD2_DATA1),
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IMX_PINCTRL_PIN(MX7D_PAD_SD2_DATA2),
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IMX_PINCTRL_PIN(MX7D_PAD_SD2_DATA3),
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IMX_PINCTRL_PIN(MX7D_PAD_SD3_CLK),
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IMX_PINCTRL_PIN(MX7D_PAD_SD3_CMD),
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IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA0),
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IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA1),
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IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA2),
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IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA3),
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IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA4),
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IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA5),
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IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA6),
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IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA7),
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IMX_PINCTRL_PIN(MX7D_PAD_SD3_STROBE),
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IMX_PINCTRL_PIN(MX7D_PAD_SD3_RESET_B),
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IMX_PINCTRL_PIN(MX7D_PAD_SAI1_RX_DATA),
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IMX_PINCTRL_PIN(MX7D_PAD_SAI1_TX_BCLK),
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IMX_PINCTRL_PIN(MX7D_PAD_SAI1_TX_SYNC),
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IMX_PINCTRL_PIN(MX7D_PAD_SAI1_TX_DATA),
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IMX_PINCTRL_PIN(MX7D_PAD_SAI1_RX_SYNC),
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IMX_PINCTRL_PIN(MX7D_PAD_SAI1_RX_BCLK),
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IMX_PINCTRL_PIN(MX7D_PAD_SAI1_MCLK),
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IMX_PINCTRL_PIN(MX7D_PAD_SAI2_TX_SYNC),
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IMX_PINCTRL_PIN(MX7D_PAD_SAI2_TX_BCLK),
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IMX_PINCTRL_PIN(MX7D_PAD_SAI2_RX_DATA),
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IMX_PINCTRL_PIN(MX7D_PAD_SAI2_TX_DATA),
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IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RD0),
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IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RD1),
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IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RD2),
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IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RD3),
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IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RX_CTL),
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|
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IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RXC),
|
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|
|
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IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TD0),
|
|
|
|
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IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TD1),
|
|
|
|
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IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TD2),
|
|
|
|
|
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TD3),
|
|
|
|
|
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TX_CTL),
|
|
|
|
|
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TXC),
|
|
|
|
|
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_TX_CLK),
|
|
|
|
|
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RX_CLK),
|
|
|
|
|
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_CRS),
|
|
|
|
|
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_COL),
|
|
|
|
|
};
|
|
|
|
|
|
2015-09-30 09:11:08 -07:00
|
|
|
/* Pad names for the pinmux subsystem */
|
|
|
|
|
static const struct pinctrl_pin_desc imx7d_lpsr_pinctrl_pads[] = {
|
|
|
|
|
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO00),
|
|
|
|
|
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO01),
|
|
|
|
|
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO02),
|
|
|
|
|
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO03),
|
|
|
|
|
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO04),
|
|
|
|
|
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO05),
|
|
|
|
|
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO06),
|
|
|
|
|
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO07),
|
|
|
|
|
};
|
|
|
|
|
|
2017-06-27 04:55:21 -07:00
|
|
|
static const struct imx_pinctrl_soc_info imx7d_pinctrl_info = {
|
2015-04-29 07:20:05 -07:00
|
|
|
.pins = imx7d_pinctrl_pads,
|
|
|
|
|
.npins = ARRAY_SIZE(imx7d_pinctrl_pads),
|
2016-02-25 10:23:07 -07:00
|
|
|
.gpr_compatible = "fsl,imx7d-iomuxc-gpr",
|
2015-04-29 07:20:05 -07:00
|
|
|
};
|
|
|
|
|
|
2017-06-27 04:55:21 -07:00
|
|
|
static const struct imx_pinctrl_soc_info imx7d_lpsr_pinctrl_info = {
|
2015-09-30 09:11:08 -07:00
|
|
|
.pins = imx7d_lpsr_pinctrl_pads,
|
|
|
|
|
.npins = ARRAY_SIZE(imx7d_lpsr_pinctrl_pads),
|
|
|
|
|
.flags = ZERO_OFFSET_VALID,
|
|
|
|
|
};
|
|
|
|
|
|
2017-06-27 04:55:21 -07:00
|
|
|
static const struct of_device_id imx7d_pinctrl_of_match[] = {
|
2015-04-29 07:20:05 -07:00
|
|
|
{ .compatible = "fsl,imx7d-iomuxc", .data = &imx7d_pinctrl_info, },
|
2015-09-30 09:11:08 -07:00
|
|
|
{ .compatible = "fsl,imx7d-iomuxc-lpsr", .data = &imx7d_lpsr_pinctrl_info },
|
2015-04-29 07:20:05 -07:00
|
|
|
{ /* sentinel */ }
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int imx7d_pinctrl_probe(struct platform_device *pdev)
|
|
|
|
|
{
|
2018-01-06 07:25:50 -07:00
|
|
|
const struct imx_pinctrl_soc_info *pinctrl_info;
|
2015-04-29 07:20:05 -07:00
|
|
|
|
2018-01-06 07:25:50 -07:00
|
|
|
pinctrl_info = of_device_get_match_data(&pdev->dev);
|
|
|
|
|
if (!pinctrl_info)
|
2015-04-29 07:20:05 -07:00
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
|
|
return imx_pinctrl_probe(pdev, pinctrl_info);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct platform_driver imx7d_pinctrl_driver = {
|
|
|
|
|
.driver = {
|
|
|
|
|
.name = "imx7d-pinctrl",
|
2021-03-28 11:30:33 -07:00
|
|
|
.of_match_table = imx7d_pinctrl_of_match,
|
2021-03-28 11:30:34 -07:00
|
|
|
.suppress_bind_attrs = true,
|
2015-04-29 07:20:05 -07:00
|
|
|
},
|
|
|
|
|
.probe = imx7d_pinctrl_probe,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int __init imx7d_pinctrl_init(void)
|
|
|
|
|
{
|
|
|
|
|
return platform_driver_register(&imx7d_pinctrl_driver);
|
|
|
|
|
}
|
|
|
|
|
arch_initcall(imx7d_pinctrl_init);
|
