2019-05-29 07:18:13 -07:00
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// SPDX-License-Identifier: GPL-2.0-only
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2021-03-21 05:30:07 -07:00
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/*
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2012-05-14 04:06:20 -07:00
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* SHA-256 routines supporting the Power 7+ Nest Accelerators driver
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*
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* Copyright (C) 2011-2012 International Business Machines Inc.
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*
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* Author: Kent Yoder <yoder1@us.ibm.com>
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*/
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#include <crypto/internal/hash.h>
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2020-11-12 22:20:21 -07:00
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#include <crypto/sha2.h>
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2012-05-14 04:06:20 -07:00
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#include <linux/module.h>
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#include <asm/vio.h>
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2014-10-28 10:49:46 -07:00
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#include <asm/byteorder.h>
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2012-05-14 04:06:20 -07:00
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#include "nx_csbcpb.h"
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#include "nx.h"
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2021-06-17 01:00:12 -07:00
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struct sha256_state_be {
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__be32 state[SHA256_DIGEST_SIZE / 4];
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u64 count;
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u8 buf[SHA256_BLOCK_SIZE];
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};
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2012-05-14 04:06:20 -07:00
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2015-07-07 02:30:25 -07:00
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static int nx_crypto_ctx_sha256_init(struct crypto_tfm *tfm)
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2012-05-14 04:06:20 -07:00
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{
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2015-07-07 02:30:25 -07:00
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struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(tfm);
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int err;
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2012-05-14 04:06:20 -07:00
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2015-07-07 02:30:25 -07:00
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err = nx_crypto_ctx_sha_init(tfm);
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if (err)
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return err;
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2012-05-14 04:06:20 -07:00
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2015-07-07 02:30:25 -07:00
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nx_ctx_init(nx_ctx, HCOP_FC_SHA);
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2012-05-14 04:06:20 -07:00
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nx_ctx->ap = &nx_ctx->props[NX_PROPS_SHA256];
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NX_CPB_SET_DIGEST_SIZE(nx_ctx->csbcpb, NX_DS_SHA256);
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2015-07-07 02:30:25 -07:00
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return 0;
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}
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2015-04-23 13:41:43 -07:00
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2015-07-07 02:30:25 -07:00
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static int nx_sha256_init(struct shash_desc *desc) {
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2021-06-17 01:00:12 -07:00
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struct sha256_state_be *sctx = shash_desc_ctx(desc);
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2014-10-28 10:49:46 -07:00
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2015-07-07 02:30:25 -07:00
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memset(sctx, 0, sizeof *sctx);
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2014-10-28 10:49:46 -07:00
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sctx->state[0] = __cpu_to_be32(SHA256_H0);
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sctx->state[1] = __cpu_to_be32(SHA256_H1);
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sctx->state[2] = __cpu_to_be32(SHA256_H2);
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sctx->state[3] = __cpu_to_be32(SHA256_H3);
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sctx->state[4] = __cpu_to_be32(SHA256_H4);
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sctx->state[5] = __cpu_to_be32(SHA256_H5);
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sctx->state[6] = __cpu_to_be32(SHA256_H6);
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sctx->state[7] = __cpu_to_be32(SHA256_H7);
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sctx->count = 0;
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2012-05-14 04:06:20 -07:00
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return 0;
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}
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static int nx_sha256_update(struct shash_desc *desc, const u8 *data,
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unsigned int len)
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{
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2021-06-17 01:00:12 -07:00
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struct sha256_state_be *sctx = shash_desc_ctx(desc);
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2012-05-14 04:06:20 -07:00
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struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
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struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb;
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2015-07-07 02:30:25 -07:00
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struct nx_sg *out_sg;
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2014-10-28 10:49:46 -07:00
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u64 to_process = 0, leftover, total;
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2013-08-12 14:49:37 -07:00
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unsigned long irq_flags;
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2012-05-14 04:06:20 -07:00
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int rc = 0;
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2014-10-28 10:49:46 -07:00
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int data_len;
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2015-04-23 13:41:43 -07:00
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u32 max_sg_len;
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2014-10-28 10:49:46 -07:00
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u64 buf_len = (sctx->count % SHA256_BLOCK_SIZE);
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2012-05-14 04:06:20 -07:00
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2013-08-12 14:49:37 -07:00
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spin_lock_irqsave(&nx_ctx->lock, irq_flags);
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2012-05-14 04:06:20 -07:00
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/* 2 cases for total data len:
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2013-08-02 05:09:52 -07:00
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* 1: < SHA256_BLOCK_SIZE: copy into state, return 0
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* 2: >= SHA256_BLOCK_SIZE: process X blocks, copy in leftover
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2012-05-14 04:06:20 -07:00
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*/
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2014-10-28 10:49:46 -07:00
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total = (sctx->count % SHA256_BLOCK_SIZE) + len;
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2013-08-02 05:09:52 -07:00
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if (total < SHA256_BLOCK_SIZE) {
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2014-10-28 10:49:46 -07:00
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memcpy(sctx->buf + buf_len, data, len);
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2012-05-14 04:06:20 -07:00
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sctx->count += len;
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goto out;
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}
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2014-10-28 10:49:46 -07:00
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memcpy(csbcpb->cpb.sha256.message_digest, sctx->state, SHA256_DIGEST_SIZE);
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NX_CPB_FDM(csbcpb) |= NX_FDM_INTERMEDIATE;
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NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION;
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2013-08-02 05:09:52 -07:00
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2015-04-23 13:41:43 -07:00
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max_sg_len = min_t(u64, nx_ctx->ap->sglen,
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nx_driver.of.max_sg_len/sizeof(struct nx_sg));
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max_sg_len = min_t(u64, max_sg_len,
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nx_ctx->ap->databytelen/NX_PAGE_SIZE);
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2015-07-07 02:30:25 -07:00
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data_len = SHA256_DIGEST_SIZE;
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out_sg = nx_build_sg_list(nx_ctx->out_sg, (u8 *)sctx->state,
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&data_len, max_sg_len);
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nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg);
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if (data_len != SHA256_DIGEST_SIZE) {
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rc = -EINVAL;
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goto out;
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}
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2013-08-02 05:09:52 -07:00
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do {
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2015-08-07 23:47:28 -07:00
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int used_sgs = 0;
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struct nx_sg *in_sg = nx_ctx->in_sg;
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2013-08-02 05:09:52 -07:00
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2014-10-28 10:49:46 -07:00
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if (buf_len) {
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data_len = buf_len;
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2015-08-07 23:47:28 -07:00
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in_sg = nx_build_sg_list(in_sg,
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2015-04-23 13:41:43 -07:00
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(u8 *) sctx->buf,
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&data_len,
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max_sg_len);
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2014-10-28 10:49:46 -07:00
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2015-04-23 13:41:43 -07:00
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if (data_len != buf_len) {
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rc = -EINVAL;
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2014-10-28 10:49:46 -07:00
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goto out;
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2015-04-23 13:41:43 -07:00
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}
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2015-08-07 23:47:28 -07:00
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used_sgs = in_sg - nx_ctx->in_sg;
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2013-08-02 05:09:52 -07:00
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}
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2014-10-28 10:49:46 -07:00
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2015-08-07 23:47:28 -07:00
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/* to_process: SHA256_BLOCK_SIZE aligned chunk to be
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* processed in this iteration. This value is restricted
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* by sg list limits and number of sgs we already used
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* for leftover data. (see above)
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* In ideal case, we could allow NX_PAGE_SIZE * max_sg_len,
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* but because data may not be aligned, we need to account
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* for that too. */
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to_process = min_t(u64, total,
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(max_sg_len - 1 - used_sgs) * NX_PAGE_SIZE);
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to_process = to_process & ~(SHA256_BLOCK_SIZE - 1);
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2014-10-28 10:49:46 -07:00
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data_len = to_process - buf_len;
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2015-04-23 13:41:43 -07:00
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in_sg = nx_build_sg_list(in_sg, (u8 *) data,
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&data_len, max_sg_len);
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2014-10-28 10:49:46 -07:00
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2015-04-23 13:41:43 -07:00
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nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg);
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2014-10-28 10:49:46 -07:00
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2015-08-07 23:47:28 -07:00
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to_process = data_len + buf_len;
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2014-10-28 10:49:46 -07:00
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leftover = total - to_process;
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/*
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* we've hit the nx chip previously and we're updating
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* again, so copy over the partial digest.
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*/
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memcpy(csbcpb->cpb.sha256.input_partial_digest,
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2013-08-02 05:09:52 -07:00
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csbcpb->cpb.sha256.message_digest,
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SHA256_DIGEST_SIZE);
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if (!nx_ctx->op.inlen || !nx_ctx->op.outlen) {
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rc = -EINVAL;
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goto out;
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}
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2019-04-14 17:37:08 -07:00
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rc = nx_hcall_sync(nx_ctx, &nx_ctx->op, 0);
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2013-08-02 05:09:52 -07:00
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if (rc)
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goto out;
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atomic_inc(&(nx_ctx->stats->sha256_ops));
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total -= to_process;
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2014-10-28 10:49:46 -07:00
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data += to_process - buf_len;
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buf_len = 0;
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2013-08-02 05:09:52 -07:00
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} while (leftover >= SHA256_BLOCK_SIZE);
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2012-05-14 04:06:20 -07:00
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/* copy the leftover back into the state struct */
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2013-04-12 10:13:59 -07:00
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if (leftover)
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2013-08-02 05:09:52 -07:00
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memcpy(sctx->buf, data, leftover);
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2014-10-28 10:49:46 -07:00
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sctx->count += len;
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memcpy(sctx->state, csbcpb->cpb.sha256.message_digest, SHA256_DIGEST_SIZE);
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2012-05-14 04:06:20 -07:00
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out:
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2013-08-12 14:49:37 -07:00
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spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
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2012-05-14 04:06:20 -07:00
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return rc;
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}
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static int nx_sha256_final(struct shash_desc *desc, u8 *out)
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{
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2021-06-17 01:00:12 -07:00
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struct sha256_state_be *sctx = shash_desc_ctx(desc);
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2012-05-14 04:06:20 -07:00
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struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
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struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb;
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2015-04-23 13:41:43 -07:00
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struct nx_sg *in_sg, *out_sg;
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2013-08-12 14:49:37 -07:00
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unsigned long irq_flags;
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2015-04-23 13:41:43 -07:00
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u32 max_sg_len;
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int rc = 0;
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2014-10-28 10:49:46 -07:00
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int len;
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2012-05-14 04:06:20 -07:00
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2013-08-12 14:49:37 -07:00
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spin_lock_irqsave(&nx_ctx->lock, irq_flags);
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2015-04-23 13:41:43 -07:00
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max_sg_len = min_t(u64, nx_ctx->ap->sglen,
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nx_driver.of.max_sg_len/sizeof(struct nx_sg));
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max_sg_len = min_t(u64, max_sg_len,
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nx_ctx->ap->databytelen/NX_PAGE_SIZE);
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2014-10-28 10:49:46 -07:00
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/* final is represented by continuing the operation and indicating that
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* this is not an intermediate operation */
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if (sctx->count >= SHA256_BLOCK_SIZE) {
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2012-05-14 04:06:20 -07:00
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/* we've hit the nx chip previously, now we're finalizing,
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* so copy over the partial digest */
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2014-10-28 10:49:46 -07:00
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memcpy(csbcpb->cpb.sha256.input_partial_digest, sctx->state, SHA256_DIGEST_SIZE);
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NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
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NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION;
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} else {
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NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
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NX_CPB_FDM(csbcpb) &= ~NX_FDM_CONTINUATION;
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2012-05-14 04:06:20 -07:00
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}
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2014-10-28 10:49:46 -07:00
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csbcpb->cpb.sha256.message_bit_length = (u64) (sctx->count * 8);
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2012-05-14 04:06:20 -07:00
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2014-10-28 10:49:46 -07:00
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len = sctx->count & (SHA256_BLOCK_SIZE - 1);
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2015-04-23 13:41:43 -07:00
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in_sg = nx_build_sg_list(nx_ctx->in_sg, (u8 *) sctx->buf,
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&len, max_sg_len);
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2012-05-14 04:06:20 -07:00
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2015-04-23 13:41:43 -07:00
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if (len != (sctx->count & (SHA256_BLOCK_SIZE - 1))) {
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rc = -EINVAL;
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2014-10-28 10:49:46 -07:00
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goto out;
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2015-04-23 13:41:43 -07:00
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}
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2014-10-28 10:49:46 -07:00
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len = SHA256_DIGEST_SIZE;
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2015-04-23 13:41:43 -07:00
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out_sg = nx_build_sg_list(nx_ctx->out_sg, out, &len, max_sg_len);
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2014-10-28 10:49:46 -07:00
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2015-04-23 13:41:43 -07:00
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if (len != SHA256_DIGEST_SIZE) {
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rc = -EINVAL;
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2014-10-28 10:49:46 -07:00
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goto out;
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2015-04-23 13:41:43 -07:00
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}
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2012-05-14 04:06:20 -07:00
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2015-04-23 13:41:43 -07:00
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nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg);
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nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg);
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2012-05-14 04:06:20 -07:00
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if (!nx_ctx->op.outlen) {
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rc = -EINVAL;
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goto out;
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}
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2019-04-14 17:37:08 -07:00
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rc = nx_hcall_sync(nx_ctx, &nx_ctx->op, 0);
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2012-05-14 04:06:20 -07:00
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if (rc)
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goto out;
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atomic_inc(&(nx_ctx->stats->sha256_ops));
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2014-10-28 10:49:46 -07:00
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atomic64_add(sctx->count, &(nx_ctx->stats->sha256_bytes));
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2012-05-14 04:06:20 -07:00
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memcpy(out, csbcpb->cpb.sha256.message_digest, SHA256_DIGEST_SIZE);
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out:
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2013-08-12 14:49:37 -07:00
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spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
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2012-05-14 04:06:20 -07:00
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return rc;
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}
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static int nx_sha256_export(struct shash_desc *desc, void *out)
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{
|
2021-06-17 01:00:12 -07:00
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struct sha256_state_be *sctx = shash_desc_ctx(desc);
|
2012-05-14 04:06:20 -07:00
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2014-10-28 10:49:46 -07:00
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memcpy(out, sctx, sizeof(*sctx));
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2012-05-14 04:06:20 -07:00
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return 0;
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}
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static int nx_sha256_import(struct shash_desc *desc, const void *in)
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{
|
2021-06-17 01:00:12 -07:00
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struct sha256_state_be *sctx = shash_desc_ctx(desc);
|
2012-05-14 04:06:20 -07:00
|
|
|
|
2014-10-28 10:49:46 -07:00
|
|
|
memcpy(sctx, in, sizeof(*sctx));
|
2012-05-14 04:06:20 -07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
struct shash_alg nx_shash_sha256_alg = {
|
|
|
|
.digestsize = SHA256_DIGEST_SIZE,
|
|
|
|
.init = nx_sha256_init,
|
|
|
|
.update = nx_sha256_update,
|
|
|
|
.final = nx_sha256_final,
|
|
|
|
.export = nx_sha256_export,
|
|
|
|
.import = nx_sha256_import,
|
2021-06-17 01:00:12 -07:00
|
|
|
.descsize = sizeof(struct sha256_state_be),
|
|
|
|
.statesize = sizeof(struct sha256_state_be),
|
2012-05-14 04:06:20 -07:00
|
|
|
.base = {
|
|
|
|
.cra_name = "sha256",
|
|
|
|
.cra_driver_name = "sha256-nx",
|
|
|
|
.cra_priority = 300,
|
|
|
|
.cra_blocksize = SHA256_BLOCK_SIZE,
|
|
|
|
.cra_module = THIS_MODULE,
|
|
|
|
.cra_ctxsize = sizeof(struct nx_crypto_ctx),
|
2015-07-07 02:30:25 -07:00
|
|
|
.cra_init = nx_crypto_ctx_sha256_init,
|
2012-05-14 04:06:20 -07:00
|
|
|
.cra_exit = nx_crypto_ctx_exit,
|
|
|
|
}
|
|
|
|
};
|