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linux/drivers/clk/ingenic/jz4770-cgu.c

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clk: Add Ingenic jz4770 CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4770 SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Maarten ter Huurne <maarten@treewalker.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18482/ Signed-off-by: James Hogan <jhogan@kernel.org>
2018-01-16 08:47:56 -07:00
// SPDX-License-Identifier: GPL-2.0
/*
* JZ4770 SoC CGU driver
* Copyright 2018, Paul Cercueil <paul@crapouillou.net>
*/
#include <linux/bitops.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
clk: Remove io.h from clk-provider.h Now that we've gotten rid of clk_readl() we can remove io.h from the clk-provider header and push out the io.h include to any code that isn't already including the io.h header but using things like readl/writel, etc. Found with this grep: git grep -l clk-provider.h | grep '.c$' | xargs git grep -L 'linux/io.h' | \ xargs git grep -l \ -e '\<__iowrite32_copy\>' --or \ -e '\<__ioread32_copy\>' --or \ -e '\<__iowrite64_copy\>' --or \ -e '\<ioremap_page_range\>' --or \ -e '\<ioremap_huge_init\>' --or \ -e '\<arch_ioremap_pud_supported\>' --or \ -e '\<arch_ioremap_pmd_supported\>' --or \ -e '\<devm_ioport_map\>' --or \ -e '\<devm_ioport_unmap\>' --or \ -e '\<IOMEM_ERR_PTR\>' --or \ -e '\<devm_ioremap\>' --or \ -e '\<devm_ioremap_nocache\>' --or \ -e '\<devm_ioremap_wc\>' --or \ -e '\<devm_iounmap\>' --or \ -e '\<devm_ioremap_release\>' --or \ -e '\<devm_memremap\>' --or \ -e '\<devm_memunmap\>' --or \ -e '\<__devm_memremap_pages\>' --or \ -e '\<pci_remap_cfgspace\>' --or \ -e '\<arch_has_dev_port\>' --or \ -e '\<arch_phys_wc_add\>' --or \ -e '\<arch_phys_wc_del\>' --or \ -e '\<memremap\>' --or \ -e '\<memunmap\>' --or \ -e '\<arch_io_reserve_memtype_wc\>' --or \ -e '\<arch_io_free_memtype_wc\>' --or \ -e '\<__io_aw\>' --or \ -e '\<__io_pbw\>' --or \ -e '\<__io_paw\>' --or \ -e '\<__io_pbr\>' --or \ -e '\<__io_par\>' --or \ -e '\<__raw_readb\>' --or \ -e '\<__raw_readw\>' --or \ -e '\<__raw_readl\>' --or \ -e '\<__raw_readq\>' --or \ -e '\<__raw_writeb\>' --or \ -e '\<__raw_writew\>' --or \ -e '\<__raw_writel\>' --or \ -e '\<__raw_writeq\>' --or \ -e '\<readb\>' --or \ -e '\<readw\>' --or \ -e '\<readl\>' --or \ -e '\<readq\>' --or \ -e '\<writeb\>' --or \ -e '\<writew\>' --or \ -e '\<writel\>' --or \ -e '\<writeq\>' --or \ -e '\<readb_relaxed\>' --or \ -e '\<readw_relaxed\>' --or \ -e '\<readl_relaxed\>' --or \ -e '\<readq_relaxed\>' --or \ -e '\<writeb_relaxed\>' --or \ -e '\<writew_relaxed\>' --or \ -e '\<writel_relaxed\>' --or \ -e '\<writeq_relaxed\>' --or \ -e '\<readsb\>' --or \ -e '\<readsw\>' --or \ -e '\<readsl\>' --or \ -e '\<readsq\>' --or \ -e '\<writesb\>' --or \ -e '\<writesw\>' --or \ -e '\<writesl\>' --or \ -e '\<writesq\>' --or \ -e '\<inb\>' --or \ -e '\<inw\>' --or \ -e '\<inl\>' --or \ -e '\<outb\>' --or \ -e '\<outw\>' --or \ -e '\<outl\>' --or \ -e '\<inb_p\>' --or \ -e '\<inw_p\>' --or \ -e '\<inl_p\>' --or \ -e '\<outb_p\>' --or \ -e '\<outw_p\>' --or \ -e '\<outl_p\>' --or \ -e '\<insb\>' --or \ -e '\<insw\>' --or \ -e '\<insl\>' --or \ -e '\<outsb\>' --or \ -e '\<outsw\>' --or \ -e '\<outsl\>' --or \ -e '\<insb_p\>' --or \ -e '\<insw_p\>' --or \ -e '\<insl_p\>' --or \ -e '\<outsb_p\>' --or \ -e '\<outsw_p\>' --or \ -e '\<outsl_p\>' --or \ -e '\<ioread8\>' --or \ -e '\<ioread16\>' --or \ -e '\<ioread32\>' --or \ -e '\<ioread64\>' --or \ -e '\<iowrite8\>' --or \ -e '\<iowrite16\>' --or \ -e '\<iowrite32\>' --or \ -e '\<iowrite64\>' --or \ -e '\<ioread16be\>' --or \ -e '\<ioread32be\>' --or \ -e '\<ioread64be\>' --or \ -e '\<iowrite16be\>' --or \ -e '\<iowrite32be\>' --or \ -e '\<iowrite64be\>' --or \ -e '\<ioread8_rep\>' --or \ -e '\<ioread16_rep\>' --or \ -e '\<ioread32_rep\>' --or \ -e '\<ioread64_rep\>' --or \ -e '\<iowrite8_rep\>' --or \ -e '\<iowrite16_rep\>' --or \ -e '\<iowrite32_rep\>' --or \ -e '\<iowrite64_rep\>' --or \ -e '\<__io_virt\>' --or \ -e '\<pci_iounmap\>' --or \ -e '\<virt_to_phys\>' --or \ -e '\<phys_to_virt\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap\>' --or \ -e '\<__ioremap\>' --or \ -e '\<iounmap\>' --or \ -e '\<ioremap\>' --or \ -e '\<ioremap_nocache\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wt\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<xlate_dev_kmem_ptr\>' --or \ -e '\<xlate_dev_mem_ptr\>' --or \ -e '\<unxlate_dev_mem_ptr\>' --or \ -e '\<virt_to_bus\>' --or \ -e '\<bus_to_virt\>' --or \ -e '\<memset_io\>' --or \ -e '\<memcpy_fromio\>' --or \ -e '\<memcpy_toio\>' I also reordered a couple includes when they weren't alphabetical and removed clk.h from kona, replacing it with clk-provider.h because that driver doesn't use clk consumer APIs. Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Sekhar Nori <nsekhar@ti.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Mark Brown <broonie@kernel.org> Cc: Chris Zankel <chris@zankel.net> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: John Crispin <john@phrozen.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-18 15:20:22 -07:00
#include <linux/io.h>
clk: Add Ingenic jz4770 CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4770 SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Maarten ter Huurne <maarten@treewalker.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18482/ Signed-off-by: James Hogan <jhogan@kernel.org>
2018-01-16 08:47:56 -07:00
#include <linux/of.h>
clk: Ingenic: Adjust cgu code to make it compatible with X1830. The PLL of X1830 Soc from Ingenic has been greatly changed, the bypass control is placed in another register, so now two registers may needed to control the PLL. To this end, a new "bypass_reg" was introduced. In addition, when calculating rate, the PLL of X1830 introduced an extra 2x multiplier, so a new "rate_multiplier" was introduced. And adjust the code in jz47xx-cgu.c and x1000-cgu.c, make it to be compatible with the new cgu code. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lkml.kernel.org/r/20200528031549.13846-3-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-27 20:15:44 -07:00
dt-bindings: Rename Ingenic CGU headers to ingenic,*.h Tidy up a bit the tree, by prefixing all include/dt-bindings/clock/ files related to Ingenic SoCs with 'ingenic,'. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211016133322.40771-1-paul@crapouillou.net
2021-10-16 06:33:21 -07:00
#include <dt-bindings/clock/ingenic,jz4770-cgu.h>
clk: Ingenic: Adjust cgu code to make it compatible with X1830. The PLL of X1830 Soc from Ingenic has been greatly changed, the bypass control is placed in another register, so now two registers may needed to control the PLL. To this end, a new "bypass_reg" was introduced. In addition, when calculating rate, the PLL of X1830 introduced an extra 2x multiplier, so a new "rate_multiplier" was introduced. And adjust the code in jz47xx-cgu.c and x1000-cgu.c, make it to be compatible with the new cgu code. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lkml.kernel.org/r/20200528031549.13846-3-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-27 20:15:44 -07:00
clk: Add Ingenic jz4770 CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4770 SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Maarten ter Huurne <maarten@treewalker.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18482/ Signed-off-by: James Hogan <jhogan@kernel.org>
2018-01-16 08:47:56 -07:00
#include "cgu.h"
clk: ingenic: Handle setting the Low-Power Mode bit The Low-Power Mode, when enabled, will make the "wait" MIPS instruction suspend the system. This is not really clock-related, but this bit happens to be in the register set of the CGU. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-11 11:07:54 -07:00
#include "pm.h"
clk: Add Ingenic jz4770 CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4770 SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Maarten ter Huurne <maarten@treewalker.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18482/ Signed-off-by: James Hogan <jhogan@kernel.org>
2018-01-16 08:47:56 -07:00
/*
* CPM registers offset address definition
*/
#define CGU_REG_CPCCR 0x00
#define CGU_REG_LCR 0x04
#define CGU_REG_CPPCR0 0x10
#define CGU_REG_CLKGR0 0x20
#define CGU_REG_OPCR 0x24
#define CGU_REG_CLKGR1 0x28
#define CGU_REG_CPPCR1 0x30
#define CGU_REG_USBPCR1 0x48
#define CGU_REG_USBCDR 0x50
#define CGU_REG_I2SCDR 0x60
#define CGU_REG_LPCDR 0x64
#define CGU_REG_MSC0CDR 0x68
#define CGU_REG_UHCCDR 0x6c
#define CGU_REG_SSICDR 0x74
#define CGU_REG_CIMCDR 0x7c
#define CGU_REG_GPSCDR 0x80
#define CGU_REG_PCMCDR 0x84
#define CGU_REG_GPUCDR 0x88
#define CGU_REG_MSC1CDR 0xA4
#define CGU_REG_MSC2CDR 0xA8
#define CGU_REG_BCHCDR 0xAC
/* bits within the OPCR register */
#define OPCR_SPENDH BIT(5) /* UHC PHY suspend */
/* bits within the USBPCR1 register */
#define USBPCR1_UHC_POWER BIT(5) /* UHC PHY power down */
static struct ingenic_cgu *cgu;
static int jz4770_uhc_phy_enable(struct clk_hw *hw)
{
void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1;
writel(readl(reg_opcr) & ~OPCR_SPENDH, reg_opcr);
writel(readl(reg_usbpcr1) | USBPCR1_UHC_POWER, reg_usbpcr1);
return 0;
}
static void jz4770_uhc_phy_disable(struct clk_hw *hw)
{
void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1;
writel(readl(reg_usbpcr1) & ~USBPCR1_UHC_POWER, reg_usbpcr1);
writel(readl(reg_opcr) | OPCR_SPENDH, reg_opcr);
}
static int jz4770_uhc_phy_is_enabled(struct clk_hw *hw)
{
void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1;
return !(readl(reg_opcr) & OPCR_SPENDH) &&
(readl(reg_usbpcr1) & USBPCR1_UHC_POWER);
}
static const struct clk_ops jz4770_uhc_phy_ops = {
.enable = jz4770_uhc_phy_enable,
.disable = jz4770_uhc_phy_disable,
.is_enabled = jz4770_uhc_phy_is_enabled,
};
static const s8 pll_od_encoding[8] = {
0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
};
clk: ingenic/jz4770: Fix incorrect dividers for main clocks The main clocks (cclk, h0clk, h1clk, h2clk, c1clk, pclk) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-05-02 14:25:00 -07:00
static const u8 jz4770_cgu_cpccr_div_table[] = {
1, 2, 3, 4, 6, 8, 12,
};
clk: Add Ingenic jz4770 CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4770 SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Maarten ter Huurne <maarten@treewalker.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18482/ Signed-off-by: James Hogan <jhogan@kernel.org>
2018-01-16 08:47:56 -07:00
static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
/* External clocks */
[JZ4770_CLK_EXT] = { "ext", CGU_CLK_EXT },
[JZ4770_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT },
/* PLLs */
[JZ4770_CLK_PLL0] = {
"pll0", CGU_CLK_PLL,
.parents = { JZ4770_CLK_EXT },
.pll = {
.reg = CGU_REG_CPPCR0,
clk: Ingenic: Adjust cgu code to make it compatible with X1830. The PLL of X1830 Soc from Ingenic has been greatly changed, the bypass control is placed in another register, so now two registers may needed to control the PLL. To this end, a new "bypass_reg" was introduced. In addition, when calculating rate, the PLL of X1830 introduced an extra 2x multiplier, so a new "rate_multiplier" was introduced. And adjust the code in jz47xx-cgu.c and x1000-cgu.c, make it to be compatible with the new cgu code. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lkml.kernel.org/r/20200528031549.13846-3-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-27 20:15:44 -07:00
.rate_multiplier = 1,
clk: Add Ingenic jz4770 CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4770 SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Maarten ter Huurne <maarten@treewalker.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18482/ Signed-off-by: James Hogan <jhogan@kernel.org>
2018-01-16 08:47:56 -07:00
.m_shift = 24,
.m_bits = 7,
.m_offset = 1,
.n_shift = 18,
.n_bits = 5,
.n_offset = 1,
.od_shift = 16,
.od_bits = 2,
.od_max = 8,
.od_encoding = pll_od_encoding,
clk: Ingenic: Adjust cgu code to make it compatible with X1830. The PLL of X1830 Soc from Ingenic has been greatly changed, the bypass control is placed in another register, so now two registers may needed to control the PLL. To this end, a new "bypass_reg" was introduced. In addition, when calculating rate, the PLL of X1830 introduced an extra 2x multiplier, so a new "rate_multiplier" was introduced. And adjust the code in jz47xx-cgu.c and x1000-cgu.c, make it to be compatible with the new cgu code. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lkml.kernel.org/r/20200528031549.13846-3-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-27 20:15:44 -07:00
.bypass_reg = CGU_REG_CPPCR0,
clk: Add Ingenic jz4770 CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4770 SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Maarten ter Huurne <maarten@treewalker.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18482/ Signed-off-by: James Hogan <jhogan@kernel.org>
2018-01-16 08:47:56 -07:00
.bypass_bit = 9,
.enable_bit = 8,
.stable_bit = 10,
},
},
[JZ4770_CLK_PLL1] = {
/* TODO: PLL1 can depend on PLL0 */
"pll1", CGU_CLK_PLL,
.parents = { JZ4770_CLK_EXT },
.pll = {
.reg = CGU_REG_CPPCR1,
clk: Ingenic: Adjust cgu code to make it compatible with X1830. The PLL of X1830 Soc from Ingenic has been greatly changed, the bypass control is placed in another register, so now two registers may needed to control the PLL. To this end, a new "bypass_reg" was introduced. In addition, when calculating rate, the PLL of X1830 introduced an extra 2x multiplier, so a new "rate_multiplier" was introduced. And adjust the code in jz47xx-cgu.c and x1000-cgu.c, make it to be compatible with the new cgu code. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lkml.kernel.org/r/20200528031549.13846-3-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-27 20:15:44 -07:00
.rate_multiplier = 1,
clk: Add Ingenic jz4770 CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4770 SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Maarten ter Huurne <maarten@treewalker.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18482/ Signed-off-by: James Hogan <jhogan@kernel.org>
2018-01-16 08:47:56 -07:00
.m_shift = 24,
.m_bits = 7,
.m_offset = 1,
.n_shift = 18,
.n_bits = 5,
.n_offset = 1,
.od_shift = 16,
.od_bits = 2,
.od_max = 8,
.od_encoding = pll_od_encoding,
clk: ingenic: Remove pll_info.no_bypass_bit We can express that a PLL has no bypass bit by simply setting the .bypass_bit field to a negative value. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-5-paul@crapouillou.net Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1830-neo/X1830 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-05-30 09:49:21 -07:00
.bypass_bit = -1,
clk: Add Ingenic jz4770 CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4770 SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Maarten ter Huurne <maarten@treewalker.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18482/ Signed-off-by: James Hogan <jhogan@kernel.org>
2018-01-16 08:47:56 -07:00
.enable_bit = 7,
.stable_bit = 6,
},
},
/* Main clocks */
[JZ4770_CLK_CCLK] = {
"cclk", CGU_CLK_DIV,
clk: ingenic: Mark critical clocks in Ingenic SoCs Consider CPU, L2 cache, and memory clocks as critical to prevent them -- and the parent clocks -- from being automatically gated, since nothing calls clk_get() on these clocks. Gating the CPU clock hangs the processor, and gating memory makes external DRAM inaccessible. Normal kernel code can't hope to deal with either situation so those clocks have to be critical. The L2 cache is required only if caches are running, and could be gated if the kernel takes care to flush and disable caches before gating the clock. There's no mechanism to do this, and probably no reason to do it, so it's simpler to mark the L2 cache as critical. Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20220428164454.17908-3-aidanmacdonald.0x0@gmail.com Tested-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> # On X1000 and X1830 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-04-28 09:44:53 -07:00
/*
* Disabling the CPU clock or any parent clocks will hang the
* system; mark it critical.
*/
.flags = CLK_IS_CRITICAL,
clk: Add Ingenic jz4770 CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4770 SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Maarten ter Huurne <maarten@treewalker.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18482/ Signed-off-by: James Hogan <jhogan@kernel.org>
2018-01-16 08:47:56 -07:00
.parents = { JZ4770_CLK_PLL0, },
clk: ingenic/jz4770: Fix incorrect dividers for main clocks The main clocks (cclk, h0clk, h1clk, h2clk, c1clk, pclk) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-05-02 14:25:00 -07:00
.div = {
clk: Support bypassing dividers When a clock is declared as both CGU_CLK_DIV and CGU_CLK_MUX, the CGU code expects the mux to be applied first, the divider second. On the JZ4760, and maybe on some other SoCs, some clocks also have a mux setting and a divider, but the divider is not applied to all parents selectable from the mux. This could be solved by creating two clocks, one with CGU_CLK_DIV and one with CGU_CLK_MUX, but that would increase the number of clocks. Instead, add a 8-bit mask to CGU_CLK_DIV clocks. If the bit corresponding to the parent clock's index is set, the divider is bypassed. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-3-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-05-30 09:49:19 -07:00
CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
clk: ingenic/jz4770: Fix incorrect dividers for main clocks The main clocks (cclk, h0clk, h1clk, h2clk, c1clk, pclk) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-05-02 14:25:00 -07:00
jz4770_cgu_cpccr_div_table,
},
clk: Add Ingenic jz4770 CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4770 SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Maarten ter Huurne <maarten@treewalker.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18482/ Signed-off-by: James Hogan <jhogan@kernel.org>
2018-01-16 08:47:56 -07:00
},
[JZ4770_CLK_H0CLK] = {
"h0clk", CGU_CLK_DIV,
.parents = { JZ4770_CLK_PLL0, },
clk: ingenic/jz4770: Fix incorrect dividers for main clocks The main clocks (cclk, h0clk, h1clk, h2clk, c1clk, pclk) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-05-02 14:25:00 -07:00
.div = {
clk: Support bypassing dividers When a clock is declared as both CGU_CLK_DIV and CGU_CLK_MUX, the CGU code expects the mux to be applied first, the divider second. On the JZ4760, and maybe on some other SoCs, some clocks also have a mux setting and a divider, but the divider is not applied to all parents selectable from the mux. This could be solved by creating two clocks, one with CGU_CLK_DIV and one with CGU_CLK_MUX, but that would increase the number of clocks. Instead, add a 8-bit mask to CGU_CLK_DIV clocks. If the bit corresponding to the parent clock's index is set, the divider is bypassed. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-3-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-05-30 09:49:19 -07:00
CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0,
clk: ingenic/jz4770: Fix incorrect dividers for main clocks The main clocks (cclk, h0clk, h1clk, h2clk, c1clk, pclk) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-05-02 14:25:00 -07:00
jz4770_cgu_cpccr_div_table,
},
clk: Add Ingenic jz4770 CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4770 SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Maarten ter Huurne <maarten@treewalker.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18482/ Signed-off-by: James Hogan <jhogan@kernel.org>
2018-01-16 08:47:56 -07:00
},
[JZ4770_CLK_H1CLK] = {
"h1clk", CGU_CLK_DIV | CGU_CLK_GATE,
.parents = { JZ4770_CLK_PLL0, },
clk: ingenic/jz4770: Fix incorrect dividers for main clocks The main clocks (cclk, h0clk, h1clk, h2clk, c1clk, pclk) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-05-02 14:25:00 -07:00
.div = {
clk: Support bypassing dividers When a clock is declared as both CGU_CLK_DIV and CGU_CLK_MUX, the CGU code expects the mux to be applied first, the divider second. On the JZ4760, and maybe on some other SoCs, some clocks also have a mux setting and a divider, but the divider is not applied to all parents selectable from the mux. This could be solved by creating two clocks, one with CGU_CLK_DIV and one with CGU_CLK_MUX, but that would increase the number of clocks. Instead, add a 8-bit mask to CGU_CLK_DIV clocks. If the bit corresponding to the parent clock's index is set, the divider is bypassed. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-3-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-05-30 09:49:19 -07:00
CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1, 0,
clk: ingenic/jz4770: Fix incorrect dividers for main clocks The main clocks (cclk, h0clk, h1clk, h2clk, c1clk, pclk) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-05-02 14:25:00 -07:00
jz4770_cgu_cpccr_div_table,
},
clk: ingenic: jz4770: Enable power of AHB1 bus after ungating VPU clock This was broken before, because the AHB1 bus was enabled before the VPU clock was ungated, while it must be done afterwards. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-20 09:31:16 -07:00
.gate = { CGU_REG_CLKGR1, 7 },
clk: Add Ingenic jz4770 CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4770 SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Maarten ter Huurne <maarten@treewalker.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18482/ Signed-off-by: James Hogan <jhogan@kernel.org>
2018-01-16 08:47:56 -07:00
},
[JZ4770_CLK_H2CLK] = {
"h2clk", CGU_CLK_DIV,
.parents = { JZ4770_CLK_PLL0, },
clk: ingenic/jz4770: Fix incorrect dividers for main clocks The main clocks (cclk, h0clk, h1clk, h2clk, c1clk, pclk) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-05-02 14:25:00 -07:00
.div = {
clk: Support bypassing dividers When a clock is declared as both CGU_CLK_DIV and CGU_CLK_MUX, the CGU code expects the mux to be applied first, the divider second. On the JZ4760, and maybe on some other SoCs, some clocks also have a mux setting and a divider, but the divider is not applied to all parents selectable from the mux. This could be solved by creating two clocks, one with CGU_CLK_DIV and one with CGU_CLK_MUX, but that would increase the number of clocks. Instead, add a 8-bit mask to CGU_CLK_DIV clocks. If the bit corresponding to the parent clock's index is set, the divider is bypassed. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-3-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-05-30 09:49:19 -07:00
CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0,
clk: ingenic/jz4770: Fix incorrect dividers for main clocks The main clocks (cclk, h0clk, h1clk, h2clk, c1clk, pclk) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-05-02 14:25:00 -07:00
jz4770_cgu_cpccr_div_table,
},
clk: Add Ingenic jz4770 CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4770 SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Maarten ter Huurne <maarten@treewalker.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18482/ Signed-off-by: James Hogan <jhogan@kernel.org>
2018-01-16 08:47:56 -07:00
},
[JZ4770_CLK_C1CLK] = {
clk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idle When the main processor goes idle, by default its clock is stopped. However, this also stops the clock of the co-processor. Here, if the C1CLK clock is enabled, we disable this functionality. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-20 09:31:15 -07:00
"c1clk", CGU_CLK_DIV | CGU_CLK_GATE,
clk: Add Ingenic jz4770 CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4770 SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Maarten ter Huurne <maarten@treewalker.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18482/ Signed-off-by: James Hogan <jhogan@kernel.org>
2018-01-16 08:47:56 -07:00
.parents = { JZ4770_CLK_PLL0, },
clk: ingenic/jz4770: Fix incorrect dividers for main clocks The main clocks (cclk, h0clk, h1clk, h2clk, c1clk, pclk) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-05-02 14:25:00 -07:00
.div = {
clk: Support bypassing dividers When a clock is declared as both CGU_CLK_DIV and CGU_CLK_MUX, the CGU code expects the mux to be applied first, the divider second. On the JZ4760, and maybe on some other SoCs, some clocks also have a mux setting and a divider, but the divider is not applied to all parents selectable from the mux. This could be solved by creating two clocks, one with CGU_CLK_DIV and one with CGU_CLK_MUX, but that would increase the number of clocks. Instead, add a 8-bit mask to CGU_CLK_DIV clocks. If the bit corresponding to the parent clock's index is set, the divider is bypassed. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-3-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-05-30 09:49:19 -07:00
CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,
clk: ingenic/jz4770: Fix incorrect dividers for main clocks The main clocks (cclk, h0clk, h1clk, h2clk, c1clk, pclk) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-05-02 14:25:00 -07:00
jz4770_cgu_cpccr_div_table,
},
clk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idle When the main processor goes idle, by default its clock is stopped. However, this also stops the clock of the co-processor. Here, if the C1CLK clock is enabled, we disable this functionality. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-20 09:31:15 -07:00
.gate = { CGU_REG_OPCR, 31, true }, // disable CCLK stop on idle
clk: Add Ingenic jz4770 CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4770 SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Maarten ter Huurne <maarten@treewalker.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18482/ Signed-off-by: James Hogan <jhogan@kernel.org>
2018-01-16 08:47:56 -07:00
},
[JZ4770_CLK_PCLK] = {
"pclk", CGU_CLK_DIV,
.parents = { JZ4770_CLK_PLL0, },
clk: ingenic/jz4770: Fix incorrect dividers for main clocks The main clocks (cclk, h0clk, h1clk, h2clk, c1clk, pclk) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-05-02 14:25:00 -07:00
.div = {
clk: Support bypassing dividers When a clock is declared as both CGU_CLK_DIV and CGU_CLK_MUX, the CGU code expects the mux to be applied first, the divider second. On the JZ4760, and maybe on some other SoCs, some clocks also have a mux setting and a divider, but the divider is not applied to all parents selectable from the mux. This could be solved by creating two clocks, one with CGU_CLK_DIV and one with CGU_CLK_MUX, but that would increase the number of clocks. Instead, add a 8-bit mask to CGU_CLK_DIV clocks. If the bit corresponding to the parent clock's index is set, the divider is bypassed. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-3-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-05-30 09:49:19 -07:00
CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0,
clk: ingenic/jz4770: Fix incorrect dividers for main clocks The main clocks (cclk, h0clk, h1clk, h2clk, c1clk, pclk) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-05-02 14:25:00 -07:00
jz4770_cgu_cpccr_div_table,
},
clk: Add Ingenic jz4770 CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4770 SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Maarten ter Huurne <maarten@treewalker.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18482/ Signed-off-by: James Hogan <jhogan@kernel.org>
2018-01-16 08:47:56 -07:00
},
/* Those divided clocks can connect to PLL0 or PLL1 */
[JZ4770_CLK_MMC0_MUX] = {
"mmc0_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
.parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
.mux = { CGU_REG_MSC0CDR, 30, 1 },
.div = { CGU_REG_MSC0CDR, 0, 1, 7, -1, -1, 31 },
.gate = { CGU_REG_MSC0CDR, 31 },
},
[JZ4770_CLK_MMC1_MUX] = {
"mmc1_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
.parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
.mux = { CGU_REG_MSC1CDR, 30, 1 },
.div = { CGU_REG_MSC1CDR, 0, 1, 7, -1, -1, 31 },
.gate = { CGU_REG_MSC1CDR, 31 },
},
[JZ4770_CLK_MMC2_MUX] = {
"mmc2_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
.parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
.mux = { CGU_REG_MSC2CDR, 30, 1 },
.div = { CGU_REG_MSC2CDR, 0, 1, 7, -1, -1, 31 },
.gate = { CGU_REG_MSC2CDR, 31 },
},
[JZ4770_CLK_CIM] = {
"cim", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
.parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
.mux = { CGU_REG_CIMCDR, 31, 1 },
.div = { CGU_REG_CIMCDR, 0, 1, 8, -1, -1, -1 },
.gate = { CGU_REG_CLKGR0, 26 },
},
[JZ4770_CLK_UHC] = {
"uhc", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
.parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
.mux = { CGU_REG_UHCCDR, 29, 1 },
.div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 },
.gate = { CGU_REG_CLKGR0, 24 },
},
[JZ4770_CLK_GPU] = {
"gpu", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
.parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, -1 },
.mux = { CGU_REG_GPUCDR, 31, 1 },
.div = { CGU_REG_GPUCDR, 0, 1, 3, -1, -1, -1 },
.gate = { CGU_REG_CLKGR1, 9 },
},
[JZ4770_CLK_BCH] = {
"bch", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
.parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
.mux = { CGU_REG_BCHCDR, 31, 1 },
.div = { CGU_REG_BCHCDR, 0, 1, 3, -1, -1, -1 },
.gate = { CGU_REG_CLKGR0, 1 },
},
[JZ4770_CLK_LPCLK_MUX] = {
"lpclk", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
.parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
.mux = { CGU_REG_LPCDR, 29, 1 },
.div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
.gate = { CGU_REG_CLKGR0, 28 },
},
[JZ4770_CLK_GPS] = {
"gps", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
.parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
.mux = { CGU_REG_GPSCDR, 31, 1 },
.div = { CGU_REG_GPSCDR, 0, 1, 4, -1, -1, -1 },
.gate = { CGU_REG_CLKGR0, 22 },
},
/* Those divided clocks can connect to EXT, PLL0 or PLL1 */
[JZ4770_CLK_SSI_MUX] = {
"ssi_mux", CGU_CLK_DIV | CGU_CLK_MUX,
.parents = { JZ4770_CLK_EXT, -1,
JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 },
.mux = { CGU_REG_SSICDR, 30, 2 },
.div = { CGU_REG_SSICDR, 0, 1, 6, -1, -1, -1 },
},
[JZ4770_CLK_PCM_MUX] = {
"pcm_mux", CGU_CLK_DIV | CGU_CLK_MUX,
.parents = { JZ4770_CLK_EXT, -1,
JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 },
.mux = { CGU_REG_PCMCDR, 30, 2 },
.div = { CGU_REG_PCMCDR, 0, 1, 9, -1, -1, -1 },
},
[JZ4770_CLK_I2S] = {
"i2s", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
.parents = { JZ4770_CLK_EXT, -1,
JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 },
.mux = { CGU_REG_I2SCDR, 30, 2 },
.div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
.gate = { CGU_REG_CLKGR1, 13 },
},
[JZ4770_CLK_OTG] = {
"usb", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
.parents = { JZ4770_CLK_EXT, -1,
JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 },
.mux = { CGU_REG_USBCDR, 30, 2 },
.div = { CGU_REG_USBCDR, 0, 1, 8, -1, -1, -1 },
.gate = { CGU_REG_CLKGR0, 2 },
},
/* Gate-only clocks */
[JZ4770_CLK_SSI0] = {
"ssi0", CGU_CLK_GATE,
.parents = { JZ4770_CLK_SSI_MUX, },
.gate = { CGU_REG_CLKGR0, 4 },
},
[JZ4770_CLK_SSI1] = {
"ssi1", CGU_CLK_GATE,
.parents = { JZ4770_CLK_SSI_MUX, },
.gate = { CGU_REG_CLKGR0, 19 },
},
[JZ4770_CLK_SSI2] = {
"ssi2", CGU_CLK_GATE,
.parents = { JZ4770_CLK_SSI_MUX, },
.gate = { CGU_REG_CLKGR0, 20 },
},
[JZ4770_CLK_PCM0] = {
"pcm0", CGU_CLK_GATE,
.parents = { JZ4770_CLK_PCM_MUX, },
.gate = { CGU_REG_CLKGR1, 8 },
},
[JZ4770_CLK_PCM1] = {
"pcm1", CGU_CLK_GATE,
.parents = { JZ4770_CLK_PCM_MUX, },
.gate = { CGU_REG_CLKGR1, 10 },
},
[JZ4770_CLK_DMA] = {
"dma", CGU_CLK_GATE,
.parents = { JZ4770_CLK_H2CLK, },
.gate = { CGU_REG_CLKGR0, 21 },
},
clk: ingenic: Add MDMA and BDMA clocks The Ingenic JZ4760 and JZ4770 both have an extra DMA core named BDMA dedicated to the NAND and BCH controller, but which can also do memory-to-memory transfers. The JZ4760 additionally has a DMA core named MDMA dedicated to memory-to-memory transfers. The programming manual for the JZ4770 does have a bit for a MDMA clock, but does not seem to have the hardware wired in. Add the BDMA and MDMA clocks to the JZ4760 CGU code, and the BDMA clock to the JZ4770 code, so that the BDMA and MDMA controllers can be used. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20211220193319.114974-3-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-12-20 12:33:19 -07:00
[JZ4770_CLK_BDMA] = {
"bdma", CGU_CLK_GATE,
.parents = { JZ4770_CLK_H2CLK, },
.gate = { CGU_REG_CLKGR1, 0 },
},
clk: Add Ingenic jz4770 CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4770 SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Maarten ter Huurne <maarten@treewalker.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18482/ Signed-off-by: James Hogan <jhogan@kernel.org>
2018-01-16 08:47:56 -07:00
[JZ4770_CLK_I2C0] = {
"i2c0", CGU_CLK_GATE,
.parents = { JZ4770_CLK_EXT, },
.gate = { CGU_REG_CLKGR0, 5 },
},
[JZ4770_CLK_I2C1] = {
"i2c1", CGU_CLK_GATE,
.parents = { JZ4770_CLK_EXT, },
.gate = { CGU_REG_CLKGR0, 6 },
},
[JZ4770_CLK_I2C2] = {
"i2c2", CGU_CLK_GATE,
.parents = { JZ4770_CLK_EXT, },
.gate = { CGU_REG_CLKGR1, 15 },
},
[JZ4770_CLK_UART0] = {
"uart0", CGU_CLK_GATE,
.parents = { JZ4770_CLK_EXT, },
.gate = { CGU_REG_CLKGR0, 15 },
},
[JZ4770_CLK_UART1] = {
"uart1", CGU_CLK_GATE,
.parents = { JZ4770_CLK_EXT, },
.gate = { CGU_REG_CLKGR0, 16 },
},
[JZ4770_CLK_UART2] = {
"uart2", CGU_CLK_GATE,
.parents = { JZ4770_CLK_EXT, },
.gate = { CGU_REG_CLKGR0, 17 },
},
[JZ4770_CLK_UART3] = {
"uart3", CGU_CLK_GATE,
.parents = { JZ4770_CLK_EXT, },
.gate = { CGU_REG_CLKGR0, 18 },
},
[JZ4770_CLK_IPU] = {
"ipu", CGU_CLK_GATE,
.parents = { JZ4770_CLK_H0CLK, },
.gate = { CGU_REG_CLKGR0, 29 },
},
[JZ4770_CLK_ADC] = {
"adc", CGU_CLK_GATE,
.parents = { JZ4770_CLK_EXT, },
.gate = { CGU_REG_CLKGR0, 14 },
},
[JZ4770_CLK_AIC] = {
"aic", CGU_CLK_GATE,
.parents = { JZ4770_CLK_EXT, },
.gate = { CGU_REG_CLKGR0, 8 },
},
[JZ4770_CLK_AUX] = {
"aux", CGU_CLK_GATE,
.parents = { JZ4770_CLK_C1CLK, },
.gate = { CGU_REG_CLKGR1, 14 },
},
[JZ4770_CLK_VPU] = {
"vpu", CGU_CLK_GATE,
.parents = { JZ4770_CLK_H1CLK, },
clk: ingenic: jz4770: Add 150us delay after enabling VPU clock This is required, as we must not use the AHB1 bus before it is stable. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-20 09:31:17 -07:00
.gate = { CGU_REG_LCR, 30, false, 150 },
clk: Add Ingenic jz4770 CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4770 SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Maarten ter Huurne <maarten@treewalker.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18482/ Signed-off-by: James Hogan <jhogan@kernel.org>
2018-01-16 08:47:56 -07:00
},
[JZ4770_CLK_MMC0] = {
"mmc0", CGU_CLK_GATE,
.parents = { JZ4770_CLK_MMC0_MUX, },
.gate = { CGU_REG_CLKGR0, 3 },
},
[JZ4770_CLK_MMC1] = {
"mmc1", CGU_CLK_GATE,
.parents = { JZ4770_CLK_MMC1_MUX, },
.gate = { CGU_REG_CLKGR0, 11 },
},
[JZ4770_CLK_MMC2] = {
"mmc2", CGU_CLK_GATE,
.parents = { JZ4770_CLK_MMC2_MUX, },
.gate = { CGU_REG_CLKGR0, 12 },
},
clk: ingenic: jz4770: Change OTG from custom to standard gated clock We now have the means to express the specificities of the OTG clock with the common CGU code. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-20 09:31:14 -07:00
[JZ4770_CLK_OTG_PHY] = {
"usb_phy", CGU_CLK_GATE,
.parents = { JZ4770_CLK_OTG },
.gate = { CGU_REG_OPCR, 7, true, 50 },
},
clk: Add Ingenic jz4770 CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4770 SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Maarten ter Huurne <maarten@treewalker.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18482/ Signed-off-by: James Hogan <jhogan@kernel.org>
2018-01-16 08:47:56 -07:00
/* Custom clocks */
[JZ4770_CLK_UHC_PHY] = {
"uhc_phy", CGU_CLK_CUSTOM,
.parents = { JZ4770_CLK_UHC, -1, -1, -1 },
.custom = { &jz4770_uhc_phy_ops },
},
[JZ4770_CLK_EXT512] = {
"ext/512", CGU_CLK_FIXDIV,
.parents = { JZ4770_CLK_EXT },
.fixdiv = { 512 },
},
[JZ4770_CLK_RTC] = {
"rtc", CGU_CLK_MUX,
.parents = { JZ4770_CLK_EXT512, JZ4770_CLK_OSC32K, },
.mux = { CGU_REG_OPCR, 2, 1},
},
};
static void __init jz4770_cgu_init(struct device_node *np)
{
int retval;
cgu = ingenic_cgu_new(jz4770_cgu_clocks,
ARRAY_SIZE(jz4770_cgu_clocks), np);
clk: ingenic/jz4770: Exit with error if CGU init failed Exit jz4770_cgu_init() if the 'cgu' pointer we get is NULL, since the pointer is passed as argument to functions later on. Fixes: 7a01c19007ad ("clk: Add Ingenic jz4770 CGU driver") Cc: stable@vger.kernel.org Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reported-by: kbuild test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lkml.kernel.org/r/20200213161952.37460-1-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-02-13 09:19:51 -07:00
if (!cgu) {
clk: Add Ingenic jz4770 CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4770 SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Maarten ter Huurne <maarten@treewalker.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18482/ Signed-off-by: James Hogan <jhogan@kernel.org>
2018-01-16 08:47:56 -07:00
pr_err("%s: failed to initialise CGU\n", __func__);
clk: ingenic/jz4770: Exit with error if CGU init failed Exit jz4770_cgu_init() if the 'cgu' pointer we get is NULL, since the pointer is passed as argument to functions later on. Fixes: 7a01c19007ad ("clk: Add Ingenic jz4770 CGU driver") Cc: stable@vger.kernel.org Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reported-by: kbuild test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lkml.kernel.org/r/20200213161952.37460-1-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-02-13 09:19:51 -07:00
return;
}
clk: Add Ingenic jz4770 CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4770 SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Maarten ter Huurne <maarten@treewalker.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18482/ Signed-off-by: James Hogan <jhogan@kernel.org>
2018-01-16 08:47:56 -07:00
retval = ingenic_cgu_register_clocks(cgu);
if (retval)
pr_err("%s: failed to register CGU Clocks\n", __func__);
clk: ingenic: Handle setting the Low-Power Mode bit The Low-Power Mode, when enabled, will make the "wait" MIPS instruction suspend the system. This is not really clock-related, but this bit happens to be in the register set of the CGU. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-11 11:07:54 -07:00
ingenic_cgu_register_syscore_ops(cgu);
clk: Add Ingenic jz4770 CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4770 SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Maarten ter Huurne <maarten@treewalker.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18482/ Signed-off-by: James Hogan <jhogan@kernel.org>
2018-01-16 08:47:56 -07:00
}
/* We only probe via devicetree, no need for a platform driver */
clk: ingenic: Use CLK_OF_DECLARE_DRIVER macro By using CLK_OF_DECLARE_DRIVER instead of the CLK_OF_DECLARE macro, we allow the driver to probe also as a platform driver. While this driver does not have code to probe as a platform driver, this is still useful for probing children devices in the case where the device node is compatible with "simple-mfd". Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lkml.kernel.org/r/20190810123620.27238-1-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-10 05:36:20 -07:00
CLK_OF_DECLARE_DRIVER(jz4770_cgu, "ingenic,jz4770-cgu", jz4770_cgu_init);
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