2017-11-01 07:09:13 -07:00
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/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
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2012-10-09 01:47:26 -07:00
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/*
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* ELF register definitions..
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _UAPI_ASM_POWERPC_ELF_H
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#define _UAPI_ASM_POWERPC_ELF_H
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#include <linux/types.h>
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#include <asm/ptrace.h>
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#include <asm/cputable.h>
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#include <asm/auxvec.h>
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/* PowerPC relocations defined by the ABIs */
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#define R_PPC_NONE 0
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#define R_PPC_ADDR32 1 /* 32bit absolute address */
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#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */
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#define R_PPC_ADDR16 3 /* 16bit absolute address */
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#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */
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#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */
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#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */
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#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */
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#define R_PPC_ADDR14_BRTAKEN 8
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#define R_PPC_ADDR14_BRNTAKEN 9
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#define R_PPC_REL24 10 /* PC relative 26 bit */
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#define R_PPC_REL14 11 /* PC relative 16 bit */
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#define R_PPC_REL14_BRTAKEN 12
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#define R_PPC_REL14_BRNTAKEN 13
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#define R_PPC_GOT16 14
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#define R_PPC_GOT16_LO 15
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#define R_PPC_GOT16_HI 16
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#define R_PPC_GOT16_HA 17
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#define R_PPC_PLTREL24 18
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#define R_PPC_COPY 19
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#define R_PPC_GLOB_DAT 20
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#define R_PPC_JMP_SLOT 21
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#define R_PPC_RELATIVE 22
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#define R_PPC_LOCAL24PC 23
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#define R_PPC_UADDR32 24
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#define R_PPC_UADDR16 25
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#define R_PPC_REL32 26
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#define R_PPC_PLT32 27
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#define R_PPC_PLTREL32 28
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#define R_PPC_PLT16_LO 29
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#define R_PPC_PLT16_HI 30
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#define R_PPC_PLT16_HA 31
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#define R_PPC_SDAREL16 32
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#define R_PPC_SECTOFF 33
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#define R_PPC_SECTOFF_LO 34
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#define R_PPC_SECTOFF_HI 35
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#define R_PPC_SECTOFF_HA 36
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/* PowerPC relocations defined for the TLS access ABI. */
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#define R_PPC_TLS 67 /* none (sym+add)@tls */
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#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */
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#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */
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#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */
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#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */
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#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */
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#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */
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#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */
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#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */
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#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */
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#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */
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#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */
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#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */
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#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */
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#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */
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#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */
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#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */
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#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */
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#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */
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#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */
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#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */
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#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */
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#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */
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#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */
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#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */
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#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */
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#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */
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#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */
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/* keep this the last entry. */
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#define R_PPC_NUM 95
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#define ELF_NGREG 48 /* includes nip, msr, lr, etc. */
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#define ELF_NFPREG 33 /* includes fpscr */
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2016-07-27 19:57:38 -07:00
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#define ELF_NVMX 34 /* includes all vector registers */
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2016-07-27 19:57:39 -07:00
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#define ELF_NVSX 32 /* includes all VSX registers */
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2016-07-27 19:57:40 -07:00
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#define ELF_NTMSPRREG 3 /* include tfhar, tfiar, texasr */
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2016-07-27 19:57:44 -07:00
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#define ELF_NEBB 3 /* includes ebbrr, ebbhr, bescr */
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#define ELF_NPMU 5 /* includes siar, sdar, sier, mmcr2, mmcr0 */
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2018-01-18 18:50:43 -07:00
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#define ELF_NPKEY 3 /* includes amr, iamr, uamor */
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2023-06-19 00:36:26 -07:00
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#define ELF_NDEXCR 2 /* includes dexcr, hdexcr */
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2023-06-19 00:36:26 -07:00
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#define ELF_NHASHKEYR 1 /* includes hashkeyr */
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2012-10-09 01:47:26 -07:00
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typedef unsigned long elf_greg_t64;
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typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];
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typedef unsigned int elf_greg_t32;
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typedef elf_greg_t32 elf_gregset_t32[ELF_NGREG];
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typedef elf_gregset_t32 compat_elf_gregset_t;
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/*
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* ELF_ARCH, CLASS, and DATA are used to set parameters in the core dumps.
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*/
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#ifdef __powerpc64__
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# define ELF_NVRREG32 33 /* includes vscr & vrsave stuffed together */
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# define ELF_NVRREG 34 /* includes vscr & vrsave in split vectors */
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# define ELF_NVSRHALFREG 32 /* Half the vsx registers */
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# define ELF_GREG_TYPE elf_greg_t64
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# define ELF_ARCH EM_PPC64
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# define ELF_CLASS ELFCLASS64
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typedef elf_greg_t64 elf_greg_t;
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typedef elf_gregset_t64 elf_gregset_t;
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2012-10-09 01:47:26 -07:00
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#else
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# define ELF_NEVRREG 34 /* includes acc (as 2) */
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# define ELF_NVRREG 33 /* includes vscr */
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# define ELF_GREG_TYPE elf_greg_t32
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# define ELF_ARCH EM_PPC
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# define ELF_CLASS ELFCLASS32
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typedef elf_greg_t32 elf_greg_t;
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typedef elf_gregset_t32 elf_gregset_t;
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2012-10-09 01:47:26 -07:00
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#endif /* __powerpc64__ */
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2013-08-06 09:01:50 -07:00
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#ifdef __BIG_ENDIAN__
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#define ELF_DATA ELFDATA2MSB
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#else
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#define ELF_DATA ELFDATA2LSB
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#endif
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2012-10-09 01:47:26 -07:00
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/* Floating point registers */
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typedef double elf_fpreg_t;
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typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
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/* Altivec registers */
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/*
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* The entries with indexes 0-31 contain the corresponding vector registers.
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* The entry with index 32 contains the vscr as the last word (offset 12)
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* within the quadword. This allows the vscr to be stored as either a
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* quadword (since it must be copied via a vector register to/from storage)
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* or as a word.
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*
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* 64-bit kernel notes: The entry at index 33 contains the vrsave as the first
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* word (offset 0) within the quadword.
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*
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* This definition of the VMX state is compatible with the current PPC32
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* ptrace interface. This allows signal handling and ptrace to use the same
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* structures. This also simplifies the implementation of a bi-arch
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* (combined (32- and 64-bit) gdb.
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*
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* Note that it's _not_ compatible with 32 bits ucontext which stuffs the
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* vrsave along with vscr and so only uses 33 vectors for the register set
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*/
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typedef __vector128 elf_vrreg_t;
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typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG];
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#ifdef __powerpc64__
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typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32];
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typedef elf_fpreg_t elf_vsrreghalf_t32[ELF_NVSRHALFREG];
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#endif
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/* PowerPC64 relocations defined by the ABIs */
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#define R_PPC64_NONE R_PPC_NONE
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#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address. */
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#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned. */
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#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address. */
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#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of abs. address. */
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#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of abs. address. */
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#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */
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#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned. */
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#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN
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#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN
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#define R_PPC64_REL24 R_PPC_REL24 /* PC relative 26 bit, word aligned. */
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#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit. */
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#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN
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#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN
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#define R_PPC64_GOT16 R_PPC_GOT16
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#define R_PPC64_GOT16_LO R_PPC_GOT16_LO
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#define R_PPC64_GOT16_HI R_PPC_GOT16_HI
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#define R_PPC64_GOT16_HA R_PPC_GOT16_HA
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#define R_PPC64_COPY R_PPC_COPY
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#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT
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#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT
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#define R_PPC64_RELATIVE R_PPC_RELATIVE
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#define R_PPC64_UADDR32 R_PPC_UADDR32
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#define R_PPC64_UADDR16 R_PPC_UADDR16
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#define R_PPC64_REL32 R_PPC_REL32
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#define R_PPC64_PLT32 R_PPC_PLT32
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#define R_PPC64_PLTREL32 R_PPC_PLTREL32
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#define R_PPC64_PLT16_LO R_PPC_PLT16_LO
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#define R_PPC64_PLT16_HI R_PPC_PLT16_HI
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#define R_PPC64_PLT16_HA R_PPC_PLT16_HA
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#define R_PPC64_SECTOFF R_PPC_SECTOFF
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#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO
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#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI
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#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA
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#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2. */
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#define R_PPC64_ADDR64 38 /* doubleword64 S + A. */
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#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A). */
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#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A). */
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#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A). */
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#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A). */
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#define R_PPC64_UADDR64 43 /* doubleword64 S + A. */
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#define R_PPC64_REL64 44 /* doubleword64 S + A - P. */
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#define R_PPC64_PLT64 45 /* doubleword64 L + A. */
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#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P. */
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#define R_PPC64_TOC16 47 /* half16* S + A - .TOC. */
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#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.). */
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#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.). */
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#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.). */
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#define R_PPC64_TOC 51 /* doubleword64 .TOC. */
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#define R_PPC64_PLTGOT16 52 /* half16* M + A. */
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#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A). */
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#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A). */
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#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A). */
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#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2. */
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#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2. */
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#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2. */
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#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2. */
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#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2. */
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#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2. */
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#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2. */
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#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2. */
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#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2. */
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#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2. */
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#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2. */
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/* PowerPC64 relocations defined for the TLS access ABI. */
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#define R_PPC64_TLS 67 /* none (sym+add)@tls */
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#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */
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#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */
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#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */
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#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */
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#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */
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#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */
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#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */
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#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */
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#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */
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#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */
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#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */
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#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */
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#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */
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#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */
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#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */
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#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */
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#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */
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#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */
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#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */
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#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */
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#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */
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#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */
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#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */
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#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */
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#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */
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#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */
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#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */
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#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */
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#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */
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#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */
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#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */
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#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */
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#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */
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#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */
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#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */
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#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */
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#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */
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#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */
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#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */
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2014-03-18 00:06:28 -07:00
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#define R_PPC64_TLSGD 107
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#define R_PPC64_TLSLD 108
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#define R_PPC64_TOCSAVE 109
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2012-10-09 01:47:26 -07:00
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2023-04-07 19:17:52 -07:00
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#define R_PPC64_REL24_NOTOC 116
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powerpc/module: Handle R_PPC64_ENTRY relocations
GCC 6 will include changes to generated code with -mcmodel=large,
which is used to build kernel modules on powerpc64le. This was
necessary because the large model is supposed to allow arbitrary
sizes and locations of the code and data sections, but the ELFv2
global entry point prolog still made the unconditional assumption
that the TOC associated with any particular function can be found
within 2 GB of the function entry point:
func:
addis r2,r12,(.TOC.-func)@ha
addi r2,r2,(.TOC.-func)@l
.localentry func, .-func
To remove this assumption, GCC will now generate instead this global
entry point prolog sequence when using -mcmodel=large:
.quad .TOC.-func
func:
.reloc ., R_PPC64_ENTRY
ld r2, -8(r12)
add r2, r2, r12
.localentry func, .-func
The new .reloc triggers an optimization in the linker that will
replace this new prolog with the original code (see above) if the
linker determines that the distance between .TOC. and func is in
range after all.
Since this new relocation is now present in module object files,
the kernel module loader is required to handle them too. This
patch adds support for the new relocation and implements the
same optimization done by the GNU linker.
Cc: stable@vger.kernel.org
Signed-off-by: Ulrich Weigand <ulrich.weigand@de.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-01-12 05:14:23 -07:00
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#define R_PPC64_ENTRY 118
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2023-04-07 19:17:52 -07:00
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#define R_PPC64_PCREL34 132
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#define R_PPC64_GOT_PCREL34 133
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2014-03-18 02:29:27 -07:00
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#define R_PPC64_REL16 249
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#define R_PPC64_REL16_LO 250
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#define R_PPC64_REL16_HI 251
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#define R_PPC64_REL16_HA 252
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2012-10-09 01:47:26 -07:00
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/* Keep this the last entry. */
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2014-03-18 02:29:27 -07:00
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#define R_PPC64_NUM 253
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2012-10-09 01:47:26 -07:00
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#endif /* _UAPI_ASM_POWERPC_ELF_H */
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