MIPS: emulate CPUCFG instruction on older Loongson64 cores
CPUCFG is the instruction for querying processor characteristics on
newer Loongson processors, much like CPUID of x86. Since the instruction
is supposedly designed to provide a unified way to do feature detection
(without having to, for example, parse /proc/cpuinfo which is too
heavyweight), it is important to provide compatibility for older cores
without native support. Fortunately, most of the fields can be
synthesized without changes to semantics. Performance is not really big
a concern, because feature detection logic is not expected to be
invoked very often in typical userland applications.
The instruction can't be emulated on LOONGSON_2EF cores, according to
FlyGoat's experiments. Because the LWC2 opcode is assigned to other
valid instructions on 2E and 2F, no RI exception is raised for us to
intercept. So compatibility is only extended back furthest to
Loongson-3A1000. Loongson-2K is covered too, as it is basically a remix
of various blocks from the 3A/3B models from a kernel perspective.
This is lightly based on Loongson's work on their Linux 3.10 fork, for
being the authority on the right feature flags to fill in, where things
aren't otherwise discoverable.
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-23 06:37:01 -07:00
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// SPDX-License-Identifier: GPL-2.0
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#include <linux/smp.h>
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#include <linux/types.h>
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#include <asm/cpu.h>
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#include <asm/cpu-info.h>
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MIPS: Expose Loongson CPUCFG availability via HWCAP
The point is to allow userspace to probe for CPUCFG without possibly
triggering invalid instructions. In addition to that, future Loongson
feature bits could all be stuffed into CPUCFG bit fields (or "leaves"
in x86-speak) if Loongson does not make mistakes, so ELF HWCAP bits are
conserved.
Userspace can determine native CPUCFG availability by checking the LCSRP
(Loongson CSR Present) bit in CPUCFG output after seeing CPUCFG bit in
HWCAP. Native CPUCFG always sets the LCSRP bit, as CPUCFG is part of the
Loongson CSR ASE, while the emulation intentionally leaves this bit
clear.
The other existing Loongson-specific HWCAP bits are, to my best
knowledge, unused, as
(1) they are fairly recent additions,
(2) Loongson never back-ported the patch into their kernel fork, and
(3) Loongson's existing installed base rarely upgrade, if ever;
However, they are still considered userspace ABI, hence unfortunately
unremovable. But hopefully at least we could stop adding new Loongson
HWCAP bits in the future.
Cc: Paul Burton <paulburton@kernel.org>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Huacai Chen <chenhc@lemote.com>
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-30 00:32:42 -07:00
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#include <asm/elf.h>
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MIPS: emulate CPUCFG instruction on older Loongson64 cores
CPUCFG is the instruction for querying processor characteristics on
newer Loongson processors, much like CPUID of x86. Since the instruction
is supposedly designed to provide a unified way to do feature detection
(without having to, for example, parse /proc/cpuinfo which is too
heavyweight), it is important to provide compatibility for older cores
without native support. Fortunately, most of the fields can be
synthesized without changes to semantics. Performance is not really big
a concern, because feature detection logic is not expected to be
invoked very often in typical userland applications.
The instruction can't be emulated on LOONGSON_2EF cores, according to
FlyGoat's experiments. Because the LWC2 opcode is assigned to other
valid instructions on 2E and 2F, no RI exception is raised for us to
intercept. So compatibility is only extended back furthest to
Loongson-3A1000. Loongson-2K is covered too, as it is basically a remix
of various blocks from the 3A/3B models from a kernel perspective.
This is lightly based on Loongson's work on their Linux 3.10 fork, for
being the authority on the right feature flags to fill in, where things
aren't otherwise discoverable.
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-23 06:37:01 -07:00
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#include <loongson_regs.h>
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#include <cpucfg-emul.h>
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static bool is_loongson(struct cpuinfo_mips *c)
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{
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switch (c->processor_id & PRID_COMP_MASK) {
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case PRID_COMP_LEGACY:
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return ((c->processor_id & PRID_IMP_MASK) ==
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PRID_IMP_LOONGSON_64C);
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case PRID_COMP_LOONGSON:
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return true;
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default:
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return false;
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}
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}
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static u32 get_loongson_fprev(struct cpuinfo_mips *c)
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{
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return c->fpu_id & LOONGSON_FPREV_MASK;
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}
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static bool cpu_has_uca(void)
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{
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u32 diag = read_c0_diag();
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u32 new_diag;
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if (diag & LOONGSON_DIAG_UCAC)
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/* UCA is already enabled. */
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return true;
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/* See if UCAC bit can be flipped on. This should be safe. */
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new_diag = diag | LOONGSON_DIAG_UCAC;
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write_c0_diag(new_diag);
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new_diag = read_c0_diag();
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write_c0_diag(diag);
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return (new_diag & LOONGSON_DIAG_UCAC) != 0;
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}
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static void probe_uca(struct cpuinfo_mips *c)
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{
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if (cpu_has_uca())
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c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_LSUCA;
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}
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static void decode_loongson_config6(struct cpuinfo_mips *c)
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{
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u32 config6 = read_c0_config6();
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2020-06-17 05:34:42 -07:00
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if (config6 & LOONGSON_CONF6_SFBEN)
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MIPS: emulate CPUCFG instruction on older Loongson64 cores
CPUCFG is the instruction for querying processor characteristics on
newer Loongson processors, much like CPUID of x86. Since the instruction
is supposedly designed to provide a unified way to do feature detection
(without having to, for example, parse /proc/cpuinfo which is too
heavyweight), it is important to provide compatibility for older cores
without native support. Fortunately, most of the fields can be
synthesized without changes to semantics. Performance is not really big
a concern, because feature detection logic is not expected to be
invoked very often in typical userland applications.
The instruction can't be emulated on LOONGSON_2EF cores, according to
FlyGoat's experiments. Because the LWC2 opcode is assigned to other
valid instructions on 2E and 2F, no RI exception is raised for us to
intercept. So compatibility is only extended back furthest to
Loongson-3A1000. Loongson-2K is covered too, as it is basically a remix
of various blocks from the 3A/3B models from a kernel perspective.
This is lightly based on Loongson's work on their Linux 3.10 fork, for
being the authority on the right feature flags to fill in, where things
aren't otherwise discoverable.
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-23 06:37:01 -07:00
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c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_SFBP;
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2020-06-17 05:34:42 -07:00
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if (config6 & LOONGSON_CONF6_LLEXC)
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MIPS: emulate CPUCFG instruction on older Loongson64 cores
CPUCFG is the instruction for querying processor characteristics on
newer Loongson processors, much like CPUID of x86. Since the instruction
is supposedly designed to provide a unified way to do feature detection
(without having to, for example, parse /proc/cpuinfo which is too
heavyweight), it is important to provide compatibility for older cores
without native support. Fortunately, most of the fields can be
synthesized without changes to semantics. Performance is not really big
a concern, because feature detection logic is not expected to be
invoked very often in typical userland applications.
The instruction can't be emulated on LOONGSON_2EF cores, according to
FlyGoat's experiments. Because the LWC2 opcode is assigned to other
valid instructions on 2E and 2F, no RI exception is raised for us to
intercept. So compatibility is only extended back furthest to
Loongson-3A1000. Loongson-2K is covered too, as it is basically a remix
of various blocks from the 3A/3B models from a kernel perspective.
This is lightly based on Loongson's work on their Linux 3.10 fork, for
being the authority on the right feature flags to fill in, where things
aren't otherwise discoverable.
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-23 06:37:01 -07:00
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c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_LLEXC;
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2020-06-17 05:34:42 -07:00
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if (config6 & LOONGSON_CONF6_SCRAND)
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MIPS: emulate CPUCFG instruction on older Loongson64 cores
CPUCFG is the instruction for querying processor characteristics on
newer Loongson processors, much like CPUID of x86. Since the instruction
is supposedly designed to provide a unified way to do feature detection
(without having to, for example, parse /proc/cpuinfo which is too
heavyweight), it is important to provide compatibility for older cores
without native support. Fortunately, most of the fields can be
synthesized without changes to semantics. Performance is not really big
a concern, because feature detection logic is not expected to be
invoked very often in typical userland applications.
The instruction can't be emulated on LOONGSON_2EF cores, according to
FlyGoat's experiments. Because the LWC2 opcode is assigned to other
valid instructions on 2E and 2F, no RI exception is raised for us to
intercept. So compatibility is only extended back furthest to
Loongson-3A1000. Loongson-2K is covered too, as it is basically a remix
of various blocks from the 3A/3B models from a kernel perspective.
This is lightly based on Loongson's work on their Linux 3.10 fork, for
being the authority on the right feature flags to fill in, where things
aren't otherwise discoverable.
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-23 06:37:01 -07:00
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c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_SCRAND;
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}
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static void patch_cpucfg_sel1(struct cpuinfo_mips *c)
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{
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u64 ases = c->ases;
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u64 options = c->options;
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u32 data = c->loongson3_cpucfg_data[0];
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if (options & MIPS_CPU_FPU) {
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data |= LOONGSON_CFG1_FP;
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data |= get_loongson_fprev(c) << LOONGSON_CFG1_FPREV_OFFSET;
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}
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if (ases & MIPS_ASE_LOONGSON_MMI)
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data |= LOONGSON_CFG1_MMI;
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if (ases & MIPS_ASE_MSA)
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data |= LOONGSON_CFG1_MSA1;
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c->loongson3_cpucfg_data[0] = data;
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}
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static void patch_cpucfg_sel2(struct cpuinfo_mips *c)
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{
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u64 ases = c->ases;
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u64 options = c->options;
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u32 data = c->loongson3_cpucfg_data[1];
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if (ases & MIPS_ASE_LOONGSON_EXT)
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data |= LOONGSON_CFG2_LEXT1;
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if (ases & MIPS_ASE_LOONGSON_EXT2)
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data |= LOONGSON_CFG2_LEXT2;
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if (options & MIPS_CPU_LDPTE)
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data |= LOONGSON_CFG2_LSPW;
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if (ases & MIPS_ASE_VZ)
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data |= LOONGSON_CFG2_LVZP;
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else
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data &= ~LOONGSON_CFG2_LVZREV;
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c->loongson3_cpucfg_data[1] = data;
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}
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static void patch_cpucfg_sel3(struct cpuinfo_mips *c)
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{
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u64 ases = c->ases;
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u32 data = c->loongson3_cpucfg_data[2];
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if (ases & MIPS_ASE_LOONGSON_CAM) {
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data |= LOONGSON_CFG3_LCAMP;
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} else {
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data &= ~LOONGSON_CFG3_LCAMREV;
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data &= ~LOONGSON_CFG3_LCAMNUM;
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data &= ~LOONGSON_CFG3_LCAMKW;
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data &= ~LOONGSON_CFG3_LCAMVW;
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}
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c->loongson3_cpucfg_data[2] = data;
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}
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void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
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{
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/* Only engage the logic on Loongson processors. */
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if (!is_loongson(c))
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return;
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/* CPUs with CPUCFG support don't need to synthesize anything. */
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if (cpu_has_cfg())
|
MIPS: Expose Loongson CPUCFG availability via HWCAP
The point is to allow userspace to probe for CPUCFG without possibly
triggering invalid instructions. In addition to that, future Loongson
feature bits could all be stuffed into CPUCFG bit fields (or "leaves"
in x86-speak) if Loongson does not make mistakes, so ELF HWCAP bits are
conserved.
Userspace can determine native CPUCFG availability by checking the LCSRP
(Loongson CSR Present) bit in CPUCFG output after seeing CPUCFG bit in
HWCAP. Native CPUCFG always sets the LCSRP bit, as CPUCFG is part of the
Loongson CSR ASE, while the emulation intentionally leaves this bit
clear.
The other existing Loongson-specific HWCAP bits are, to my best
knowledge, unused, as
(1) they are fairly recent additions,
(2) Loongson never back-ported the patch into their kernel fork, and
(3) Loongson's existing installed base rarely upgrade, if ever;
However, they are still considered userspace ABI, hence unfortunately
unremovable. But hopefully at least we could stop adding new Loongson
HWCAP bits in the future.
Cc: Paul Burton <paulburton@kernel.org>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Huacai Chen <chenhc@lemote.com>
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-30 00:32:42 -07:00
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goto have_cpucfg_now;
|
MIPS: emulate CPUCFG instruction on older Loongson64 cores
CPUCFG is the instruction for querying processor characteristics on
newer Loongson processors, much like CPUID of x86. Since the instruction
is supposedly designed to provide a unified way to do feature detection
(without having to, for example, parse /proc/cpuinfo which is too
heavyweight), it is important to provide compatibility for older cores
without native support. Fortunately, most of the fields can be
synthesized without changes to semantics. Performance is not really big
a concern, because feature detection logic is not expected to be
invoked very often in typical userland applications.
The instruction can't be emulated on LOONGSON_2EF cores, according to
FlyGoat's experiments. Because the LWC2 opcode is assigned to other
valid instructions on 2E and 2F, no RI exception is raised for us to
intercept. So compatibility is only extended back furthest to
Loongson-3A1000. Loongson-2K is covered too, as it is basically a remix
of various blocks from the 3A/3B models from a kernel perspective.
This is lightly based on Loongson's work on their Linux 3.10 fork, for
being the authority on the right feature flags to fill in, where things
aren't otherwise discoverable.
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-23 06:37:01 -07:00
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c->loongson3_cpucfg_data[0] = 0;
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c->loongson3_cpucfg_data[1] = 0;
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c->loongson3_cpucfg_data[2] = 0;
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2020-05-30 00:32:41 -07:00
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/* Add CPUCFG features non-discoverable otherwise. */
|
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switch (c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) {
|
2020-05-30 00:32:43 -07:00
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case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_0:
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case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_1:
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case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_2:
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case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_3:
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decode_loongson_config6(c);
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probe_uca(c);
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c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
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LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LLSYNC |
|
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LOONGSON_CFG1_TGTSYNC);
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|
c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 |
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LOONGSON_CFG2_LBT2 | LOONGSON_CFG2_LPMP |
|
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|
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LOONGSON_CFG2_LPM_REV2);
|
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|
c->loongson3_cpucfg_data[2] = 0;
|
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|
break;
|
|
|
|
|
|
2020-05-30 00:32:41 -07:00
|
|
|
case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R1:
|
MIPS: emulate CPUCFG instruction on older Loongson64 cores
CPUCFG is the instruction for querying processor characteristics on
newer Loongson processors, much like CPUID of x86. Since the instruction
is supposedly designed to provide a unified way to do feature detection
(without having to, for example, parse /proc/cpuinfo which is too
heavyweight), it is important to provide compatibility for older cores
without native support. Fortunately, most of the fields can be
synthesized without changes to semantics. Performance is not really big
a concern, because feature detection logic is not expected to be
invoked very often in typical userland applications.
The instruction can't be emulated on LOONGSON_2EF cores, according to
FlyGoat's experiments. Because the LWC2 opcode is assigned to other
valid instructions on 2E and 2F, no RI exception is raised for us to
intercept. So compatibility is only extended back furthest to
Loongson-3A1000. Loongson-2K is covered too, as it is basically a remix
of various blocks from the 3A/3B models from a kernel perspective.
This is lightly based on Loongson's work on their Linux 3.10 fork, for
being the authority on the right feature flags to fill in, where things
aren't otherwise discoverable.
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-23 06:37:01 -07:00
|
|
|
c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
|
|
|
|
|
LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LSUCA |
|
|
|
|
|
LOONGSON_CFG1_LLSYNC | LOONGSON_CFG1_TGTSYNC);
|
|
|
|
|
c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 |
|
|
|
|
|
LOONGSON_CFG2_LPMP | LOONGSON_CFG2_LPM_REV1);
|
|
|
|
|
c->loongson3_cpucfg_data[2] |= (
|
|
|
|
|
LOONGSON_CFG3_LCAM_REV1 |
|
|
|
|
|
LOONGSON_CFG3_LCAMNUM_REV1 |
|
|
|
|
|
LOONGSON_CFG3_LCAMKW_REV1 |
|
|
|
|
|
LOONGSON_CFG3_LCAMVW_REV1);
|
|
|
|
|
break;
|
|
|
|
|
|
2020-05-30 00:32:41 -07:00
|
|
|
case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3B_R1:
|
|
|
|
|
case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3B_R2:
|
MIPS: emulate CPUCFG instruction on older Loongson64 cores
CPUCFG is the instruction for querying processor characteristics on
newer Loongson processors, much like CPUID of x86. Since the instruction
is supposedly designed to provide a unified way to do feature detection
(without having to, for example, parse /proc/cpuinfo which is too
heavyweight), it is important to provide compatibility for older cores
without native support. Fortunately, most of the fields can be
synthesized without changes to semantics. Performance is not really big
a concern, because feature detection logic is not expected to be
invoked very often in typical userland applications.
The instruction can't be emulated on LOONGSON_2EF cores, according to
FlyGoat's experiments. Because the LWC2 opcode is assigned to other
valid instructions on 2E and 2F, no RI exception is raised for us to
intercept. So compatibility is only extended back furthest to
Loongson-3A1000. Loongson-2K is covered too, as it is basically a remix
of various blocks from the 3A/3B models from a kernel perspective.
This is lightly based on Loongson's work on their Linux 3.10 fork, for
being the authority on the right feature flags to fill in, where things
aren't otherwise discoverable.
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-23 06:37:01 -07:00
|
|
|
c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
|
|
|
|
|
LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LSUCA |
|
|
|
|
|
LOONGSON_CFG1_LLSYNC | LOONGSON_CFG1_TGTSYNC);
|
|
|
|
|
c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 |
|
|
|
|
|
LOONGSON_CFG2_LPMP | LOONGSON_CFG2_LPM_REV1);
|
|
|
|
|
c->loongson3_cpucfg_data[2] |= (
|
|
|
|
|
LOONGSON_CFG3_LCAM_REV1 |
|
|
|
|
|
LOONGSON_CFG3_LCAMNUM_REV1 |
|
|
|
|
|
LOONGSON_CFG3_LCAMKW_REV1 |
|
|
|
|
|
LOONGSON_CFG3_LCAMVW_REV1);
|
|
|
|
|
break;
|
|
|
|
|
|
2020-05-30 00:32:41 -07:00
|
|
|
case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0:
|
|
|
|
|
case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_1:
|
|
|
|
|
case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R3_0:
|
|
|
|
|
case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R3_1:
|
MIPS: emulate CPUCFG instruction on older Loongson64 cores
CPUCFG is the instruction for querying processor characteristics on
newer Loongson processors, much like CPUID of x86. Since the instruction
is supposedly designed to provide a unified way to do feature detection
(without having to, for example, parse /proc/cpuinfo which is too
heavyweight), it is important to provide compatibility for older cores
without native support. Fortunately, most of the fields can be
synthesized without changes to semantics. Performance is not really big
a concern, because feature detection logic is not expected to be
invoked very often in typical userland applications.
The instruction can't be emulated on LOONGSON_2EF cores, according to
FlyGoat's experiments. Because the LWC2 opcode is assigned to other
valid instructions on 2E and 2F, no RI exception is raised for us to
intercept. So compatibility is only extended back furthest to
Loongson-3A1000. Loongson-2K is covered too, as it is basically a remix
of various blocks from the 3A/3B models from a kernel perspective.
This is lightly based on Loongson's work on their Linux 3.10 fork, for
being the authority on the right feature flags to fill in, where things
aren't otherwise discoverable.
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-23 06:37:01 -07:00
|
|
|
decode_loongson_config6(c);
|
|
|
|
|
probe_uca(c);
|
|
|
|
|
|
|
|
|
|
c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_CNT64 |
|
|
|
|
|
LOONGSON_CFG1_LSLDR0 | LOONGSON_CFG1_LSPREF |
|
|
|
|
|
LOONGSON_CFG1_LSPREFX | LOONGSON_CFG1_LSSYNCI |
|
|
|
|
|
LOONGSON_CFG1_LLSYNC | LOONGSON_CFG1_TGTSYNC);
|
|
|
|
|
c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 |
|
|
|
|
|
LOONGSON_CFG2_LBT2 | LOONGSON_CFG2_LBTMMU |
|
|
|
|
|
LOONGSON_CFG2_LPMP | LOONGSON_CFG2_LPM_REV1 |
|
|
|
|
|
LOONGSON_CFG2_LVZ_REV1);
|
|
|
|
|
c->loongson3_cpucfg_data[2] |= (LOONGSON_CFG3_LCAM_REV1 |
|
|
|
|
|
LOONGSON_CFG3_LCAMNUM_REV1 |
|
|
|
|
|
LOONGSON_CFG3_LCAMKW_REV1 |
|
|
|
|
|
LOONGSON_CFG3_LCAMVW_REV1);
|
|
|
|
|
break;
|
2020-05-30 00:32:41 -07:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
/* It is possible that some future Loongson cores still do
|
|
|
|
|
* not have CPUCFG, so do not emulate anything for these
|
|
|
|
|
* cores.
|
|
|
|
|
*/
|
|
|
|
|
return;
|
MIPS: emulate CPUCFG instruction on older Loongson64 cores
CPUCFG is the instruction for querying processor characteristics on
newer Loongson processors, much like CPUID of x86. Since the instruction
is supposedly designed to provide a unified way to do feature detection
(without having to, for example, parse /proc/cpuinfo which is too
heavyweight), it is important to provide compatibility for older cores
without native support. Fortunately, most of the fields can be
synthesized without changes to semantics. Performance is not really big
a concern, because feature detection logic is not expected to be
invoked very often in typical userland applications.
The instruction can't be emulated on LOONGSON_2EF cores, according to
FlyGoat's experiments. Because the LWC2 opcode is assigned to other
valid instructions on 2E and 2F, no RI exception is raised for us to
intercept. So compatibility is only extended back furthest to
Loongson-3A1000. Loongson-2K is covered too, as it is basically a remix
of various blocks from the 3A/3B models from a kernel perspective.
This is lightly based on Loongson's work on their Linux 3.10 fork, for
being the authority on the right feature flags to fill in, where things
aren't otherwise discoverable.
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-23 06:37:01 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* This feature is set by firmware, but all known Loongson-64 systems
|
|
|
|
|
* are configured this way.
|
|
|
|
|
*/
|
|
|
|
|
c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_CDMAP;
|
|
|
|
|
|
|
|
|
|
/* Patch in dynamically probed bits. */
|
|
|
|
|
patch_cpucfg_sel1(c);
|
|
|
|
|
patch_cpucfg_sel2(c);
|
|
|
|
|
patch_cpucfg_sel3(c);
|
MIPS: Expose Loongson CPUCFG availability via HWCAP
The point is to allow userspace to probe for CPUCFG without possibly
triggering invalid instructions. In addition to that, future Loongson
feature bits could all be stuffed into CPUCFG bit fields (or "leaves"
in x86-speak) if Loongson does not make mistakes, so ELF HWCAP bits are
conserved.
Userspace can determine native CPUCFG availability by checking the LCSRP
(Loongson CSR Present) bit in CPUCFG output after seeing CPUCFG bit in
HWCAP. Native CPUCFG always sets the LCSRP bit, as CPUCFG is part of the
Loongson CSR ASE, while the emulation intentionally leaves this bit
clear.
The other existing Loongson-specific HWCAP bits are, to my best
knowledge, unused, as
(1) they are fairly recent additions,
(2) Loongson never back-ported the patch into their kernel fork, and
(3) Loongson's existing installed base rarely upgrade, if ever;
However, they are still considered userspace ABI, hence unfortunately
unremovable. But hopefully at least we could stop adding new Loongson
HWCAP bits in the future.
Cc: Paul Burton <paulburton@kernel.org>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Huacai Chen <chenhc@lemote.com>
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-30 00:32:42 -07:00
|
|
|
|
|
|
|
|
have_cpucfg_now:
|
|
|
|
|
/* We have usable CPUCFG now, emulated or not.
|
|
|
|
|
* Announce CPUCFG availability to userspace via hwcap.
|
|
|
|
|
*/
|
|
|
|
|
elf_hwcap |= HWCAP_LOONGSON_CPUCFG;
|
MIPS: emulate CPUCFG instruction on older Loongson64 cores
CPUCFG is the instruction for querying processor characteristics on
newer Loongson processors, much like CPUID of x86. Since the instruction
is supposedly designed to provide a unified way to do feature detection
(without having to, for example, parse /proc/cpuinfo which is too
heavyweight), it is important to provide compatibility for older cores
without native support. Fortunately, most of the fields can be
synthesized without changes to semantics. Performance is not really big
a concern, because feature detection logic is not expected to be
invoked very often in typical userland applications.
The instruction can't be emulated on LOONGSON_2EF cores, according to
FlyGoat's experiments. Because the LWC2 opcode is assigned to other
valid instructions on 2E and 2F, no RI exception is raised for us to
intercept. So compatibility is only extended back furthest to
Loongson-3A1000. Loongson-2K is covered too, as it is basically a remix
of various blocks from the 3A/3B models from a kernel perspective.
This is lightly based on Loongson's work on their Linux 3.10 fork, for
being the authority on the right feature flags to fill in, where things
aren't otherwise discoverable.
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-23 06:37:01 -07:00
|
|
|
}
|