2024-02-05 08:58:02 -07:00
|
|
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
|
|
%YAML 1.2
|
|
|
|
---
|
|
|
|
$id: http://devicetree.org/schemas/pci/qcom,pcie-sc7280.yaml#
|
|
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
|
|
|
|
title: Qualcomm SC7280 PCI Express Root Complex
|
|
|
|
|
|
|
|
maintainers:
|
|
|
|
- Bjorn Andersson <andersson@kernel.org>
|
|
|
|
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
|
|
|
|
|
|
|
description:
|
|
|
|
Qualcomm SC7280 SoC PCIe root complex controller is based on the Synopsys
|
|
|
|
DesignWare PCIe IP.
|
|
|
|
|
|
|
|
properties:
|
|
|
|
compatible:
|
|
|
|
const: qcom,pcie-sc7280
|
|
|
|
|
|
|
|
reg:
|
|
|
|
minItems: 5
|
|
|
|
maxItems: 6
|
|
|
|
|
|
|
|
reg-names:
|
|
|
|
minItems: 5
|
|
|
|
items:
|
|
|
|
- const: parf # Qualcomm specific registers
|
|
|
|
- const: dbi # DesignWare PCIe registers
|
|
|
|
- const: elbi # External local bus interface registers
|
|
|
|
- const: atu # ATU address space
|
|
|
|
- const: config # PCIe configuration space
|
|
|
|
- const: mhi # MHI registers
|
|
|
|
|
|
|
|
clocks:
|
|
|
|
minItems: 13
|
|
|
|
maxItems: 13
|
|
|
|
|
|
|
|
clock-names:
|
|
|
|
items:
|
|
|
|
- const: pipe # PIPE clock
|
|
|
|
- const: pipe_mux # PIPE MUX
|
|
|
|
- const: phy_pipe # PIPE output clock
|
|
|
|
- const: ref # REFERENCE clock
|
|
|
|
- const: aux # Auxiliary clock
|
|
|
|
- const: cfg # Configuration clock
|
|
|
|
- const: bus_master # Master AXI clock
|
|
|
|
- const: bus_slave # Slave AXI clock
|
|
|
|
- const: slave_q2a # Slave Q2A clock
|
|
|
|
- const: tbu # PCIe TBU clock
|
|
|
|
- const: ddrss_sf_tbu # PCIe SF TBU clock
|
|
|
|
- const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock
|
|
|
|
- const: aggre1 # Aggre NoC PCIe1 AXI clock
|
|
|
|
|
|
|
|
interrupts:
|
2024-07-22 02:18:50 -07:00
|
|
|
minItems: 8
|
|
|
|
maxItems: 8
|
2024-02-05 08:58:02 -07:00
|
|
|
|
|
|
|
interrupt-names:
|
|
|
|
items:
|
2024-07-22 02:18:50 -07:00
|
|
|
- const: msi0
|
|
|
|
- const: msi1
|
|
|
|
- const: msi2
|
|
|
|
- const: msi3
|
|
|
|
- const: msi4
|
|
|
|
- const: msi5
|
|
|
|
- const: msi6
|
|
|
|
- const: msi7
|
2024-02-05 08:58:02 -07:00
|
|
|
|
|
|
|
resets:
|
|
|
|
maxItems: 1
|
|
|
|
|
|
|
|
reset-names:
|
|
|
|
items:
|
|
|
|
- const: pci
|
|
|
|
|
|
|
|
allOf:
|
|
|
|
- $ref: qcom,pcie-common.yaml#
|
|
|
|
|
|
|
|
unevaluatedProperties: false
|
|
|
|
|
|
|
|
examples:
|
|
|
|
- |
|
|
|
|
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
|
|
|
|
#include <dt-bindings/clock/qcom,rpmh.h>
|
|
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
|
|
|
|
|
|
soc {
|
|
|
|
#address-cells = <2>;
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
|
|
|
pcie@1c08000 {
|
|
|
|
compatible = "qcom,pcie-sc7280";
|
|
|
|
reg = <0 0x01c08000 0 0x3000>,
|
|
|
|
<0 0x40000000 0 0xf1d>,
|
|
|
|
<0 0x40000f20 0 0xa8>,
|
|
|
|
<0 0x40001000 0 0x1000>,
|
|
|
|
<0 0x40100000 0 0x100000>;
|
|
|
|
reg-names = "parf", "dbi", "elbi", "atu", "config";
|
|
|
|
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
|
|
|
|
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
|
|
|
|
|
|
|
|
bus-range = <0x00 0xff>;
|
|
|
|
device_type = "pci";
|
|
|
|
linux,pci-domain = <1>;
|
|
|
|
num-lanes = <2>;
|
|
|
|
|
|
|
|
#address-cells = <3>;
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
|
|
|
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
|
|
|
|
assigned-clock-rates = <19200000>;
|
|
|
|
|
|
|
|
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
|
|
|
|
<&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
|
|
|
|
<&pcie1_phy>,
|
|
|
|
<&rpmhcc RPMH_CXO_CLK>,
|
|
|
|
<&gcc GCC_PCIE_1_AUX_CLK>,
|
|
|
|
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
|
|
|
|
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
|
|
|
|
<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
|
|
|
|
<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
|
|
|
|
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
|
|
|
|
<&gcc GCC_DDRSS_PCIE_SF_CLK>,
|
|
|
|
<&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>,
|
|
|
|
<&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
|
|
|
|
|
|
|
|
clock-names = "pipe",
|
|
|
|
"pipe_mux",
|
|
|
|
"phy_pipe",
|
|
|
|
"ref",
|
|
|
|
"aux",
|
|
|
|
"cfg",
|
|
|
|
"bus_master",
|
|
|
|
"bus_slave",
|
|
|
|
"slave_q2a",
|
|
|
|
"tbu",
|
|
|
|
"ddrss_sf_tbu",
|
|
|
|
"aggre0",
|
|
|
|
"aggre1";
|
|
|
|
|
|
|
|
dma-coherent;
|
|
|
|
|
2024-07-22 02:18:50 -07:00
|
|
|
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
interrupt-names = "msi0", "msi1", "msi2", "msi3",
|
|
|
|
"msi4", "msi5", "msi6", "msi7";
|
2024-02-05 08:58:02 -07:00
|
|
|
#interrupt-cells = <1>;
|
|
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
|
|
interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
|
|
|
iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
|
|
|
|
<0x100 &apps_smmu 0x1c81 0x1>;
|
|
|
|
|
|
|
|
phys = <&pcie1_phy>;
|
|
|
|
phy-names = "pciephy";
|
|
|
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <&pcie1_clkreq_n>;
|
|
|
|
|
|
|
|
power-domains = <&gcc GCC_PCIE_1_GDSC>;
|
|
|
|
|
|
|
|
resets = <&gcc GCC_PCIE_1_BCR>;
|
|
|
|
reset-names = "pci";
|
|
|
|
|
|
|
|
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
|
|
|
|
vddpe-3v3-supply = <&pp3300_ssd>;
|
|
|
|
};
|
|
|
|
};
|