54 lines
1.2 KiB
YAML
54 lines
1.2 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/sophgo,sg2042-pll.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Sophgo SG2042 PLL Clock Generator
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maintainers:
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- Chen Wang <unicorn_wang@outlook.com>
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properties:
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compatible:
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const: sophgo,sg2042-pll
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz)
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- description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz)
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- description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz)
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clock-names:
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items:
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- const: cgi_main
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- const: cgi_dpll0
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- const: cgi_dpll1
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'#clock-cells':
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const: 1
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description:
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See <dt-bindings/clock/sophgo,sg2042-pll.h> for valid indices.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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clock-controller@10000000 {
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compatible = "sophgo,sg2042-pll";
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reg = <0x10000000 0x10000>;
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clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>;
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clock-names = "cgi_main", "cgi_dpll0", "cgi_dpll1";
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#clock-cells = <1>;
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};
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