83 lines
2.3 KiB
YAML
83 lines
2.3 KiB
YAML
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||
|
|
%YAML 1.2
|
||
|
|
---
|
||
|
|
$id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml#
|
||
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||
|
|
|
||
|
|
title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks
|
||
|
|
|
||
|
|
maintainers:
|
||
|
|
- Geert Uytterhoeven <geert+renesas@glider.be>
|
||
|
|
|
||
|
|
description:
|
||
|
|
The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are
|
||
|
|
organized in groups of up to 32 gates.
|
||
|
|
|
||
|
|
This device tree binding describes a single 32 gate clocks group per node.
|
||
|
|
Clocks are referenced by user nodes by the Module Stop (MSTP) node phandle
|
||
|
|
and the clock index in the group, from 0 to 31.
|
||
|
|
|
||
|
|
properties:
|
||
|
|
compatible:
|
||
|
|
items:
|
||
|
|
- enum:
|
||
|
|
- renesas,r7s72100-mstp-clocks # RZ/A1
|
||
|
|
- renesas,r8a73a4-mstp-clocks # R-Mobile APE6
|
||
|
|
- renesas,r8a7740-mstp-clocks # R-Mobile A1
|
||
|
|
- renesas,r8a7778-mstp-clocks # R-Car M1
|
||
|
|
- renesas,r8a7779-mstp-clocks # R-Car H1
|
||
|
|
- renesas,sh73a0-mstp-clocks # SH-Mobile AG5
|
||
|
|
- const: renesas,cpg-mstp-clocks
|
||
|
|
|
||
|
|
reg:
|
||
|
|
minItems: 1
|
||
|
|
items:
|
||
|
|
- description: Module Stop Control Register (MSTPCR)
|
||
|
|
- description: Module Stop Status Register (MSTPSR)
|
||
|
|
|
||
|
|
clocks:
|
||
|
|
minItems: 1
|
||
|
|
maxItems: 32
|
||
|
|
|
||
|
|
'#clock-cells':
|
||
|
|
const: 1
|
||
|
|
|
||
|
|
clock-indices:
|
||
|
|
minItems: 1
|
||
|
|
maxItems: 32
|
||
|
|
|
||
|
|
clock-output-names:
|
||
|
|
minItems: 1
|
||
|
|
maxItems: 32
|
||
|
|
|
||
|
|
required:
|
||
|
|
- compatible
|
||
|
|
- reg
|
||
|
|
- clocks
|
||
|
|
- '#clock-cells'
|
||
|
|
- clock-indices
|
||
|
|
- clock-output-names
|
||
|
|
|
||
|
|
additionalProperties: false
|
||
|
|
|
||
|
|
examples:
|
||
|
|
- |
|
||
|
|
#include <dt-bindings/clock/r8a73a4-clock.h>
|
||
|
|
mstp2_clks: mstp2_clks@e6150138 {
|
||
|
|
compatible = "renesas,r8a73a4-mstp-clocks",
|
||
|
|
"renesas,cpg-mstp-clocks";
|
||
|
|
reg = <0xe6150138 4>, <0xe6150040 4>;
|
||
|
|
clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
|
||
|
|
<&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
clock-indices = <
|
||
|
|
R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1
|
||
|
|
R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1
|
||
|
|
R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3
|
||
|
|
R8A73A4_CLK_DMAC
|
||
|
|
>;
|
||
|
|
clock-output-names =
|
||
|
|
"scifa0", "scifa1", "scifb0", "scifb1", "scifb2", "scifb3",
|
||
|
|
"dmac";
|
||
|
|
};
|