46 lines
952 B
YAML
46 lines
952 B
YAML
|
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||
|
|
%YAML 1.2
|
||
|
|
---
|
||
|
|
$id: http://devicetree.org/schemas/clock/mediatek,mt7622-ssusbsys.yaml#
|
||
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||
|
|
|
||
|
|
title: MediaTek SSUSBSYS clock and reset controller
|
||
|
|
|
||
|
|
description:
|
||
|
|
The MediaTek SSUSBSYS controller provides various clocks to the system.
|
||
|
|
|
||
|
|
maintainers:
|
||
|
|
- Matthias Brugger <matthias.bgg@gmail.com>
|
||
|
|
|
||
|
|
properties:
|
||
|
|
compatible:
|
||
|
|
enum:
|
||
|
|
- mediatek,mt7622-ssusbsys
|
||
|
|
- mediatek,mt7629-ssusbsys
|
||
|
|
|
||
|
|
reg:
|
||
|
|
maxItems: 1
|
||
|
|
|
||
|
|
"#clock-cells":
|
||
|
|
const: 1
|
||
|
|
description: The available clocks are defined in dt-bindings/clock/mt*-clk.h
|
||
|
|
|
||
|
|
"#reset-cells":
|
||
|
|
const: 1
|
||
|
|
|
||
|
|
required:
|
||
|
|
- reg
|
||
|
|
- "#clock-cells"
|
||
|
|
- "#reset-cells"
|
||
|
|
|
||
|
|
additionalProperties: false
|
||
|
|
|
||
|
|
examples:
|
||
|
|
- |
|
||
|
|
clock-controller@1a000000 {
|
||
|
|
compatible = "mediatek,mt7622-ssusbsys";
|
||
|
|
reg = <0x1a000000 0x1000>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
#reset-cells = <1>;
|
||
|
|
};
|