2020-11-23 19:38:14 -07:00
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.. _elf_hwcaps_index:
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2019-06-12 10:52:38 -07:00
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================
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2017-10-11 06:01:03 -07:00
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ARM64 ELF hwcaps
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================
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This document describes the usage and semantics of the arm64 ELF hwcaps.
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1. Introduction
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---------------
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Some hardware or software features are only available on some CPU
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implementations, and/or with certain kernel configurations, but have no
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architected discovery mechanism available to userspace code at EL0. The
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kernel exposes the presence of these features to userspace through a set
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2023-01-26 23:39:32 -07:00
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of flags called hwcaps, exposed in the auxiliary vector.
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2017-10-11 06:01:03 -07:00
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2019-04-09 02:52:40 -07:00
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Userspace software can test for features by acquiring the AT_HWCAP or
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AT_HWCAP2 entry of the auxiliary vector, and testing whether the relevant
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2019-06-12 10:52:38 -07:00
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flags are set, e.g.::
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2019-06-12 10:52:38 -07:00
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bool floating_point_is_present(void)
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{
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unsigned long hwcaps = getauxval(AT_HWCAP);
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if (hwcaps & HWCAP_FP)
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return true;
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2017-10-11 06:01:03 -07:00
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2019-06-12 10:52:38 -07:00
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return false;
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}
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2017-10-11 06:01:03 -07:00
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Where software relies on a feature described by a hwcap, it should check
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the relevant hwcap flag to verify that the feature is present before
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attempting to make use of the feature.
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Features cannot be probed reliably through other means. When a feature
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is not available, attempting to use it may result in unpredictable
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behaviour, and is not guaranteed to result in any reliable indication
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that the feature is unavailable, such as a SIGILL.
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2. Interpretation of hwcaps
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---------------------------
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The majority of hwcaps are intended to indicate the presence of features
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which are described by architected ID registers inaccessible to
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userspace code at EL0. These hwcaps are defined in terms of ID register
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fields, and should be interpreted with reference to the definition of
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these fields in the ARM Architecture Reference Manual (ARM ARM).
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2019-06-12 10:52:38 -07:00
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Such hwcaps are described below in the form::
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Functionality implied by idreg.field == val.
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Such hwcaps indicate the availability of functionality that the ARM ARM
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defines as being present when idreg.field has value val, but do not
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indicate that idreg.field is precisely equal to val, nor do they
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indicate the absence of functionality implied by other values of
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idreg.field.
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Other hwcaps may indicate the presence of features which cannot be
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described by ID registers alone. These may be described without
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reference to ID registers, and may refer to other documentation.
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3. The hwcaps exposed in AT_HWCAP
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---------------------------------
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HWCAP_FP
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Functionality implied by ID_AA64PFR0_EL1.FP == 0b0000.
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HWCAP_ASIMD
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Functionality implied by ID_AA64PFR0_EL1.AdvSIMD == 0b0000.
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HWCAP_EVTSTRM
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The generic timer is configured to generate events at a frequency of
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2021-05-05 06:28:45 -07:00
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approximately 10KHz.
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HWCAP_AES
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Functionality implied by ID_AA64ISAR0_EL1.AES == 0b0001.
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HWCAP_PMULL
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2018-10-01 07:24:47 -07:00
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Functionality implied by ID_AA64ISAR0_EL1.AES == 0b0010.
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HWCAP_SHA1
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Functionality implied by ID_AA64ISAR0_EL1.SHA1 == 0b0001.
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HWCAP_SHA2
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Functionality implied by ID_AA64ISAR0_EL1.SHA2 == 0b0001.
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HWCAP_CRC32
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Functionality implied by ID_AA64ISAR0_EL1.CRC32 == 0b0001.
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HWCAP_ATOMICS
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Functionality implied by ID_AA64ISAR0_EL1.Atomic == 0b0010.
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HWCAP_FPHP
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Functionality implied by ID_AA64PFR0_EL1.FP == 0b0001.
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HWCAP_ASIMDHP
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Functionality implied by ID_AA64PFR0_EL1.AdvSIMD == 0b0001.
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HWCAP_CPUID
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EL0 access to certain ID registers is available, to the extent
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described by Documentation/arch/arm64/cpu-feature-registers.rst.
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These ID registers may imply the availability of features.
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HWCAP_ASIMDRDM
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Functionality implied by ID_AA64ISAR0_EL1.RDM == 0b0001.
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HWCAP_JSCVT
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Functionality implied by ID_AA64ISAR1_EL1.JSCVT == 0b0001.
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HWCAP_FCMA
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Functionality implied by ID_AA64ISAR1_EL1.FCMA == 0b0001.
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HWCAP_LRCPC
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Functionality implied by ID_AA64ISAR1_EL1.LRCPC == 0b0001.
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HWCAP_DCPOP
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Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0001.
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HWCAP_SHA3
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Functionality implied by ID_AA64ISAR0_EL1.SHA3 == 0b0001.
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HWCAP_SM3
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Functionality implied by ID_AA64ISAR0_EL1.SM3 == 0b0001.
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HWCAP_SM4
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Functionality implied by ID_AA64ISAR0_EL1.SM4 == 0b0001.
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HWCAP_ASIMDDP
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Functionality implied by ID_AA64ISAR0_EL1.DP == 0b0001.
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HWCAP_SHA512
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Functionality implied by ID_AA64ISAR0_EL1.SHA2 == 0b0010.
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HWCAP_SVE
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Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001.
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2017-12-13 03:13:56 -07:00
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HWCAP_ASIMDFHM
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Functionality implied by ID_AA64ISAR0_EL1.FHM == 0b0001.
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2018-03-12 03:04:14 -07:00
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HWCAP_DIT
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Functionality implied by ID_AA64PFR0_EL1.DIT == 0b0001.
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HWCAP_USCAT
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Functionality implied by ID_AA64MMFR2_EL1.AT == 0b0001.
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HWCAP_ILRCPC
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Functionality implied by ID_AA64ISAR1_EL1.LRCPC == 0b0010.
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2018-03-12 03:04:14 -07:00
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HWCAP_FLAGM
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Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0001.
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2018-10-01 07:24:48 -07:00
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HWCAP_SSBS
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Functionality implied by ID_AA64PFR1_EL1.SSBS == 0b0010.
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2018-12-07 11:39:31 -07:00
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2019-10-03 04:12:10 -07:00
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HWCAP_SB
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Functionality implied by ID_AA64ISAR1_EL1.SB == 0b0001.
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2018-12-07 11:39:31 -07:00
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HWCAP_PACA
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Functionality implied by ID_AA64ISAR1_EL1.APA == 0b0001 or
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ID_AA64ISAR1_EL1.API == 0b0001, as described by
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Documentation/arch/arm64/pointer-authentication.rst.
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2018-12-07 11:39:31 -07:00
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HWCAP_PACG
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Functionality implied by ID_AA64ISAR1_EL1.GPA == 0b0001 or
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ID_AA64ISAR1_EL1.GPI == 0b0001, as described by
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Documentation/arch/arm64/pointer-authentication.rst.
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2019-10-03 04:12:09 -07:00
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HWCAP2_DCPODP
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Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0010.
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HWCAP2_SVE2
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Functionality implied by ID_AA64ZFR0_EL1.SVEver == 0b0001.
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HWCAP2_SVEAES
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Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0001.
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HWCAP2_SVEPMULL
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Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0010.
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HWCAP2_SVEBITPERM
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Functionality implied by ID_AA64ZFR0_EL1.BitPerm == 0b0001.
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HWCAP2_SVESHA3
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Functionality implied by ID_AA64ZFR0_EL1.SHA3 == 0b0001.
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HWCAP2_SVESM4
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Functionality implied by ID_AA64ZFR0_EL1.SM4 == 0b0001.
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HWCAP2_FLAGM2
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Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0010.
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2019-06-18 11:10:55 -07:00
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HWCAP2_FRINT
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Functionality implied by ID_AA64ISAR1_EL1.FRINTTS == 0b0001.
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2019-12-16 04:33:37 -07:00
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HWCAP2_SVEI8MM
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Functionality implied by ID_AA64ZFR0_EL1.I8MM == 0b0001.
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HWCAP2_SVEF32MM
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Functionality implied by ID_AA64ZFR0_EL1.F32MM == 0b0001.
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HWCAP2_SVEF64MM
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Functionality implied by ID_AA64ZFR0_EL1.F64MM == 0b0001.
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HWCAP2_SVEBF16
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Functionality implied by ID_AA64ZFR0_EL1.BF16 == 0b0001.
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HWCAP2_I8MM
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Functionality implied by ID_AA64ISAR1_EL1.I8MM == 0b0001.
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HWCAP2_BF16
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Functionality implied by ID_AA64ISAR1_EL1.BF16 == 0b0001.
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HWCAP2_DGH
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Functionality implied by ID_AA64ISAR1_EL1.DGH == 0b0001.
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2020-01-21 05:58:52 -07:00
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HWCAP2_RNG
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Functionality implied by ID_AA64ISAR0_EL1.RNDR == 0b0001.
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2020-03-16 09:50:45 -07:00
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HWCAP2_BTI
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Functionality implied by ID_AA64PFR1_EL1.BT == 0b0001.
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2020-03-16 09:50:45 -07:00
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2019-09-06 02:52:39 -07:00
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HWCAP2_MTE
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Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0010, as described
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by Documentation/arch/arm64/memory-tagging-extension.rst.
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2020-03-16 09:50:45 -07:00
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2021-10-17 05:42:25 -07:00
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HWCAP2_ECV
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Functionality implied by ID_AA64MMFR0_EL1.ECV == 0b0001.
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2021-12-10 09:54:30 -07:00
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HWCAP2_AFP
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2023-10-31 13:08:38 -07:00
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Functionality implied by ID_AA64MMFR1_EL1.AFP == 0b0001.
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2021-12-10 09:54:30 -07:00
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2021-12-10 09:54:32 -07:00
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HWCAP2_RPRES
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Functionality implied by ID_AA64ISAR2_EL1.RPRES == 0b0001.
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2022-02-16 10:32:23 -07:00
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HWCAP2_MTE3
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Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0011, as described
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by Documentation/arch/arm64/memory-tagging-extension.rst.
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2022-04-19 04:22:16 -07:00
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HWCAP2_SME
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Functionality implied by ID_AA64PFR1_EL1.SME == 0b0001, as described
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by Documentation/arch/arm64/sme.rst.
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HWCAP2_SME_I16I64
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Functionality implied by ID_AA64SMFR0_EL1.I16I64 == 0b1111.
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HWCAP2_SME_F64F64
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Functionality implied by ID_AA64SMFR0_EL1.F64F64 == 0b1.
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HWCAP2_SME_I8I32
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Functionality implied by ID_AA64SMFR0_EL1.I8I32 == 0b1111.
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HWCAP2_SME_F16F32
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Functionality implied by ID_AA64SMFR0_EL1.F16F32 == 0b1.
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HWCAP2_SME_B16F32
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Functionality implied by ID_AA64SMFR0_EL1.B16F32 == 0b1.
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HWCAP2_SME_F32F32
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Functionality implied by ID_AA64SMFR0_EL1.F32F32 == 0b1.
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HWCAP2_SME_FA64
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Functionality implied by ID_AA64SMFR0_EL1.FA64 == 0b1.
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2022-04-20 05:21:12 -07:00
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HWCAP2_WFXT
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Functionality implied by ID_AA64ISAR2_EL1.WFXT == 0b0010.
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2022-07-07 03:36:32 -07:00
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HWCAP2_EBF16
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Functionality implied by ID_AA64ISAR1_EL1.BF16 == 0b0010.
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2022-08-29 08:48:15 -07:00
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HWCAP2_SVE_EBF16
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Functionality implied by ID_AA64ZFR0_EL1.BF16 == 0b0010.
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2022-10-17 08:25:15 -07:00
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HWCAP2_CSSC
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Functionality implied by ID_AA64ISAR2_EL1.CSSC == 0b0001.
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2022-10-17 08:25:17 -07:00
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HWCAP2_RPRFM
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Functionality implied by ID_AA64ISAR2_EL1.RPRFM == 0b0001.
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2022-10-17 08:25:19 -07:00
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HWCAP2_SVE2P1
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Functionality implied by ID_AA64ZFR0_EL1.SVEver == 0b0010.
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2023-01-16 09:04:48 -07:00
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HWCAP2_SME2
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Functionality implied by ID_AA64SMFR0_EL1.SMEver == 0b0001.
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HWCAP2_SME2P1
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Functionality implied by ID_AA64SMFR0_EL1.SMEver == 0b0010.
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HWCAP2_SMEI16I32
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Functionality implied by ID_AA64SMFR0_EL1.I16I32 == 0b0101
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HWCAP2_SMEBI32I32
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Functionality implied by ID_AA64SMFR0_EL1.BI32I32 == 0b1
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HWCAP2_SMEB16B16
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Functionality implied by ID_AA64SMFR0_EL1.B16B16 == 0b1
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HWCAP2_SMEF16F16
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Functionality implied by ID_AA64SMFR0_EL1.F16F16 == 0b1
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2023-05-09 07:22:33 -07:00
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HWCAP2_MOPS
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Functionality implied by ID_AA64ISAR2_EL1.MOPS == 0b0001.
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2023-09-14 03:09:29 -07:00
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HWCAP2_HBC
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Functionality implied by ID_AA64ISAR2_EL1.BC == 0b0001.
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2023-09-15 05:18:06 -07:00
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HWCAP2_SVE_B16B16
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Functionality implied by ID_AA64ZFR0_EL1.B16B16 == 0b0001.
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2023-09-19 09:27:56 -07:00
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HWCAP2_LRCPC3
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Functionality implied by ID_AA64ISAR1_EL1.LRCPC == 0b0011.
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2023-10-03 05:45:43 -07:00
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HWCAP2_LSE128
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Functionality implied by ID_AA64ISAR0_EL1.Atomic == 0b0011.
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2024-03-06 16:14:51 -07:00
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HWCAP2_FPMR
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Functionality implied by ID_AA64PFR2_EL1.FMR == 0b0001.
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HWCAP2_LUT
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Functionality implied by ID_AA64ISAR2_EL1.LUT == 0b0001.
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HWCAP2_FAMINMAX
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Functionality implied by ID_AA64ISAR3_EL1.FAMINMAX == 0b0001.
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HWCAP2_F8CVT
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Functionality implied by ID_AA64FPFR0_EL1.F8CVT == 0b1.
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HWCAP2_F8FMA
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Functionality implied by ID_AA64FPFR0_EL1.F8FMA == 0b1.
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HWCAP2_F8DP4
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Functionality implied by ID_AA64FPFR0_EL1.F8DP4 == 0b1.
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HWCAP2_F8DP2
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Functionality implied by ID_AA64FPFR0_EL1.F8DP2 == 0b1.
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HWCAP2_F8E4M3
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Functionality implied by ID_AA64FPFR0_EL1.F8E4M3 == 0b1.
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HWCAP2_F8E5M2
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Functionality implied by ID_AA64FPFR0_EL1.F8E5M2 == 0b1.
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HWCAP2_SME_LUTV2
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Functionality implied by ID_AA64SMFR0_EL1.LUTv2 == 0b1.
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HWCAP2_SME_F8F16
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Functionality implied by ID_AA64SMFR0_EL1.F8F16 == 0b1.
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HWCAP2_SME_F8F32
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Functionality implied by ID_AA64SMFR0_EL1.F8F32 == 0b1.
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HWCAP2_SME_SF8FMA
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Functionality implied by ID_AA64SMFR0_EL1.SF8FMA == 0b1.
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HWCAP2_SME_SF8DP4
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Functionality implied by ID_AA64SMFR0_EL1.SF8DP4 == 0b1.
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HWCAP2_SME_SF8DP2
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Functionality implied by ID_AA64SMFR0_EL1.SF8DP2 == 0b1.
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HWCAP2_SME_SF8DP4
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Functionality implied by ID_AA64SMFR0_EL1.SF8DP4 == 0b1.
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|
2024-08-22 08:10:54 -07:00
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HWCAP2_POE
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Functionality implied by ID_AA64MMFR3_EL1.S1POE == 0b0001.
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2024-03-06 16:14:51 -07:00
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|
2019-04-09 02:52:40 -07:00
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4. Unused AT_HWCAP bits
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|
-----------------------
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For interoperation with userspace, the kernel guarantees that bits 62
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and 63 of AT_HWCAP will always be returned as 0.
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