2011-07-05 10:48:26 -07:00
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/*
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* Broadcom specific AMBA
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* PCI Core in hostmode
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*
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2012-01-30 16:03:35 -07:00
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* Copyright 2005 - 2011, Broadcom Corporation
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* Copyright 2006, 2007, Michael Buesch <m@bues.ch>
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* Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
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*
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2011-07-05 10:48:26 -07:00
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include "bcma_private.h"
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2012-03-25 17:02:55 -07:00
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#include <linux/pci.h>
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2012-01-30 16:03:35 -07:00
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#include <linux/export.h>
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2011-07-05 10:48:26 -07:00
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#include <linux/bcma/bcma.h>
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2012-01-30 16:03:35 -07:00
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#include <asm/paccess.h>
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/* Probe a 32bit value on the bus and catch bus exceptions.
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* Returns nonzero on a bus exception.
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* This is MIPS specific */
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#define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr)))
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/* Assume one-hot slot wiring */
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#define BCMA_PCI_SLOT_MAX 16
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#define PCI_CONFIG_SPACE_SIZE 256
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2012-12-21 16:12:59 -07:00
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bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
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2012-01-30 16:03:35 -07:00
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{
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struct bcma_bus *bus = pc->core->bus;
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u16 chipid_top;
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u32 tmp;
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chipid_top = (bus->chipinfo.id & 0xFF00);
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if (chipid_top != 0x4700 &&
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chipid_top != 0x5300)
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return false;
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bcma_core_enable(pc->core, 0);
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return !mips_busprobe32(tmp, pc->core->io_addr);
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}
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static u32 bcma_pcie_read_config(struct bcma_drv_pci *pc, u32 address)
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{
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pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
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pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
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return pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_DATA);
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}
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static void bcma_pcie_write_config(struct bcma_drv_pci *pc, u32 address,
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u32 data)
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{
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pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
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pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
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pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_DATA, data);
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}
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static u32 bcma_get_cfgspace_addr(struct bcma_drv_pci *pc, unsigned int dev,
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unsigned int func, unsigned int off)
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{
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u32 addr = 0;
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/* Issue config commands only when the data link is up (atleast
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* one external pcie device is present).
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*/
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if (dev >= 2 || !(bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_LSREG)
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& BCMA_CORE_PCI_DLLP_LSREG_LINKUP))
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goto out;
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/* Type 0 transaction */
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/* Slide the PCI window to the appropriate slot */
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pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
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/* Calculate the address */
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addr = pc->host_controller->host_cfg_addr;
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addr |= (dev << BCMA_CORE_PCI_CFG_SLOT_SHIFT);
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addr |= (func << BCMA_CORE_PCI_CFG_FUN_SHIFT);
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addr |= (off & ~3);
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out:
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return addr;
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}
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static int bcma_extpci_read_config(struct bcma_drv_pci *pc, unsigned int dev,
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unsigned int func, unsigned int off,
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void *buf, int len)
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{
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int err = -EINVAL;
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u32 addr, val;
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void __iomem *mmio = 0;
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WARN_ON(!pc->hostmode);
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if (unlikely(len != 1 && len != 2 && len != 4))
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goto out;
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if (dev == 0) {
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/* we support only two functions on device 0 */
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if (func > 1)
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2013-01-12 03:46:14 -07:00
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goto out;
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2012-01-30 16:03:35 -07:00
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/* accesses to config registers with offsets >= 256
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* requires indirect access.
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*/
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if (off >= PCI_CONFIG_SPACE_SIZE) {
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addr = (func << 12);
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2013-01-12 03:46:16 -07:00
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addr |= (off & 0x0FFC);
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2012-01-30 16:03:35 -07:00
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val = bcma_pcie_read_config(pc, addr);
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} else {
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addr = BCMA_CORE_PCI_PCICFG0;
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addr |= (func << 8);
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2013-01-12 03:46:17 -07:00
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addr |= (off & 0xFC);
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2012-01-30 16:03:35 -07:00
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val = pcicore_read32(pc, addr);
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}
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} else {
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addr = bcma_get_cfgspace_addr(pc, dev, func, off);
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if (unlikely(!addr))
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goto out;
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err = -ENOMEM;
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2012-05-04 21:56:34 -07:00
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mmio = ioremap_nocache(addr, sizeof(val));
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2012-01-30 16:03:35 -07:00
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if (!mmio)
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goto out;
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if (mips_busprobe32(val, mmio)) {
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2013-01-12 03:46:17 -07:00
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val = 0xFFFFFFFF;
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2012-01-30 16:03:35 -07:00
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goto unmap;
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}
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}
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val >>= (8 * (off & 3));
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switch (len) {
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case 1:
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*((u8 *)buf) = (u8)val;
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break;
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case 2:
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*((u16 *)buf) = (u16)val;
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break;
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case 4:
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*((u32 *)buf) = (u32)val;
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break;
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}
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err = 0;
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unmap:
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if (mmio)
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iounmap(mmio);
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out:
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return err;
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}
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static int bcma_extpci_write_config(struct bcma_drv_pci *pc, unsigned int dev,
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unsigned int func, unsigned int off,
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const void *buf, int len)
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{
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int err = -EINVAL;
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2013-01-12 03:46:15 -07:00
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u32 addr, val;
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2012-01-30 16:03:35 -07:00
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void __iomem *mmio = 0;
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u16 chipid = pc->core->bus->chipinfo.id;
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WARN_ON(!pc->hostmode);
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if (unlikely(len != 1 && len != 2 && len != 4))
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goto out;
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if (dev == 0) {
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2013-01-12 03:46:14 -07:00
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/* we support only two functions on device 0 */
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if (func > 1)
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goto out;
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2012-01-30 16:03:35 -07:00
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/* accesses to config registers with offsets >= 256
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* requires indirect access.
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*/
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2013-01-12 03:46:16 -07:00
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if (off >= PCI_CONFIG_SPACE_SIZE) {
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addr = (func << 12);
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addr |= (off & 0x0FFC);
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val = bcma_pcie_read_config(pc, addr);
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} else {
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2013-01-12 03:46:15 -07:00
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addr = BCMA_CORE_PCI_PCICFG0;
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2012-01-30 16:03:35 -07:00
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addr |= (func << 8);
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2013-01-12 03:46:17 -07:00
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addr |= (off & 0xFC);
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2013-01-12 03:46:15 -07:00
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val = pcicore_read32(pc, addr);
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2012-01-30 16:03:35 -07:00
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}
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} else {
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addr = bcma_get_cfgspace_addr(pc, dev, func, off);
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if (unlikely(!addr))
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goto out;
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err = -ENOMEM;
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2012-05-04 21:56:34 -07:00
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mmio = ioremap_nocache(addr, sizeof(val));
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2012-01-30 16:03:35 -07:00
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if (!mmio)
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goto out;
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if (mips_busprobe32(val, mmio)) {
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2013-01-12 03:46:17 -07:00
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val = 0xFFFFFFFF;
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2012-01-30 16:03:35 -07:00
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goto unmap;
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}
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}
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switch (len) {
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case 1:
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val &= ~(0xFF << (8 * (off & 3)));
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val |= *((const u8 *)buf) << (8 * (off & 3));
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break;
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case 2:
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val &= ~(0xFFFF << (8 * (off & 3)));
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val |= *((const u16 *)buf) << (8 * (off & 3));
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break;
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case 4:
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val = *((const u32 *)buf);
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break;
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}
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2013-01-12 03:46:15 -07:00
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if (dev == 0) {
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2012-01-30 16:03:35 -07:00
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/* accesses to config registers with offsets >= 256
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* requires indirect access.
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*/
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2013-01-12 03:46:16 -07:00
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if (off >= PCI_CONFIG_SPACE_SIZE)
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2013-01-12 03:46:15 -07:00
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bcma_pcie_write_config(pc, addr, val);
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2013-01-12 03:46:16 -07:00
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else
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2013-01-12 03:46:15 -07:00
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pcicore_write32(pc, addr, val);
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2012-01-30 16:03:35 -07:00
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} else {
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writel(val, mmio);
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2012-06-29 16:44:38 -07:00
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if (chipid == BCMA_CHIP_ID_BCM4716 ||
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chipid == BCMA_CHIP_ID_BCM4748)
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2012-01-30 16:03:35 -07:00
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readl(mmio);
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}
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err = 0;
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unmap:
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if (mmio)
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iounmap(mmio);
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out:
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return err;
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}
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static int bcma_core_pci_hostmode_read_config(struct pci_bus *bus,
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unsigned int devfn,
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int reg, int size, u32 *val)
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{
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unsigned long flags;
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int err;
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struct bcma_drv_pci *pc;
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struct bcma_drv_pci_host *pc_host;
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pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
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pc = pc_host->pdev;
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spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
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err = bcma_extpci_read_config(pc, PCI_SLOT(devfn),
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PCI_FUNC(devfn), reg, val, size);
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spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
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return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
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}
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static int bcma_core_pci_hostmode_write_config(struct pci_bus *bus,
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unsigned int devfn,
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int reg, int size, u32 val)
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{
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unsigned long flags;
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int err;
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struct bcma_drv_pci *pc;
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struct bcma_drv_pci_host *pc_host;
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pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
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pc = pc_host->pdev;
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spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
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err = bcma_extpci_write_config(pc, PCI_SLOT(devfn),
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PCI_FUNC(devfn), reg, &val, size);
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spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
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return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
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}
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/* return cap_offset if requested capability exists in the PCI config space */
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2012-12-21 16:12:59 -07:00
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static u8 bcma_find_pci_capability(struct bcma_drv_pci *pc, unsigned int dev,
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unsigned int func, u8 req_cap_id,
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unsigned char *buf, u32 *buflen)
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2012-01-30 16:03:35 -07:00
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{
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u8 cap_id;
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u8 cap_ptr = 0;
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u32 bufsize;
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u8 byte_val;
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/* check for Header type 0 */
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bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val,
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sizeof(u8));
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2013-01-12 03:46:17 -07:00
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if ((byte_val & 0x7F) != PCI_HEADER_TYPE_NORMAL)
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2012-01-30 16:03:35 -07:00
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return cap_ptr;
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/* check if the capability pointer field exists */
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bcma_extpci_read_config(pc, dev, func, PCI_STATUS, &byte_val,
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sizeof(u8));
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if (!(byte_val & PCI_STATUS_CAP_LIST))
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return cap_ptr;
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/* check if the capability pointer is 0x00 */
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bcma_extpci_read_config(pc, dev, func, PCI_CAPABILITY_LIST, &cap_ptr,
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sizeof(u8));
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if (cap_ptr == 0x00)
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return cap_ptr;
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/* loop thr'u the capability list and see if the requested capabilty
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* exists */
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bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id, sizeof(u8));
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while (cap_id != req_cap_id) {
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bcma_extpci_read_config(pc, dev, func, cap_ptr + 1, &cap_ptr,
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sizeof(u8));
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if (cap_ptr == 0x00)
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return cap_ptr;
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bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id,
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sizeof(u8));
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}
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/* found the caller requested capability */
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if ((buf != NULL) && (buflen != NULL)) {
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u8 cap_data;
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bufsize = *buflen;
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if (!bufsize)
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return cap_ptr;
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*buflen = 0;
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/* copy the cpability data excluding cap ID and next ptr */
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cap_data = cap_ptr + 2;
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if ((bufsize + cap_data) > PCI_CONFIG_SPACE_SIZE)
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bufsize = PCI_CONFIG_SPACE_SIZE - cap_data;
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*buflen = bufsize;
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while (bufsize--) {
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bcma_extpci_read_config(pc, dev, func, cap_data, buf,
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sizeof(u8));
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cap_data++;
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buf++;
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}
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}
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return cap_ptr;
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}
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/* If the root port is capable of returning Config Request
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* Retry Status (CRS) Completion Status to software then
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* enable the feature.
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*/
|
2012-12-21 16:12:59 -07:00
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|
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static void bcma_core_pci_enable_crs(struct bcma_drv_pci *pc)
|
2012-01-30 16:03:35 -07:00
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|
|
{
|
2012-07-05 13:07:32 -07:00
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|
|
struct bcma_bus *bus = pc->core->bus;
|
2012-01-30 16:03:35 -07:00
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|
|
u8 cap_ptr, root_ctrl, root_cap, dev;
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|
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u16 val16;
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|
|
int i;
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cap_ptr = bcma_find_pci_capability(pc, 0, 0, PCI_CAP_ID_EXP, NULL,
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|
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NULL);
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root_cap = cap_ptr + PCI_EXP_RTCAP;
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bcma_extpci_read_config(pc, 0, 0, root_cap, &val16, sizeof(u16));
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if (val16 & BCMA_CORE_PCI_RC_CRS_VISIBILITY) {
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/* Enable CRS software visibility */
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root_ctrl = cap_ptr + PCI_EXP_RTCTL;
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val16 = PCI_EXP_RTCTL_CRSSVE;
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bcma_extpci_read_config(pc, 0, 0, root_ctrl, &val16,
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|
|
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sizeof(u16));
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/* Initiate a configuration request to read the vendor id
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* field of the device function's config space header after
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* 100 ms wait time from the end of Reset. If the device is
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* not done with its internal initialization, it must at
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* least return a completion TLP, with a completion status
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* of "Configuration Request Retry Status (CRS)". The root
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* complex must complete the request to the host by returning
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* a read-data value of 0001h for the Vendor ID field and
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* all 1s for any additional bytes included in the request.
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* Poll using the config reads for max wait time of 1 sec or
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* until we receive the successful completion status. Repeat
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* the procedure for all the devices.
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*/
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for (dev = 1; dev < BCMA_PCI_SLOT_MAX; dev++) {
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for (i = 0; i < 100000; i++) {
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bcma_extpci_read_config(pc, dev, 0,
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PCI_VENDOR_ID, &val16,
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|
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sizeof(val16));
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if (val16 != 0x1)
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break;
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udelay(10);
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}
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if (val16 == 0x1)
|
2012-07-05 13:07:32 -07:00
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bcma_err(bus, "PCI: Broken device in slot %d\n",
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dev);
|
2012-01-30 16:03:35 -07:00
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}
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}
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|
|
}
|
2011-07-05 10:48:26 -07:00
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|
|
2012-12-21 16:12:59 -07:00
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|
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void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
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2011-07-05 10:48:26 -07:00
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|
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{
|
2012-01-30 16:03:35 -07:00
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struct bcma_bus *bus = pc->core->bus;
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struct bcma_drv_pci_host *pc_host;
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u32 tmp;
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u32 pci_membase_1G;
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unsigned long io_map_base;
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|
2012-07-05 13:07:32 -07:00
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bcma_info(bus, "PCIEcore in host mode found\n");
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2012-01-30 16:03:35 -07:00
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|
2012-09-30 15:12:54 -07:00
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if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
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bcma_info(bus, "This PCIE core is disabled and not working\n");
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return;
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}
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|
2012-01-30 16:03:35 -07:00
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pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
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if (!pc_host) {
|
2012-07-05 13:07:32 -07:00
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bcma_err(bus, "can not allocate memory");
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2012-01-30 16:03:35 -07:00
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return;
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}
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|
|
2013-02-23 15:30:22 -07:00
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spin_lock_init(&pc_host->cfgspace_lock);
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|
2012-01-30 16:03:35 -07:00
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pc->host_controller = pc_host;
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pc_host->pci_controller.io_resource = &pc_host->io_resource;
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pc_host->pci_controller.mem_resource = &pc_host->mem_resource;
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pc_host->pci_controller.pci_ops = &pc_host->pci_ops;
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pc_host->pdev = pc;
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pci_membase_1G = BCMA_SOC_PCI_DMA;
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pc_host->host_cfg_addr = BCMA_SOC_PCI_CFG;
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pc_host->pci_ops.read = bcma_core_pci_hostmode_read_config;
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pc_host->pci_ops.write = bcma_core_pci_hostmode_write_config;
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pc_host->mem_resource.name = "BCMA PCIcore external memory",
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pc_host->mem_resource.start = BCMA_SOC_PCI_DMA;
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pc_host->mem_resource.end = BCMA_SOC_PCI_DMA + BCMA_SOC_PCI_DMA_SZ - 1;
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pc_host->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
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pc_host->io_resource.name = "BCMA PCIcore external I/O",
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pc_host->io_resource.start = 0x100;
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pc_host->io_resource.end = 0x7FF;
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pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
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/* Reset RC */
|
2012-09-25 01:17:22 -07:00
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usleep_range(3000, 5000);
|
2012-01-30 16:03:35 -07:00
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pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
|
2013-01-10 23:24:03 -07:00
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msleep(50);
|
2012-01-30 16:03:35 -07:00
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pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
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BCMA_CORE_PCI_CTL_RST_OE);
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/* 64 MB I/O access window. On 4716, use
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* sbtopcie0 to access the device registers. We
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* can't use address match 2 (1 GB window) region
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* as mips can't generate 64-bit address on the
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* backplane.
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*/
|
2012-06-29 16:44:38 -07:00
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if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4716 ||
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bus->chipinfo.id == BCMA_CHIP_ID_BCM4748) {
|
2012-01-30 16:03:35 -07:00
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pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
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pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
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BCMA_SOC_PCI_MEM_SZ - 1;
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pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
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BCMA_CORE_PCI_SBTOPCI_MEM | BCMA_SOC_PCI_MEM);
|
2012-06-29 16:44:38 -07:00
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} else if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
|
2012-01-30 16:03:35 -07:00
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tmp = BCMA_CORE_PCI_SBTOPCI_MEM;
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tmp |= BCMA_CORE_PCI_SBTOPCI_PREF;
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tmp |= BCMA_CORE_PCI_SBTOPCI_BURST;
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if (pc->core->core_unit == 0) {
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pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
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pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
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BCMA_SOC_PCI_MEM_SZ - 1;
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2012-09-29 11:40:18 -07:00
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pc_host->io_resource.start = 0x100;
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pc_host->io_resource.end = 0x47F;
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2012-01-30 16:03:35 -07:00
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pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
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pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
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tmp | BCMA_SOC_PCI_MEM);
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} else if (pc->core->core_unit == 1) {
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pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
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pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
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BCMA_SOC_PCI_MEM_SZ - 1;
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2012-09-29 11:40:18 -07:00
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pc_host->io_resource.start = 0x480;
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pc_host->io_resource.end = 0x7FF;
|
2012-01-30 16:03:35 -07:00
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pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
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pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
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pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
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tmp | BCMA_SOC_PCI1_MEM);
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}
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} else
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pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
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BCMA_CORE_PCI_SBTOPCI_IO);
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/* 64 MB configuration access window */
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pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
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/* 1 GB memory access window */
|
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pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI2,
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BCMA_CORE_PCI_SBTOPCI_MEM | pci_membase_1G);
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|
|
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|
|
|
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|
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/* As per PCI Express Base Spec 1.1 we need to wait for
|
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|
* at least 100 ms from the end of a reset (cold/warm/hot)
|
|
|
|
* before issuing configuration requests to PCI Express
|
|
|
|
* devices.
|
|
|
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*/
|
2012-09-25 01:17:22 -07:00
|
|
|
msleep(100);
|
2012-01-30 16:03:35 -07:00
|
|
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bcma_core_pci_enable_crs(pc);
|
|
|
|
|
2013-01-10 23:24:03 -07:00
|
|
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if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706 ||
|
|
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|
bus->chipinfo.id == BCMA_CHIP_ID_BCM4716) {
|
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|
u16 val16;
|
|
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|
bcma_extpci_read_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
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|
|
|
&val16, sizeof(val16));
|
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|
|
val16 |= (2 << 5); /* Max payload size of 512 */
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val16 |= (2 << 12); /* MRRS 512 */
|
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|
bcma_extpci_write_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
|
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|
|
&val16, sizeof(val16));
|
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|
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}
|
|
|
|
|
2012-01-30 16:03:35 -07:00
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|
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/* Enable PCI bridge BAR0 memory & master access */
|
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tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
|
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bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));
|
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|
|
|
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|
|
/* Enable PCI interrupts */
|
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pcicore_write32(pc, BCMA_CORE_PCI_IMASK, BCMA_CORE_PCI_IMASK_INTA);
|
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|
|
|
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|
|
/* Ok, ready to run, register it to the system.
|
|
|
|
* The following needs change, if we want to port hostmode
|
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|
* to non-MIPS platform. */
|
2012-05-04 21:56:33 -07:00
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|
io_map_base = (unsigned long)ioremap_nocache(pc_host->mem_resource.start,
|
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|
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resource_size(&pc_host->mem_resource));
|
2012-01-30 16:03:35 -07:00
|
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pc_host->pci_controller.io_map_base = io_map_base;
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set_io_port_base(pc_host->pci_controller.io_map_base);
|
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|
|
/* Give some time to the PCI controller to configure itself with the new
|
|
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|
* values. Not waiting at this point causes crashes of the machine. */
|
2012-09-25 01:17:22 -07:00
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|
|
usleep_range(10000, 15000);
|
2012-01-30 16:03:35 -07:00
|
|
|
register_pci_controller(&pc_host->pci_controller);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Early PCI fixup for a device on the PCI-core bridge. */
|
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|
|
static void bcma_core_pci_fixup_pcibridge(struct pci_dev *dev)
|
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|
|
{
|
|
|
|
if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
|
|
|
|
/* This is not a device on the PCI-core bridge. */
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (PCI_SLOT(dev->devfn) != 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
pr_info("PCI: Fixing up bridge %s\n", pci_name(dev));
|
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|
|
|
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|
|
/* Enable PCI bridge bus mastering and memory space */
|
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|
|
pci_set_master(dev);
|
|
|
|
if (pcibios_enable_device(dev, ~0) < 0) {
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|
|
|
pr_err("PCI: BCMA bridge enable failed\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Enable PCI bridge BAR1 prefetch and burst */
|
|
|
|
pci_write_config_dword(dev, BCMA_PCI_BAR1_CONTROL, 3);
|
|
|
|
}
|
|
|
|
DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_pcibridge);
|
|
|
|
|
|
|
|
/* Early PCI fixup for all PCI-cores to set the correct memory address. */
|
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|
|
static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
struct resource *res;
|
2012-11-26 16:30:04 -07:00
|
|
|
int pos, err;
|
2012-01-30 16:03:35 -07:00
|
|
|
|
|
|
|
if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
|
|
|
|
/* This is not a device on the PCI-core bridge. */
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (PCI_SLOT(dev->devfn) == 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
pr_info("PCI: Fixing up addresses %s\n", pci_name(dev));
|
|
|
|
|
|
|
|
for (pos = 0; pos < 6; pos++) {
|
|
|
|
res = &dev->resource[pos];
|
2012-11-26 16:30:04 -07:00
|
|
|
if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) {
|
|
|
|
err = pci_assign_resource(dev, pos);
|
|
|
|
if (err)
|
|
|
|
pr_err("PCI: Problem fixing up the addresses on %s\n",
|
|
|
|
pci_name(dev));
|
|
|
|
}
|
2012-01-30 16:03:35 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
|
|
|
|
|
|
|
|
/* This function is called when doing a pci_enable_device().
|
|
|
|
* We must first check if the device is a device on the PCI-core bridge. */
|
|
|
|
int bcma_core_pci_plat_dev_init(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
struct bcma_drv_pci_host *pc_host;
|
2013-08-23 14:22:29 -07:00
|
|
|
int readrq;
|
2012-01-30 16:03:35 -07:00
|
|
|
|
|
|
|
if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
|
|
|
|
/* This is not a device on the PCI-core bridge. */
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
|
|
|
|
pci_ops);
|
|
|
|
|
|
|
|
pr_info("PCI: Fixing up device %s\n", pci_name(dev));
|
|
|
|
|
|
|
|
/* Fix up interrupt lines */
|
2013-01-10 09:54:09 -07:00
|
|
|
dev->irq = bcma_core_irq(pc_host->pdev->core);
|
2012-01-30 16:03:35 -07:00
|
|
|
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
|
|
|
|
|
2013-08-23 14:22:29 -07:00
|
|
|
readrq = pcie_get_readrq(dev);
|
|
|
|
if (readrq > 128) {
|
|
|
|
pr_info("change PCIe max read request size from %i to 128\n", readrq);
|
|
|
|
pcie_set_readrq(dev, 128);
|
|
|
|
}
|
2012-01-30 16:03:35 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(bcma_core_pci_plat_dev_init);
|
|
|
|
|
|
|
|
/* PCI device IRQ mapping. */
|
|
|
|
int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
struct bcma_drv_pci_host *pc_host;
|
|
|
|
|
|
|
|
if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
|
|
|
|
/* This is not a device on the PCI-core bridge. */
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
|
|
|
|
pci_ops);
|
2013-01-10 09:54:09 -07:00
|
|
|
return bcma_core_irq(pc_host->pdev->core);
|
2011-07-05 10:48:26 -07:00
|
|
|
}
|
2012-01-30 16:03:35 -07:00
|
|
|
EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq);
|