2008-03-18 01:02:50 -07:00
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/*
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* OMAP2/3 System Control Module register access
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*
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* Copyright (C) 2007 Texas Instruments, Inc.
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* Copyright (C) 2007 Nokia Corporation
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*
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* Written by Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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2008-07-03 02:24:44 -07:00
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#include <linux/io.h>
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2008-03-18 01:02:50 -07:00
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2009-10-20 09:40:47 -07:00
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#include <plat/common.h>
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2008-09-26 05:18:46 -07:00
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#include <plat/sdrc.h>
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2010-10-08 10:40:20 -07:00
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2008-09-26 05:18:46 -07:00
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#include "cm-regbits-34xx.h"
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#include "prm-regbits-34xx.h"
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#include "cm.h"
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#include "prm.h"
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#include "sdrc.h"
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2010-10-08 09:56:37 -07:00
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#include "pm.h"
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2010-10-08 10:40:20 -07:00
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#include "control.h"
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2008-03-18 01:02:50 -07:00
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2008-07-03 02:24:44 -07:00
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static void __iomem *omap2_ctrl_base;
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2010-09-27 13:02:57 -07:00
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static void __iomem *omap4_ctrl_pad_base;
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2008-03-18 01:02:50 -07:00
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2008-09-26 05:19:02 -07:00
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#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
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2008-09-26 05:18:46 -07:00
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struct omap3_scratchpad {
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u32 boot_config_ptr;
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u32 public_restore_ptr;
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u32 secure_ram_restore_ptr;
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u32 sdrc_module_semaphore;
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u32 prcm_block_offset;
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u32 sdrc_block_offset;
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};
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struct omap3_scratchpad_prcm_block {
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u32 prm_clksrc_ctrl;
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u32 prm_clksel;
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u32 cm_clksel_core;
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u32 cm_clksel_wkup;
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u32 cm_clken_pll;
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u32 cm_autoidle_pll;
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u32 cm_clksel1_pll;
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u32 cm_clksel2_pll;
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u32 cm_clksel3_pll;
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u32 cm_clken_pll_mpu;
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u32 cm_autoidle_pll_mpu;
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u32 cm_clksel1_pll_mpu;
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u32 cm_clksel2_pll_mpu;
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u32 prcm_block_size;
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};
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struct omap3_scratchpad_sdrc_block {
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u16 sysconfig;
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u16 cs_cfg;
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u16 sharing;
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u16 err_type;
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u32 dll_a_ctrl;
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u32 dll_b_ctrl;
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u32 power;
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u32 cs_0;
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u32 mcfg_0;
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u16 mr_0;
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u16 emr_1_0;
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u16 emr_2_0;
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u16 emr_3_0;
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u32 actim_ctrla_0;
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u32 actim_ctrlb_0;
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u32 rfr_ctrl_0;
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u32 cs_1;
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u32 mcfg_1;
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u16 mr_1;
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u16 emr_1_1;
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u16 emr_2_1;
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u16 emr_3_1;
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u32 actim_ctrla_1;
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u32 actim_ctrlb_1;
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u32 rfr_ctrl_1;
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u16 dcdl_1_ctrl;
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u16 dcdl_2_ctrl;
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u32 flags;
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u32 block_size;
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};
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2008-10-13 03:15:00 -07:00
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void *omap3_secure_ram_storage;
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2008-09-26 05:18:46 -07:00
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/*
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* This is used to store ARM registers in SDRAM before attempting
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* an MPU OFF. The save and restore happens from the SRAM sleep code.
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* The address is stored in scratchpad, so that it can be used
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* during the restore path.
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*/
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u32 omap3_arm_context[128];
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2008-09-26 05:19:02 -07:00
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struct omap3_control_regs {
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u32 sysconfig;
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u32 devconf0;
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u32 mem_dftrw0;
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u32 mem_dftrw1;
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u32 msuspendmux_0;
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u32 msuspendmux_1;
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u32 msuspendmux_2;
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u32 msuspendmux_3;
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u32 msuspendmux_4;
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u32 msuspendmux_5;
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u32 sec_ctrl;
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u32 devconf1;
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u32 csirxfe;
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u32 iva2_bootaddr;
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u32 iva2_bootmod;
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u32 debobs_0;
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u32 debobs_1;
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u32 debobs_2;
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u32 debobs_3;
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u32 debobs_4;
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u32 debobs_5;
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u32 debobs_6;
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u32 debobs_7;
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u32 debobs_8;
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u32 prog_io0;
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u32 prog_io1;
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u32 dss_dpll_spreading;
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u32 core_dpll_spreading;
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u32 per_dpll_spreading;
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u32 usbhost_dpll_spreading;
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u32 pbias_lite;
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u32 temp_sensor;
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u32 sramldo4;
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u32 sramldo5;
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u32 csi;
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};
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static struct omap3_control_regs control_context;
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#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
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2008-07-03 02:24:44 -07:00
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#define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg))
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2010-09-27 13:02:57 -07:00
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#define OMAP4_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg))
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2008-03-18 01:02:50 -07:00
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2008-07-03 02:24:44 -07:00
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void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
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2008-03-18 01:02:50 -07:00
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{
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2010-02-15 05:33:37 -07:00
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/* Static mapping, never released */
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if (omap2_globals->ctrl) {
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omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K);
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WARN_ON(!omap2_ctrl_base);
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}
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2010-09-27 13:02:57 -07:00
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/* Static mapping, never released */
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if (omap2_globals->ctrl_pad) {
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omap4_ctrl_pad_base = ioremap(omap2_globals->ctrl_pad, SZ_4K);
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WARN_ON(!omap4_ctrl_pad_base);
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}
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2008-03-18 01:02:50 -07:00
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}
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2008-07-03 02:24:44 -07:00
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void __iomem *omap_ctrl_base_get(void)
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2008-03-18 01:02:50 -07:00
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{
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return omap2_ctrl_base;
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}
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u8 omap_ctrl_readb(u16 offset)
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{
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return __raw_readb(OMAP_CTRL_REGADDR(offset));
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}
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u16 omap_ctrl_readw(u16 offset)
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{
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return __raw_readw(OMAP_CTRL_REGADDR(offset));
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}
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u32 omap_ctrl_readl(u16 offset)
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{
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return __raw_readl(OMAP_CTRL_REGADDR(offset));
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}
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void omap_ctrl_writeb(u8 val, u16 offset)
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{
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__raw_writeb(val, OMAP_CTRL_REGADDR(offset));
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}
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void omap_ctrl_writew(u16 val, u16 offset)
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{
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__raw_writew(val, OMAP_CTRL_REGADDR(offset));
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}
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void omap_ctrl_writel(u32 val, u16 offset)
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{
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__raw_writel(val, OMAP_CTRL_REGADDR(offset));
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}
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2010-09-27 13:02:57 -07:00
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/*
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* On OMAP4 control pad are not addressable from control
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* core base. So the common omap_ctrl_read/write APIs breaks
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* Hence export separate APIs to manage the omap4 pad control
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* registers. This APIs will work only for OMAP4
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*/
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u32 omap4_ctrl_pad_readl(u16 offset)
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{
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return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset));
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}
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void omap4_ctrl_pad_writel(u32 val, u16 offset)
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{
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__raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset));
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}
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2008-09-26 05:19:02 -07:00
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#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
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2008-09-26 05:18:46 -07:00
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/*
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* Clears the scratchpad contents in case of cold boot-
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* called during bootup
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*/
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void omap3_clear_scratchpad_contents(void)
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{
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u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
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2010-10-08 09:56:11 -07:00
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void __iomem *v_addr;
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2008-09-26 05:18:46 -07:00
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u32 offset = 0;
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v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
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if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
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2010-05-18 17:47:24 -07:00
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OMAP3430_GLOBAL_COLD_RST_MASK) {
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2008-09-26 05:18:46 -07:00
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for ( ; offset <= max_offset; offset += 0x4)
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__raw_writel(0x0, (v_addr + offset));
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2010-05-18 17:47:24 -07:00
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prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
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OMAP3430_GR_MOD,
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OMAP3_PRM_RSTST_OFFSET);
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2008-09-26 05:18:46 -07:00
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}
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}
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/* Populate the scratchpad structure with restore structure */
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void omap3_save_scratchpad_contents(void)
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{
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2010-10-08 09:56:11 -07:00
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void __iomem *scratchpad_address;
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2008-09-26 05:18:46 -07:00
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u32 arm_context_addr;
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struct omap3_scratchpad scratchpad_contents;
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struct omap3_scratchpad_prcm_block prcm_block_contents;
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struct omap3_scratchpad_sdrc_block sdrc_block_contents;
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/* Populate the Scratchpad contents */
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scratchpad_contents.boot_config_ptr = 0x0;
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2008-10-13 07:58:50 -07:00
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if (omap_rev() != OMAP3430_REV_ES3_0 &&
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omap_rev() != OMAP3430_REV_ES3_1)
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scratchpad_contents.public_restore_ptr =
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virt_to_phys(get_restore_pointer());
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else
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scratchpad_contents.public_restore_ptr =
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virt_to_phys(get_es3_restore_pointer());
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2008-10-13 03:15:00 -07:00
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if (omap_type() == OMAP2_DEVICE_TYPE_GP)
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scratchpad_contents.secure_ram_restore_ptr = 0x0;
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else
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scratchpad_contents.secure_ram_restore_ptr =
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(u32) __pa(omap3_secure_ram_storage);
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2008-09-26 05:18:46 -07:00
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scratchpad_contents.sdrc_module_semaphore = 0x0;
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scratchpad_contents.prcm_block_offset = 0x2C;
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scratchpad_contents.sdrc_block_offset = 0x64;
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/* Populate the PRCM block contents */
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prcm_block_contents.prm_clksrc_ctrl = prm_read_mod_reg(OMAP3430_GR_MOD,
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OMAP3_PRM_CLKSRC_CTRL_OFFSET);
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prcm_block_contents.prm_clksel = prm_read_mod_reg(OMAP3430_CCR_MOD,
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OMAP3_PRM_CLKSEL_OFFSET);
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prcm_block_contents.cm_clksel_core =
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cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
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prcm_block_contents.cm_clksel_wkup =
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cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
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prcm_block_contents.cm_clken_pll =
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2009-05-12 04:02:16 -07:00
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cm_read_mod_reg(PLL_MOD, CM_CLKEN);
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2008-09-26 05:18:46 -07:00
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prcm_block_contents.cm_autoidle_pll =
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cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL);
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prcm_block_contents.cm_clksel1_pll =
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cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
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prcm_block_contents.cm_clksel2_pll =
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cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
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prcm_block_contents.cm_clksel3_pll =
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cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
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prcm_block_contents.cm_clken_pll_mpu =
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cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
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prcm_block_contents.cm_autoidle_pll_mpu =
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cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
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prcm_block_contents.cm_clksel1_pll_mpu =
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cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
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prcm_block_contents.cm_clksel2_pll_mpu =
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cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
|
|
|
|
|
prcm_block_contents.prcm_block_size = 0x0;
|
|
|
|
|
|
|
|
|
|
/* Populate the SDRC block contents */
|
|
|
|
|
sdrc_block_contents.sysconfig =
|
|
|
|
|
(sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
|
|
|
|
|
sdrc_block_contents.cs_cfg =
|
|
|
|
|
(sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
|
|
|
|
|
sdrc_block_contents.sharing =
|
|
|
|
|
(sdrc_read_reg(SDRC_SHARING) & 0xFFFF);
|
|
|
|
|
sdrc_block_contents.err_type =
|
|
|
|
|
(sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);
|
|
|
|
|
sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);
|
|
|
|
|
sdrc_block_contents.dll_b_ctrl = 0x0;
|
2009-06-09 10:00:41 -07:00
|
|
|
/*
|
|
|
|
|
* Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
|
|
|
|
|
* be programed to issue automatic self refresh on timeout
|
|
|
|
|
* of AUTO_CNT = 1 prior to any transition to OFF mode.
|
|
|
|
|
*/
|
|
|
|
|
if ((omap_type() != OMAP2_DEVICE_TYPE_GP)
|
|
|
|
|
&& (omap_rev() >= OMAP3430_REV_ES3_0))
|
|
|
|
|
sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &
|
|
|
|
|
~(SDRC_POWER_AUTOCOUNT_MASK|
|
|
|
|
|
SDRC_POWER_CLKCTRL_MASK)) |
|
|
|
|
|
(1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
|
|
|
|
|
SDRC_SELF_REFRESH_ON_AUTOCOUNT;
|
|
|
|
|
else
|
|
|
|
|
sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);
|
|
|
|
|
|
2008-09-26 05:18:46 -07:00
|
|
|
sdrc_block_contents.cs_0 = 0x0;
|
|
|
|
|
sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);
|
|
|
|
|
sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);
|
|
|
|
|
sdrc_block_contents.emr_1_0 = 0x0;
|
|
|
|
|
sdrc_block_contents.emr_2_0 = 0x0;
|
|
|
|
|
sdrc_block_contents.emr_3_0 = 0x0;
|
|
|
|
|
sdrc_block_contents.actim_ctrla_0 =
|
|
|
|
|
sdrc_read_reg(SDRC_ACTIM_CTRL_A_0);
|
|
|
|
|
sdrc_block_contents.actim_ctrlb_0 =
|
|
|
|
|
sdrc_read_reg(SDRC_ACTIM_CTRL_B_0);
|
|
|
|
|
sdrc_block_contents.rfr_ctrl_0 =
|
|
|
|
|
sdrc_read_reg(SDRC_RFR_CTRL_0);
|
|
|
|
|
sdrc_block_contents.cs_1 = 0x0;
|
|
|
|
|
sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1);
|
|
|
|
|
sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF;
|
|
|
|
|
sdrc_block_contents.emr_1_1 = 0x0;
|
|
|
|
|
sdrc_block_contents.emr_2_1 = 0x0;
|
|
|
|
|
sdrc_block_contents.emr_3_1 = 0x0;
|
|
|
|
|
sdrc_block_contents.actim_ctrla_1 =
|
|
|
|
|
sdrc_read_reg(SDRC_ACTIM_CTRL_A_1);
|
|
|
|
|
sdrc_block_contents.actim_ctrlb_1 =
|
|
|
|
|
sdrc_read_reg(SDRC_ACTIM_CTRL_B_1);
|
|
|
|
|
sdrc_block_contents.rfr_ctrl_1 =
|
|
|
|
|
sdrc_read_reg(SDRC_RFR_CTRL_1);
|
|
|
|
|
sdrc_block_contents.dcdl_1_ctrl = 0x0;
|
|
|
|
|
sdrc_block_contents.dcdl_2_ctrl = 0x0;
|
|
|
|
|
sdrc_block_contents.flags = 0x0;
|
|
|
|
|
sdrc_block_contents.block_size = 0x0;
|
|
|
|
|
|
|
|
|
|
arm_context_addr = virt_to_phys(omap3_arm_context);
|
|
|
|
|
|
|
|
|
|
/* Copy all the contents to the scratchpad location */
|
|
|
|
|
scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
|
|
|
|
|
memcpy_toio(scratchpad_address, &scratchpad_contents,
|
|
|
|
|
sizeof(scratchpad_contents));
|
|
|
|
|
/* Scratchpad contents being 32 bits, a divide by 4 done here */
|
|
|
|
|
memcpy_toio(scratchpad_address +
|
|
|
|
|
scratchpad_contents.prcm_block_offset,
|
|
|
|
|
&prcm_block_contents, sizeof(prcm_block_contents));
|
|
|
|
|
memcpy_toio(scratchpad_address +
|
|
|
|
|
scratchpad_contents.sdrc_block_offset,
|
|
|
|
|
&sdrc_block_contents, sizeof(sdrc_block_contents));
|
|
|
|
|
/*
|
|
|
|
|
* Copies the address of the location in SDRAM where ARM
|
|
|
|
|
* registers get saved during a MPU OFF transition.
|
|
|
|
|
*/
|
|
|
|
|
memcpy_toio(scratchpad_address +
|
|
|
|
|
scratchpad_contents.sdrc_block_offset +
|
|
|
|
|
sizeof(sdrc_block_contents), &arm_context_addr, 4);
|
|
|
|
|
}
|
|
|
|
|
|
2008-09-26 05:19:02 -07:00
|
|
|
void omap3_control_save_context(void)
|
|
|
|
|
{
|
|
|
|
|
control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG);
|
|
|
|
|
control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
|
|
|
|
|
control_context.mem_dftrw0 =
|
|
|
|
|
omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0);
|
|
|
|
|
control_context.mem_dftrw1 =
|
|
|
|
|
omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1);
|
|
|
|
|
control_context.msuspendmux_0 =
|
|
|
|
|
omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0);
|
|
|
|
|
control_context.msuspendmux_1 =
|
|
|
|
|
omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1);
|
|
|
|
|
control_context.msuspendmux_2 =
|
|
|
|
|
omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2);
|
|
|
|
|
control_context.msuspendmux_3 =
|
|
|
|
|
omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3);
|
|
|
|
|
control_context.msuspendmux_4 =
|
|
|
|
|
omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4);
|
|
|
|
|
control_context.msuspendmux_5 =
|
|
|
|
|
omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5);
|
|
|
|
|
control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL);
|
|
|
|
|
control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
|
|
|
|
|
control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE);
|
|
|
|
|
control_context.iva2_bootaddr =
|
|
|
|
|
omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR);
|
|
|
|
|
control_context.iva2_bootmod =
|
|
|
|
|
omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD);
|
|
|
|
|
control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0));
|
|
|
|
|
control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1));
|
|
|
|
|
control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2));
|
|
|
|
|
control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3));
|
|
|
|
|
control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4));
|
|
|
|
|
control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5));
|
|
|
|
|
control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6));
|
|
|
|
|
control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7));
|
|
|
|
|
control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8));
|
|
|
|
|
control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0);
|
|
|
|
|
control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
|
|
|
|
|
control_context.dss_dpll_spreading =
|
|
|
|
|
omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING);
|
|
|
|
|
control_context.core_dpll_spreading =
|
|
|
|
|
omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING);
|
|
|
|
|
control_context.per_dpll_spreading =
|
|
|
|
|
omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING);
|
|
|
|
|
control_context.usbhost_dpll_spreading =
|
|
|
|
|
omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
|
|
|
|
|
control_context.pbias_lite =
|
|
|
|
|
omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
|
|
|
|
|
control_context.temp_sensor =
|
|
|
|
|
omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR);
|
|
|
|
|
control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);
|
|
|
|
|
control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);
|
|
|
|
|
control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void omap3_control_restore_context(void)
|
|
|
|
|
{
|
|
|
|
|
omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG);
|
|
|
|
|
omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0);
|
|
|
|
|
omap_ctrl_writel(control_context.mem_dftrw0,
|
|
|
|
|
OMAP343X_CONTROL_MEM_DFTRW0);
|
|
|
|
|
omap_ctrl_writel(control_context.mem_dftrw1,
|
|
|
|
|
OMAP343X_CONTROL_MEM_DFTRW1);
|
|
|
|
|
omap_ctrl_writel(control_context.msuspendmux_0,
|
|
|
|
|
OMAP2_CONTROL_MSUSPENDMUX_0);
|
|
|
|
|
omap_ctrl_writel(control_context.msuspendmux_1,
|
|
|
|
|
OMAP2_CONTROL_MSUSPENDMUX_1);
|
|
|
|
|
omap_ctrl_writel(control_context.msuspendmux_2,
|
|
|
|
|
OMAP2_CONTROL_MSUSPENDMUX_2);
|
|
|
|
|
omap_ctrl_writel(control_context.msuspendmux_3,
|
|
|
|
|
OMAP2_CONTROL_MSUSPENDMUX_3);
|
|
|
|
|
omap_ctrl_writel(control_context.msuspendmux_4,
|
|
|
|
|
OMAP2_CONTROL_MSUSPENDMUX_4);
|
|
|
|
|
omap_ctrl_writel(control_context.msuspendmux_5,
|
|
|
|
|
OMAP2_CONTROL_MSUSPENDMUX_5);
|
|
|
|
|
omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL);
|
|
|
|
|
omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1);
|
|
|
|
|
omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE);
|
|
|
|
|
omap_ctrl_writel(control_context.iva2_bootaddr,
|
|
|
|
|
OMAP343X_CONTROL_IVA2_BOOTADDR);
|
|
|
|
|
omap_ctrl_writel(control_context.iva2_bootmod,
|
|
|
|
|
OMAP343X_CONTROL_IVA2_BOOTMOD);
|
|
|
|
|
omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0));
|
|
|
|
|
omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1));
|
|
|
|
|
omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2));
|
|
|
|
|
omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3));
|
|
|
|
|
omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4));
|
|
|
|
|
omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5));
|
|
|
|
|
omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6));
|
|
|
|
|
omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7));
|
|
|
|
|
omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8));
|
|
|
|
|
omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0);
|
|
|
|
|
omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1);
|
|
|
|
|
omap_ctrl_writel(control_context.dss_dpll_spreading,
|
|
|
|
|
OMAP343X_CONTROL_DSS_DPLL_SPREADING);
|
|
|
|
|
omap_ctrl_writel(control_context.core_dpll_spreading,
|
|
|
|
|
OMAP343X_CONTROL_CORE_DPLL_SPREADING);
|
|
|
|
|
omap_ctrl_writel(control_context.per_dpll_spreading,
|
|
|
|
|
OMAP343X_CONTROL_PER_DPLL_SPREADING);
|
|
|
|
|
omap_ctrl_writel(control_context.usbhost_dpll_spreading,
|
|
|
|
|
OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
|
|
|
|
|
omap_ctrl_writel(control_context.pbias_lite,
|
|
|
|
|
OMAP343X_CONTROL_PBIAS_LITE);
|
|
|
|
|
omap_ctrl_writel(control_context.temp_sensor,
|
|
|
|
|
OMAP343X_CONTROL_TEMP_SENSOR);
|
|
|
|
|
omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4);
|
|
|
|
|
omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5);
|
|
|
|
|
omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
|
