2019-05-26 23:55:06 -07:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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2017-03-13 12:07:26 -07:00
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/*
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2005-04-16 15:20:36 -07:00
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* Copyright (c) 2004 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C2410 Watchdog Timer Support
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*
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* Based on, softdog.c by Alan Cox,
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2008-10-27 08:17:56 -07:00
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* (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
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2017-03-13 12:07:26 -07:00
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*/
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2005-04-16 15:20:36 -07:00
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2023-12-11 09:23:25 -07:00
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#include <linux/bits.h>
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2005-04-16 15:20:36 -07:00
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/types.h>
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#include <linux/timer.h>
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#include <linux/watchdog.h>
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2005-10-29 11:07:23 -07:00
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#include <linux/platform_device.h>
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2005-04-16 15:20:36 -07:00
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#include <linux/interrupt.h>
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2006-01-07 09:15:52 -07:00
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#include <linux/clk.h>
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2008-08-04 09:54:46 -07:00
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#include <linux/uaccess.h>
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#include <linux/io.h>
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2009-10-29 17:30:25 -07:00
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#include <linux/cpufreq.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 01:04:11 -07:00
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#include <linux/slab.h>
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2011-09-26 06:40:14 -07:00
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#include <linux/err.h>
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2012-05-02 22:24:17 -07:00
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#include <linux/of.h>
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2013-12-05 22:47:47 -07:00
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#include <linux/regmap.h>
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2014-08-19 17:45:36 -07:00
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#include <linux/delay.h>
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2024-02-20 15:06:13 -07:00
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#include <linux/soc/samsung/exynos-pmu.h>
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2005-04-16 15:20:36 -07:00
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2013-06-17 07:45:24 -07:00
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#define S3C2410_WTCON 0x00
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#define S3C2410_WTDAT 0x04
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#define S3C2410_WTCNT 0x08
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2017-02-24 08:11:16 -07:00
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#define S3C2410_WTCLRINT 0x0c
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2005-04-16 15:20:36 -07:00
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2016-03-01 09:45:17 -07:00
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#define S3C2410_WTCNT_MAXCNT 0xffff
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2023-12-11 09:23:25 -07:00
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#define S3C2410_WTCON_RSTEN BIT(0)
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#define S3C2410_WTCON_INTEN BIT(2)
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#define S3C2410_WTCON_ENABLE BIT(5)
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#define S3C2410_WTCON_DBGACK_MASK BIT(16)
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2005-04-16 15:20:36 -07:00
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2013-06-17 07:45:24 -07:00
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#define S3C2410_WTCON_DIV16 (0 << 3)
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#define S3C2410_WTCON_DIV32 (1 << 3)
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#define S3C2410_WTCON_DIV64 (2 << 3)
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#define S3C2410_WTCON_DIV128 (3 << 3)
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2016-03-01 09:45:17 -07:00
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#define S3C2410_WTCON_MAXDIV 0x80
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2013-06-17 07:45:24 -07:00
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#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
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#define S3C2410_WTCON_PRESCALE_MASK (0xff << 8)
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2016-03-01 09:45:17 -07:00
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#define S3C2410_WTCON_PRESCALE_MAX 0xff
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2005-04-16 15:20:36 -07:00
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2017-02-24 08:11:15 -07:00
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#define S3C2410_WATCHDOG_ATBOOT (0)
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#define S3C2410_WATCHDOG_DEFAULT_TIME (15)
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2005-04-16 15:20:36 -07:00
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2013-12-06 14:08:07 -07:00
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#define EXYNOS5_RST_STAT_REG_OFFSET 0x0404
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2013-12-05 22:47:47 -07:00
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#define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408
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#define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c
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2021-11-21 09:56:47 -07:00
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#define EXYNOS850_CLUSTER0_NONCPU_OUT 0x1220
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#define EXYNOS850_CLUSTER0_NONCPU_INT_EN 0x1244
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#define EXYNOS850_CLUSTER1_NONCPU_OUT 0x1620
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#define EXYNOS850_CLUSTER1_NONCPU_INT_EN 0x1644
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2022-05-20 05:17:48 -07:00
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#define EXYNOSAUTOV9_CLUSTER1_NONCPU_OUT 0x1520
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#define EXYNOSAUTOV9_CLUSTER1_NONCPU_INT_EN 0x1544
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2021-11-21 09:56:47 -07:00
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#define EXYNOS850_CLUSTER0_WDTRESET_BIT 24
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#define EXYNOS850_CLUSTER1_WDTRESET_BIT 23
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2022-05-20 05:17:48 -07:00
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#define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT 25
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#define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT 24
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2021-11-23 16:26:13 -07:00
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2023-12-11 09:23:27 -07:00
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#define GS_CLUSTER0_NONCPU_OUT 0x1220
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#define GS_CLUSTER1_NONCPU_OUT 0x1420
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#define GS_CLUSTER0_NONCPU_INT_EN 0x1244
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#define GS_CLUSTER1_NONCPU_INT_EN 0x1444
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#define GS_CLUSTER2_NONCPU_INT_EN 0x1644
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#define GS_RST_STAT_REG_OFFSET 0x3B44
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2021-11-23 16:26:13 -07:00
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/**
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* DOC: Quirk flags for different Samsung watchdog IP-cores
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*
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* This driver supports multiple Samsung SoCs, each of which might have
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* different set of registers and features supported. As watchdog block
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* sometimes requires modifying PMU registers for proper functioning, register
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* differences in both watchdog and PMU IP-cores should be accounted for. Quirk
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* flags described below serve the purpose of telling the driver about mentioned
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* SoC traits, and can be specified in driver data for each particular supported
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* device.
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*
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* %QUIRK_HAS_WTCLRINT_REG: Watchdog block has WTCLRINT register. It's used to
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* clear the interrupt once the interrupt service routine is complete. It's
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* write-only, writing any values to this register clears the interrupt, but
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* reading is not permitted.
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*
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* %QUIRK_HAS_PMU_MASK_RESET: PMU block has the register for disabling/enabling
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* WDT reset request. On old SoCs it's usually called MASK_WDT_RESET_REQUEST,
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* new SoCs have CLUSTERx_NONCPU_INT_EN register, which 'mask_bit' value is
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* inverted compared to the former one.
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*
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* %QUIRK_HAS_PMU_RST_STAT: PMU block has RST_STAT (reset status) register,
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* which contains bits indicating the reason for most recent CPU reset. If
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* present, driver will use this register to check if previous reboot was due to
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* watchdog timer reset.
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*
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* %QUIRK_HAS_PMU_AUTO_DISABLE: PMU block has AUTOMATIC_WDT_RESET_DISABLE
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* register. If 'mask_bit' bit is set, PMU will disable WDT reset when
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* corresponding processor is in reset state.
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*
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* %QUIRK_HAS_PMU_CNT_EN: PMU block has some register (e.g. CLUSTERx_NONCPU_OUT)
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* with "watchdog counter enable" bit. That bit should be set to make watchdog
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* counter running.
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2023-12-11 09:23:25 -07:00
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*
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* %QUIRK_HAS_DBGACK_BIT: WTCON register has DBGACK_MASK bit. Setting the
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* DBGACK_MASK bit disables the watchdog outputs when the SoC is in debug mode.
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* Debug mode is determined by the DBGACK CPU signal.
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2021-11-23 16:26:13 -07:00
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*/
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2023-12-11 09:23:26 -07:00
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#define QUIRK_HAS_WTCLRINT_REG BIT(0)
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#define QUIRK_HAS_PMU_MASK_RESET BIT(1)
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#define QUIRK_HAS_PMU_RST_STAT BIT(2)
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#define QUIRK_HAS_PMU_AUTO_DISABLE BIT(3)
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#define QUIRK_HAS_PMU_CNT_EN BIT(4)
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2023-12-11 09:23:25 -07:00
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#define QUIRK_HAS_DBGACK_BIT BIT(5)
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2013-12-06 14:08:07 -07:00
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/* These quirks require that we have a PMU register map */
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2021-11-23 16:26:13 -07:00
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#define QUIRKS_HAVE_PMUREG \
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(QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_RST_STAT | \
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QUIRK_HAS_PMU_AUTO_DISABLE | QUIRK_HAS_PMU_CNT_EN)
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2013-12-05 22:47:47 -07:00
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2012-03-05 08:51:11 -07:00
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static bool nowayout = WATCHDOG_NOWAYOUT;
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2013-02-14 01:14:25 -07:00
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static int tmr_margin;
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2017-02-24 08:11:15 -07:00
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static int tmr_atboot = S3C2410_WATCHDOG_ATBOOT;
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2008-08-04 09:54:46 -07:00
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static int soft_noboot;
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2005-04-16 15:20:36 -07:00
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module_param(tmr_margin, int, 0);
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module_param(tmr_atboot, int, 0);
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2012-03-05 08:51:11 -07:00
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module_param(nowayout, bool, 0);
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2005-04-16 15:20:36 -07:00
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module_param(soft_noboot, int, 0);
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2010-05-01 09:46:15 -07:00
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MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default="
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2017-02-24 08:11:15 -07:00
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__MODULE_STRING(S3C2410_WATCHDOG_DEFAULT_TIME) ")");
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2008-08-04 09:54:46 -07:00
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MODULE_PARM_DESC(tmr_atboot,
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"Watchdog is started at boot time if set to 1, default="
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2017-02-24 08:11:15 -07:00
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__MODULE_STRING(S3C2410_WATCHDOG_ATBOOT));
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2008-08-04 09:54:46 -07:00
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MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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2017-03-13 12:07:26 -07:00
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MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, 0 to reboot (default 0)");
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2005-04-16 15:20:36 -07:00
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2013-12-05 22:47:47 -07:00
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/**
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* struct s3c2410_wdt_variant - Per-variant config data
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*
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* @disable_reg: Offset in pmureg for the register that disables the watchdog
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* timer reset functionality.
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* @mask_reset_reg: Offset in pmureg for the register that masks the watchdog
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* timer reset functionality.
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2021-11-21 09:56:42 -07:00
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* @mask_reset_inv: If set, mask_reset_reg value will have inverted meaning.
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2013-12-05 22:47:47 -07:00
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* @mask_bit: Bit number for the watchdog timer in the disable register and the
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* mask reset register.
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2013-12-06 14:08:07 -07:00
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* @rst_stat_reg: Offset in pmureg for the register that has the reset status.
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* @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog
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* reset.
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2021-11-21 09:56:43 -07:00
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* @cnt_en_reg: Offset in pmureg for the register that enables WDT counter.
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* @cnt_en_bit: Bit number for "watchdog counter enable" in cnt_en register.
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2013-12-05 22:47:47 -07:00
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* @quirks: A bitfield of quirks.
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*/
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struct s3c2410_wdt_variant {
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int disable_reg;
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int mask_reset_reg;
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2021-11-21 09:56:42 -07:00
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bool mask_reset_inv;
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2013-12-05 22:47:47 -07:00
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int mask_bit;
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2013-12-06 14:08:07 -07:00
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int rst_stat_reg;
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int rst_stat_bit;
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2021-11-21 09:56:43 -07:00
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int cnt_en_reg;
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int cnt_en_bit;
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2013-12-05 22:47:47 -07:00
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u32 quirks;
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};
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2013-08-27 03:06:03 -07:00
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struct s3c2410_wdt {
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struct device *dev;
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2021-11-21 09:56:45 -07:00
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struct clk *bus_clk; /* for register interface (PCLK) */
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struct clk *src_clk; /* for WDT counter */
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2013-08-27 03:06:03 -07:00
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void __iomem *reg_base;
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unsigned int count;
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spinlock_t lock;
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unsigned long wtcon_save;
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unsigned long wtdat_save;
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struct watchdog_device wdt_device;
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struct notifier_block freq_transition;
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2017-03-13 12:07:24 -07:00
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const struct s3c2410_wdt_variant *drv_data;
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2013-12-05 22:47:47 -07:00
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struct regmap *pmureg;
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};
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static const struct s3c2410_wdt_variant drv_data_s3c2410 = {
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.quirks = 0
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};
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#ifdef CONFIG_OF
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2017-02-24 08:11:16 -07:00
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static const struct s3c2410_wdt_variant drv_data_s3c6410 = {
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.quirks = QUIRK_HAS_WTCLRINT_REG,
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};
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2013-12-05 22:47:47 -07:00
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static const struct s3c2410_wdt_variant drv_data_exynos5250 = {
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.disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
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.mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
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.mask_bit = 20,
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2013-12-06 14:08:07 -07:00
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.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
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.rst_stat_bit = 20,
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2021-11-23 16:26:13 -07:00
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.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \
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QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_AUTO_DISABLE,
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2013-12-05 22:47:47 -07:00
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};
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static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
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.disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
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.mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
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.mask_bit = 0,
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2013-12-06 14:08:07 -07:00
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.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
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.rst_stat_bit = 9,
|
2021-11-23 16:26:13 -07:00
|
|
|
.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \
|
|
|
|
QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_AUTO_DISABLE,
|
2013-12-05 22:47:47 -07:00
|
|
|
};
|
|
|
|
|
2014-08-27 02:47:11 -07:00
|
|
|
static const struct s3c2410_wdt_variant drv_data_exynos7 = {
|
|
|
|
.disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
|
|
|
|
.mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
|
2014-10-17 09:12:53 -07:00
|
|
|
.mask_bit = 23,
|
2014-08-27 02:47:11 -07:00
|
|
|
.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
|
|
|
|
.rst_stat_bit = 23, /* A57 WDTRESET */
|
2021-11-23 16:26:13 -07:00
|
|
|
.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \
|
|
|
|
QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_AUTO_DISABLE,
|
2014-08-27 02:47:11 -07:00
|
|
|
};
|
|
|
|
|
2021-11-21 09:56:47 -07:00
|
|
|
static const struct s3c2410_wdt_variant drv_data_exynos850_cl0 = {
|
|
|
|
.mask_reset_reg = EXYNOS850_CLUSTER0_NONCPU_INT_EN,
|
|
|
|
.mask_bit = 2,
|
|
|
|
.mask_reset_inv = true,
|
|
|
|
.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
|
|
|
|
.rst_stat_bit = EXYNOS850_CLUSTER0_WDTRESET_BIT,
|
|
|
|
.cnt_en_reg = EXYNOS850_CLUSTER0_NONCPU_OUT,
|
|
|
|
.cnt_en_bit = 7,
|
|
|
|
.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \
|
|
|
|
QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct s3c2410_wdt_variant drv_data_exynos850_cl1 = {
|
|
|
|
.mask_reset_reg = EXYNOS850_CLUSTER1_NONCPU_INT_EN,
|
|
|
|
.mask_bit = 2,
|
|
|
|
.mask_reset_inv = true,
|
|
|
|
.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
|
|
|
|
.rst_stat_bit = EXYNOS850_CLUSTER1_WDTRESET_BIT,
|
|
|
|
.cnt_en_reg = EXYNOS850_CLUSTER1_NONCPU_OUT,
|
|
|
|
.cnt_en_bit = 7,
|
|
|
|
.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \
|
|
|
|
QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN,
|
|
|
|
};
|
|
|
|
|
2022-05-20 05:17:48 -07:00
|
|
|
static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl0 = {
|
|
|
|
.mask_reset_reg = EXYNOS850_CLUSTER0_NONCPU_INT_EN,
|
|
|
|
.mask_bit = 2,
|
|
|
|
.mask_reset_inv = true,
|
|
|
|
.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
|
|
|
|
.rst_stat_bit = EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT,
|
|
|
|
.cnt_en_reg = EXYNOS850_CLUSTER0_NONCPU_OUT,
|
|
|
|
.cnt_en_bit = 7,
|
|
|
|
.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
|
|
|
|
QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl1 = {
|
|
|
|
.mask_reset_reg = EXYNOSAUTOV9_CLUSTER1_NONCPU_INT_EN,
|
|
|
|
.mask_bit = 2,
|
|
|
|
.mask_reset_inv = true,
|
|
|
|
.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
|
|
|
|
.rst_stat_bit = EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT,
|
|
|
|
.cnt_en_reg = EXYNOSAUTOV9_CLUSTER1_NONCPU_OUT,
|
|
|
|
.cnt_en_bit = 7,
|
|
|
|
.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
|
|
|
|
QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN,
|
|
|
|
};
|
|
|
|
|
2023-12-11 09:23:27 -07:00
|
|
|
static const struct s3c2410_wdt_variant drv_data_gs101_cl0 = {
|
|
|
|
.mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN,
|
|
|
|
.mask_bit = 2,
|
|
|
|
.mask_reset_inv = true,
|
|
|
|
.rst_stat_reg = GS_RST_STAT_REG_OFFSET,
|
|
|
|
.rst_stat_bit = 0,
|
|
|
|
.cnt_en_reg = GS_CLUSTER0_NONCPU_OUT,
|
|
|
|
.cnt_en_bit = 8,
|
|
|
|
.quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET |
|
|
|
|
QUIRK_HAS_PMU_CNT_EN | QUIRK_HAS_WTCLRINT_REG |
|
|
|
|
QUIRK_HAS_DBGACK_BIT,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = {
|
|
|
|
.mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN,
|
|
|
|
.mask_bit = 2,
|
|
|
|
.mask_reset_inv = true,
|
|
|
|
.rst_stat_reg = GS_RST_STAT_REG_OFFSET,
|
|
|
|
.rst_stat_bit = 1,
|
|
|
|
.cnt_en_reg = GS_CLUSTER1_NONCPU_OUT,
|
|
|
|
.cnt_en_bit = 7,
|
|
|
|
.quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET |
|
|
|
|
QUIRK_HAS_PMU_CNT_EN | QUIRK_HAS_WTCLRINT_REG |
|
|
|
|
QUIRK_HAS_DBGACK_BIT,
|
|
|
|
};
|
|
|
|
|
2013-12-05 22:47:47 -07:00
|
|
|
static const struct of_device_id s3c2410_wdt_match[] = {
|
2023-12-11 09:23:27 -07:00
|
|
|
{ .compatible = "google,gs101-wdt",
|
|
|
|
.data = &drv_data_gs101_cl0 },
|
2013-12-05 22:47:47 -07:00
|
|
|
{ .compatible = "samsung,s3c2410-wdt",
|
|
|
|
.data = &drv_data_s3c2410 },
|
2017-02-24 08:11:16 -07:00
|
|
|
{ .compatible = "samsung,s3c6410-wdt",
|
|
|
|
.data = &drv_data_s3c6410 },
|
2013-12-05 22:47:47 -07:00
|
|
|
{ .compatible = "samsung,exynos5250-wdt",
|
|
|
|
.data = &drv_data_exynos5250 },
|
|
|
|
{ .compatible = "samsung,exynos5420-wdt",
|
|
|
|
.data = &drv_data_exynos5420 },
|
2014-08-27 02:47:11 -07:00
|
|
|
{ .compatible = "samsung,exynos7-wdt",
|
|
|
|
.data = &drv_data_exynos7 },
|
2021-11-21 09:56:47 -07:00
|
|
|
{ .compatible = "samsung,exynos850-wdt",
|
|
|
|
.data = &drv_data_exynos850_cl0 },
|
2022-05-20 05:17:48 -07:00
|
|
|
{ .compatible = "samsung,exynosautov9-wdt",
|
|
|
|
.data = &drv_data_exynosautov9_cl0 },
|
2013-12-05 22:47:47 -07:00
|
|
|
{},
|
2013-08-27 03:06:03 -07:00
|
|
|
};
|
2013-12-05 22:47:47 -07:00
|
|
|
MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static const struct platform_device_id s3c2410_wdt_ids[] = {
|
|
|
|
{
|
|
|
|
.name = "s3c2410-wdt",
|
|
|
|
.driver_data = (unsigned long)&drv_data_s3c2410,
|
|
|
|
},
|
|
|
|
{}
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(platform, s3c2410_wdt_ids);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
/* functions */
|
|
|
|
|
2021-11-21 09:56:45 -07:00
|
|
|
static inline unsigned long s3c2410wdt_get_freq(struct s3c2410_wdt *wdt)
|
2016-03-01 09:45:17 -07:00
|
|
|
{
|
2021-11-21 09:56:45 -07:00
|
|
|
return clk_get_rate(wdt->src_clk ? wdt->src_clk : wdt->bus_clk);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline unsigned int s3c2410wdt_max_timeout(struct s3c2410_wdt *wdt)
|
|
|
|
{
|
|
|
|
const unsigned long freq = s3c2410wdt_get_freq(wdt);
|
2016-03-01 09:45:17 -07:00
|
|
|
|
|
|
|
return S3C2410_WTCNT_MAXCNT / (freq / (S3C2410_WTCON_PRESCALE_MAX + 1)
|
|
|
|
/ S3C2410_WTCON_MAXDIV);
|
|
|
|
}
|
|
|
|
|
2021-11-21 09:56:41 -07:00
|
|
|
static int s3c2410wdt_disable_wdt_reset(struct s3c2410_wdt *wdt, bool mask)
|
2013-12-05 22:47:47 -07:00
|
|
|
{
|
2021-11-21 09:56:41 -07:00
|
|
|
const u32 mask_val = BIT(wdt->drv_data->mask_bit);
|
|
|
|
const u32 val = mask ? mask_val : 0;
|
2013-12-05 22:47:47 -07:00
|
|
|
int ret;
|
|
|
|
|
2021-11-21 09:56:41 -07:00
|
|
|
ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->disable_reg,
|
|
|
|
mask_val, val);
|
|
|
|
if (ret < 0)
|
|
|
|
dev_err(wdt->dev, "failed to update reg(%d)\n", ret);
|
2013-12-05 22:47:47 -07:00
|
|
|
|
2021-11-21 09:56:41 -07:00
|
|
|
return ret;
|
|
|
|
}
|
2013-12-05 22:47:47 -07:00
|
|
|
|
2021-11-21 09:56:41 -07:00
|
|
|
static int s3c2410wdt_mask_wdt_reset(struct s3c2410_wdt *wdt, bool mask)
|
|
|
|
{
|
|
|
|
const u32 mask_val = BIT(wdt->drv_data->mask_bit);
|
2021-11-21 09:56:42 -07:00
|
|
|
const bool val_inv = wdt->drv_data->mask_reset_inv;
|
|
|
|
const u32 val = (mask ^ val_inv) ? mask_val : 0;
|
2021-11-21 09:56:41 -07:00
|
|
|
int ret;
|
2013-12-05 22:47:47 -07:00
|
|
|
|
2021-11-21 09:56:41 -07:00
|
|
|
ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->mask_reset_reg,
|
|
|
|
mask_val, val);
|
2013-12-05 22:47:47 -07:00
|
|
|
if (ret < 0)
|
|
|
|
dev_err(wdt->dev, "failed to update reg(%d)\n", ret);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2021-11-21 09:56:43 -07:00
|
|
|
static int s3c2410wdt_enable_counter(struct s3c2410_wdt *wdt, bool en)
|
|
|
|
{
|
|
|
|
const u32 mask_val = BIT(wdt->drv_data->cnt_en_bit);
|
|
|
|
const u32 val = en ? mask_val : 0;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->cnt_en_reg,
|
|
|
|
mask_val, val);
|
|
|
|
if (ret < 0)
|
|
|
|
dev_err(wdt->dev, "failed to update reg(%d)\n", ret);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2021-11-23 16:26:13 -07:00
|
|
|
static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en)
|
2021-11-21 09:56:41 -07:00
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (wdt->drv_data->quirks & QUIRK_HAS_PMU_AUTO_DISABLE) {
|
2021-11-23 16:26:13 -07:00
|
|
|
ret = s3c2410wdt_disable_wdt_reset(wdt, !en);
|
2021-11-21 09:56:41 -07:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2021-11-23 16:26:13 -07:00
|
|
|
if (wdt->drv_data->quirks & QUIRK_HAS_PMU_MASK_RESET) {
|
|
|
|
ret = s3c2410wdt_mask_wdt_reset(wdt, !en);
|
2021-11-21 09:56:41 -07:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2021-11-21 09:56:43 -07:00
|
|
|
if (wdt->drv_data->quirks & QUIRK_HAS_PMU_CNT_EN) {
|
2021-11-23 16:26:13 -07:00
|
|
|
ret = s3c2410wdt_enable_counter(wdt, en);
|
2021-11-21 09:56:43 -07:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2021-11-21 09:56:41 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2023-12-11 09:23:25 -07:00
|
|
|
/* Disable watchdog outputs if CPU is in debug mode */
|
|
|
|
static void s3c2410wdt_mask_dbgack(struct s3c2410_wdt *wdt)
|
|
|
|
{
|
|
|
|
unsigned long wtcon;
|
|
|
|
|
|
|
|
if (!(wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT))
|
|
|
|
return;
|
|
|
|
|
|
|
|
wtcon = readl(wdt->reg_base + S3C2410_WTCON);
|
|
|
|
wtcon |= S3C2410_WTCON_DBGACK_MASK;
|
|
|
|
writel(wtcon, wdt->reg_base + S3C2410_WTCON);
|
|
|
|
}
|
|
|
|
|
2011-09-26 06:40:14 -07:00
|
|
|
static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
|
2005-04-16 15:20:36 -07:00
|
|
|
{
|
2013-08-27 03:06:03 -07:00
|
|
|
struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
|
2023-07-05 02:09:51 -07:00
|
|
|
unsigned long flags;
|
2013-08-27 03:06:03 -07:00
|
|
|
|
2023-07-05 02:09:51 -07:00
|
|
|
spin_lock_irqsave(&wdt->lock, flags);
|
2013-08-27 03:06:03 -07:00
|
|
|
writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
|
2023-07-05 02:09:51 -07:00
|
|
|
spin_unlock_irqrestore(&wdt->lock, flags);
|
2011-09-26 06:40:14 -07:00
|
|
|
|
|
|
|
return 0;
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
2013-08-27 03:06:03 -07:00
|
|
|
static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt)
|
2008-08-04 09:54:46 -07:00
|
|
|
{
|
|
|
|
unsigned long wtcon;
|
|
|
|
|
2013-08-27 03:06:03 -07:00
|
|
|
wtcon = readl(wdt->reg_base + S3C2410_WTCON);
|
2008-08-04 09:54:46 -07:00
|
|
|
wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
|
2013-08-27 03:06:03 -07:00
|
|
|
writel(wtcon, wdt->reg_base + S3C2410_WTCON);
|
2008-08-04 09:54:46 -07:00
|
|
|
}
|
|
|
|
|
2011-09-26 06:40:14 -07:00
|
|
|
static int s3c2410wdt_stop(struct watchdog_device *wdd)
|
2008-08-04 09:54:46 -07:00
|
|
|
{
|
2013-08-27 03:06:03 -07:00
|
|
|
struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
|
2023-07-05 02:09:51 -07:00
|
|
|
unsigned long flags;
|
2013-08-27 03:06:03 -07:00
|
|
|
|
2023-07-05 02:09:51 -07:00
|
|
|
spin_lock_irqsave(&wdt->lock, flags);
|
2013-08-27 03:06:03 -07:00
|
|
|
__s3c2410wdt_stop(wdt);
|
2023-07-05 02:09:51 -07:00
|
|
|
spin_unlock_irqrestore(&wdt->lock, flags);
|
2011-09-26 06:40:14 -07:00
|
|
|
|
|
|
|
return 0;
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
2011-09-26 06:40:14 -07:00
|
|
|
static int s3c2410wdt_start(struct watchdog_device *wdd)
|
2005-04-16 15:20:36 -07:00
|
|
|
{
|
|
|
|
unsigned long wtcon;
|
2013-08-27 03:06:03 -07:00
|
|
|
struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
|
2023-07-05 02:09:51 -07:00
|
|
|
unsigned long flags;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2023-07-05 02:09:51 -07:00
|
|
|
spin_lock_irqsave(&wdt->lock, flags);
|
2008-08-04 09:54:46 -07:00
|
|
|
|
2013-08-27 03:06:03 -07:00
|
|
|
__s3c2410wdt_stop(wdt);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2013-08-27 03:06:03 -07:00
|
|
|
wtcon = readl(wdt->reg_base + S3C2410_WTCON);
|
2005-04-16 15:20:36 -07:00
|
|
|
wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128;
|
|
|
|
|
|
|
|
if (soft_noboot) {
|
|
|
|
wtcon |= S3C2410_WTCON_INTEN;
|
|
|
|
wtcon &= ~S3C2410_WTCON_RSTEN;
|
|
|
|
} else {
|
|
|
|
wtcon &= ~S3C2410_WTCON_INTEN;
|
|
|
|
wtcon |= S3C2410_WTCON_RSTEN;
|
|
|
|
}
|
|
|
|
|
2017-02-24 14:07:40 -07:00
|
|
|
dev_dbg(wdt->dev, "Starting watchdog: count=0x%08x, wtcon=%08lx\n",
|
|
|
|
wdt->count, wtcon);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2013-08-27 03:06:03 -07:00
|
|
|
writel(wdt->count, wdt->reg_base + S3C2410_WTDAT);
|
|
|
|
writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
|
|
|
|
writel(wtcon, wdt->reg_base + S3C2410_WTCON);
|
2023-07-05 02:09:51 -07:00
|
|
|
spin_unlock_irqrestore(&wdt->lock, flags);
|
2011-09-26 06:40:14 -07:00
|
|
|
|
|
|
|
return 0;
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
2017-03-13 12:07:26 -07:00
|
|
|
static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd,
|
|
|
|
unsigned int timeout)
|
2005-04-16 15:20:36 -07:00
|
|
|
{
|
2013-08-27 03:06:03 -07:00
|
|
|
struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
|
2021-11-21 09:56:45 -07:00
|
|
|
unsigned long freq = s3c2410wdt_get_freq(wdt);
|
2005-04-16 15:20:36 -07:00
|
|
|
unsigned int count;
|
|
|
|
unsigned int divisor = 1;
|
|
|
|
unsigned long wtcon;
|
|
|
|
|
|
|
|
if (timeout < 1)
|
|
|
|
return -EINVAL;
|
|
|
|
|
watchdog: s3c2410_wdt: Handle rounding a little better for timeout
The existing watchdog timeout worked OK but didn't deal with
rounding in an ideal way when dividing out all of its clocks.
Specifically if you had a timeout of 32 seconds and an input clock of
66666666, you'd end up setting a timeout of 31.9998 seconds and
reporting a timeout of 31 seconds.
Specifically DBG printouts showed:
s3c2410wdt_set_heartbeat: count=16666656, timeout=32, freq=520833
s3c2410wdt_set_heartbeat: timeout=32, divisor=255, count=16666656 (0000ff4f)
and the final timeout reported to the user was:
((count / divisor) * divisor) / freq
(0xff4f * 255) / 520833 = 31 (truncated from 31.9998)
the technically "correct" value is:
(0xff4f * 255) / (66666666.0 / 128) = 31.9998
By using "DIV_ROUND_UP" we can be a little more correct.
s3c2410wdt_set_heartbeat: count=16666688, timeout=32, freq=520834
s3c2410wdt_set_heartbeat: timeout=32, divisor=255, count=16666688 (0000ff50)
and the final timeout reported to the user:
(0xff50 * 255) / 520834 = 32
the technically "correct" value is:
(0xff50 * 255) / (66666666.0 / 128) = 32.0003
We'll use a DIV_ROUND_UP to solve this, generally erroring on the side
of reporting shorter values to the user and setting the watchdog to
slightly longer than requested:
* Round input frequency up to assume watchdog is counting faster.
* Round divisions by divisor up to give us extra time.
At the same time we can avoid a for loop by just doing the right math.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
2013-11-26 17:57:19 -07:00
|
|
|
freq = DIV_ROUND_UP(freq, 128);
|
2005-04-16 15:20:36 -07:00
|
|
|
count = timeout * freq;
|
|
|
|
|
2017-02-24 14:07:40 -07:00
|
|
|
dev_dbg(wdt->dev, "Heartbeat: count=%d, timeout=%d, freq=%lu\n",
|
|
|
|
count, timeout, freq);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
/* if the count is bigger than the watchdog register,
|
|
|
|
then work out what we need to do (and if) we can
|
|
|
|
actually make this value
|
|
|
|
*/
|
|
|
|
|
|
|
|
if (count >= 0x10000) {
|
watchdog: s3c2410_wdt: Handle rounding a little better for timeout
The existing watchdog timeout worked OK but didn't deal with
rounding in an ideal way when dividing out all of its clocks.
Specifically if you had a timeout of 32 seconds and an input clock of
66666666, you'd end up setting a timeout of 31.9998 seconds and
reporting a timeout of 31 seconds.
Specifically DBG printouts showed:
s3c2410wdt_set_heartbeat: count=16666656, timeout=32, freq=520833
s3c2410wdt_set_heartbeat: timeout=32, divisor=255, count=16666656 (0000ff4f)
and the final timeout reported to the user was:
((count / divisor) * divisor) / freq
(0xff4f * 255) / 520833 = 31 (truncated from 31.9998)
the technically "correct" value is:
(0xff4f * 255) / (66666666.0 / 128) = 31.9998
By using "DIV_ROUND_UP" we can be a little more correct.
s3c2410wdt_set_heartbeat: count=16666688, timeout=32, freq=520834
s3c2410wdt_set_heartbeat: timeout=32, divisor=255, count=16666688 (0000ff50)
and the final timeout reported to the user:
(0xff50 * 255) / 520834 = 32
the technically "correct" value is:
(0xff50 * 255) / (66666666.0 / 128) = 32.0003
We'll use a DIV_ROUND_UP to solve this, generally erroring on the side
of reporting shorter values to the user and setting the watchdog to
slightly longer than requested:
* Round input frequency up to assume watchdog is counting faster.
* Round divisions by divisor up to give us extra time.
At the same time we can avoid a for loop by just doing the right math.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
2013-11-26 17:57:19 -07:00
|
|
|
divisor = DIV_ROUND_UP(count, 0xffff);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
watchdog: s3c2410_wdt: Handle rounding a little better for timeout
The existing watchdog timeout worked OK but didn't deal with
rounding in an ideal way when dividing out all of its clocks.
Specifically if you had a timeout of 32 seconds and an input clock of
66666666, you'd end up setting a timeout of 31.9998 seconds and
reporting a timeout of 31 seconds.
Specifically DBG printouts showed:
s3c2410wdt_set_heartbeat: count=16666656, timeout=32, freq=520833
s3c2410wdt_set_heartbeat: timeout=32, divisor=255, count=16666656 (0000ff4f)
and the final timeout reported to the user was:
((count / divisor) * divisor) / freq
(0xff4f * 255) / 520833 = 31 (truncated from 31.9998)
the technically "correct" value is:
(0xff4f * 255) / (66666666.0 / 128) = 31.9998
By using "DIV_ROUND_UP" we can be a little more correct.
s3c2410wdt_set_heartbeat: count=16666688, timeout=32, freq=520834
s3c2410wdt_set_heartbeat: timeout=32, divisor=255, count=16666688 (0000ff50)
and the final timeout reported to the user:
(0xff50 * 255) / 520834 = 32
the technically "correct" value is:
(0xff50 * 255) / (66666666.0 / 128) = 32.0003
We'll use a DIV_ROUND_UP to solve this, generally erroring on the side
of reporting shorter values to the user and setting the watchdog to
slightly longer than requested:
* Round input frequency up to assume watchdog is counting faster.
* Round divisions by divisor up to give us extra time.
At the same time we can avoid a for loop by just doing the right math.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
2013-11-26 17:57:19 -07:00
|
|
|
if (divisor > 0x100) {
|
2013-08-27 03:06:03 -07:00
|
|
|
dev_err(wdt->dev, "timeout %d too big\n", timeout);
|
2005-04-16 15:20:36 -07:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-02-24 14:07:40 -07:00
|
|
|
dev_dbg(wdt->dev, "Heartbeat: timeout=%d, divisor=%d, count=%d (%08x)\n",
|
|
|
|
timeout, divisor, count, DIV_ROUND_UP(count, divisor));
|
2005-04-16 15:20:36 -07:00
|
|
|
|
watchdog: s3c2410_wdt: Handle rounding a little better for timeout
The existing watchdog timeout worked OK but didn't deal with
rounding in an ideal way when dividing out all of its clocks.
Specifically if you had a timeout of 32 seconds and an input clock of
66666666, you'd end up setting a timeout of 31.9998 seconds and
reporting a timeout of 31 seconds.
Specifically DBG printouts showed:
s3c2410wdt_set_heartbeat: count=16666656, timeout=32, freq=520833
s3c2410wdt_set_heartbeat: timeout=32, divisor=255, count=16666656 (0000ff4f)
and the final timeout reported to the user was:
((count / divisor) * divisor) / freq
(0xff4f * 255) / 520833 = 31 (truncated from 31.9998)
the technically "correct" value is:
(0xff4f * 255) / (66666666.0 / 128) = 31.9998
By using "DIV_ROUND_UP" we can be a little more correct.
s3c2410wdt_set_heartbeat: count=16666688, timeout=32, freq=520834
s3c2410wdt_set_heartbeat: timeout=32, divisor=255, count=16666688 (0000ff50)
and the final timeout reported to the user:
(0xff50 * 255) / 520834 = 32
the technically "correct" value is:
(0xff50 * 255) / (66666666.0 / 128) = 32.0003
We'll use a DIV_ROUND_UP to solve this, generally erroring on the side
of reporting shorter values to the user and setting the watchdog to
slightly longer than requested:
* Round input frequency up to assume watchdog is counting faster.
* Round divisions by divisor up to give us extra time.
At the same time we can avoid a for loop by just doing the right math.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
2013-11-26 17:57:19 -07:00
|
|
|
count = DIV_ROUND_UP(count, divisor);
|
2013-08-27 03:06:03 -07:00
|
|
|
wdt->count = count;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
/* update the pre-scaler */
|
2013-08-27 03:06:03 -07:00
|
|
|
wtcon = readl(wdt->reg_base + S3C2410_WTCON);
|
2005-04-16 15:20:36 -07:00
|
|
|
wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
|
|
|
|
wtcon |= S3C2410_WTCON_PRESCALE(divisor-1);
|
|
|
|
|
2013-08-27 03:06:03 -07:00
|
|
|
writel(count, wdt->reg_base + S3C2410_WTDAT);
|
|
|
|
writel(wtcon, wdt->reg_base + S3C2410_WTCON);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2012-05-11 03:00:27 -07:00
|
|
|
wdd->timeout = (count * divisor) / freq;
|
2012-02-29 12:20:58 -07:00
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-02-26 18:32:49 -07:00
|
|
|
static int s3c2410wdt_restart(struct watchdog_device *wdd, unsigned long action,
|
|
|
|
void *data)
|
2015-11-16 10:28:10 -07:00
|
|
|
{
|
|
|
|
struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
|
|
|
|
void __iomem *wdt_base = wdt->reg_base;
|
|
|
|
|
|
|
|
/* disable watchdog, to be safe */
|
|
|
|
writel(0, wdt_base + S3C2410_WTCON);
|
|
|
|
|
|
|
|
/* put initial values into count and data */
|
|
|
|
writel(0x80, wdt_base + S3C2410_WTCNT);
|
|
|
|
writel(0x80, wdt_base + S3C2410_WTDAT);
|
|
|
|
|
|
|
|
/* set the watchdog to go and reset... */
|
|
|
|
writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 |
|
|
|
|
S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20),
|
|
|
|
wdt_base + S3C2410_WTCON);
|
|
|
|
|
|
|
|
/* wait for reset to assert... */
|
|
|
|
mdelay(500);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-04-14 13:20:07 -07:00
|
|
|
#define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2008-08-04 09:54:46 -07:00
|
|
|
static const struct watchdog_info s3c2410_wdt_ident = {
|
2005-04-16 15:20:36 -07:00
|
|
|
.options = OPTIONS,
|
|
|
|
.firmware_version = 0,
|
|
|
|
.identity = "S3C2410 Watchdog",
|
|
|
|
};
|
|
|
|
|
2017-01-28 00:41:17 -07:00
|
|
|
static const struct watchdog_ops s3c2410wdt_ops = {
|
2011-09-26 06:40:14 -07:00
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.start = s3c2410wdt_start,
|
|
|
|
.stop = s3c2410wdt_stop,
|
|
|
|
.ping = s3c2410wdt_keepalive,
|
|
|
|
.set_timeout = s3c2410wdt_set_heartbeat,
|
2015-11-16 10:28:10 -07:00
|
|
|
.restart = s3c2410wdt_restart,
|
2005-04-16 15:20:36 -07:00
|
|
|
};
|
|
|
|
|
2017-03-13 12:07:24 -07:00
|
|
|
static const struct watchdog_device s3c2410_wdd = {
|
2011-09-26 06:40:14 -07:00
|
|
|
.info = &s3c2410_wdt_ident,
|
|
|
|
.ops = &s3c2410wdt_ops,
|
2017-02-24 08:11:15 -07:00
|
|
|
.timeout = S3C2410_WATCHDOG_DEFAULT_TIME,
|
2005-04-16 15:20:36 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
/* interrupt handler code */
|
|
|
|
|
IRQ: Maintain regs pointer globally rather than passing to IRQ handlers
Maintain a per-CPU global "struct pt_regs *" variable which can be used instead
of passing regs around manually through all ~1800 interrupt handlers in the
Linux kernel.
The regs pointer is used in few places, but it potentially costs both stack
space and code to pass it around. On the FRV arch, removing the regs parameter
from all the genirq function results in a 20% speed up of the IRQ exit path
(ie: from leaving timer_interrupt() to leaving do_IRQ()).
Where appropriate, an arch may override the generic storage facility and do
something different with the variable. On FRV, for instance, the address is
maintained in GR28 at all times inside the kernel as part of general exception
handling.
Having looked over the code, it appears that the parameter may be handed down
through up to twenty or so layers of functions. Consider a USB character
device attached to a USB hub, attached to a USB controller that posts its
interrupts through a cascaded auxiliary interrupt controller. A character
device driver may want to pass regs to the sysrq handler through the input
layer which adds another few layers of parameter passing.
I've build this code with allyesconfig for x86_64 and i386. I've runtested the
main part of the code on FRV and i386, though I can't test most of the drivers.
I've also done partial conversion for powerpc and MIPS - these at least compile
with minimal configurations.
This will affect all archs. Mostly the changes should be relatively easy.
Take do_IRQ(), store the regs pointer at the beginning, saving the old one:
struct pt_regs *old_regs = set_irq_regs(regs);
And put the old one back at the end:
set_irq_regs(old_regs);
Don't pass regs through to generic_handle_irq() or __do_IRQ().
In timer_interrupt(), this sort of change will be necessary:
- update_process_times(user_mode(regs));
- profile_tick(CPU_PROFILING, regs);
+ update_process_times(user_mode(get_irq_regs()));
+ profile_tick(CPU_PROFILING);
I'd like to move update_process_times()'s use of get_irq_regs() into itself,
except that i386, alone of the archs, uses something other than user_mode().
Some notes on the interrupt handling in the drivers:
(*) input_dev() is now gone entirely. The regs pointer is no longer stored in
the input_dev struct.
(*) finish_unlinks() in drivers/usb/host/ohci-q.c needs checking. It does
something different depending on whether it's been supplied with a regs
pointer or not.
(*) Various IRQ handler function pointers have been moved to type
irq_handler_t.
Signed-Off-By: David Howells <dhowells@redhat.com>
(cherry picked from 1b16e7ac850969f38b375e511e3fa2f474a33867 commit)
2006-10-05 06:55:46 -07:00
|
|
|
static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
|
2005-04-16 15:20:36 -07:00
|
|
|
{
|
2013-08-27 03:06:03 -07:00
|
|
|
struct s3c2410_wdt *wdt = platform_get_drvdata(param);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2013-08-27 03:06:03 -07:00
|
|
|
dev_info(wdt->dev, "watchdog timer expired (irq)\n");
|
|
|
|
|
|
|
|
s3c2410wdt_keepalive(&wdt->wdt_device);
|
2017-02-24 08:11:16 -07:00
|
|
|
|
|
|
|
if (wdt->drv_data->quirks & QUIRK_HAS_WTCLRINT_REG)
|
|
|
|
writel(0x1, wdt->reg_base + S3C2410_WTCLRINT);
|
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
2009-10-29 17:30:25 -07:00
|
|
|
|
2013-12-06 14:08:07 -07:00
|
|
|
static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt *wdt)
|
|
|
|
{
|
|
|
|
unsigned int rst_stat;
|
|
|
|
int ret;
|
|
|
|
|
2021-11-23 16:26:13 -07:00
|
|
|
if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_RST_STAT))
|
2013-12-06 14:08:07 -07:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
ret = regmap_read(wdt->pmureg, wdt->drv_data->rst_stat_reg, &rst_stat);
|
|
|
|
if (ret)
|
|
|
|
dev_warn(wdt->dev, "Couldn't get RST_STAT register\n");
|
|
|
|
else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit))
|
|
|
|
return WDIOF_CARDRESET;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2023-03-06 23:56:02 -07:00
|
|
|
static inline int
|
|
|
|
s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
|
2013-12-05 22:47:47 -07:00
|
|
|
{
|
2017-03-13 12:07:25 -07:00
|
|
|
const struct s3c2410_wdt_variant *variant;
|
2021-11-21 09:56:47 -07:00
|
|
|
struct device *dev = &pdev->dev;
|
2017-03-13 12:07:25 -07:00
|
|
|
|
2021-11-21 09:56:47 -07:00
|
|
|
variant = of_device_get_match_data(dev);
|
2017-03-13 12:07:25 -07:00
|
|
|
if (!variant) {
|
|
|
|
/* Device matched by platform_device_id */
|
|
|
|
variant = (struct s3c2410_wdt_variant *)
|
|
|
|
platform_get_device_id(pdev)->driver_data;
|
2013-12-05 22:47:47 -07:00
|
|
|
}
|
2017-03-13 12:07:25 -07:00
|
|
|
|
2021-11-21 09:56:47 -07:00
|
|
|
#ifdef CONFIG_OF
|
2022-05-20 05:17:48 -07:00
|
|
|
/* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */
|
|
|
|
if (variant == &drv_data_exynos850_cl0 ||
|
2023-12-11 09:23:27 -07:00
|
|
|
variant == &drv_data_exynosautov9_cl0 ||
|
|
|
|
variant == &drv_data_gs101_cl0) {
|
2021-11-21 09:56:47 -07:00
|
|
|
u32 index;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
err = of_property_read_u32(dev->of_node,
|
|
|
|
"samsung,cluster-index", &index);
|
2023-03-06 23:56:03 -07:00
|
|
|
if (err)
|
|
|
|
return dev_err_probe(dev, -EINVAL, "failed to get cluster index\n");
|
2021-11-21 09:56:47 -07:00
|
|
|
|
|
|
|
switch (index) {
|
|
|
|
case 0:
|
2023-03-06 23:56:02 -07:00
|
|
|
break;
|
2021-11-21 09:56:47 -07:00
|
|
|
case 1:
|
2023-12-11 09:23:27 -07:00
|
|
|
if (variant == &drv_data_exynos850_cl0)
|
|
|
|
variant = &drv_data_exynos850_cl1;
|
|
|
|
else if (variant == &drv_data_exynosautov9_cl0)
|
|
|
|
variant = &drv_data_exynosautov9_cl1;
|
|
|
|
else if (variant == &drv_data_gs101_cl0)
|
|
|
|
variant = &drv_data_gs101_cl1;
|
2023-03-06 23:56:02 -07:00
|
|
|
break;
|
2021-11-21 09:56:47 -07:00
|
|
|
default:
|
2023-03-06 23:56:03 -07:00
|
|
|
return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index);
|
2021-11-21 09:56:47 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2023-03-06 23:56:02 -07:00
|
|
|
wdt->drv_data = variant;
|
|
|
|
return 0;
|
2013-12-05 22:47:47 -07:00
|
|
|
}
|
|
|
|
|
2023-03-04 09:56:53 -07:00
|
|
|
static void s3c2410wdt_wdt_disable_action(void *data)
|
|
|
|
{
|
|
|
|
s3c2410wdt_enable(data, false);
|
|
|
|
}
|
|
|
|
|
2012-11-19 11:21:41 -07:00
|
|
|
static int s3c2410wdt_probe(struct platform_device *pdev)
|
2005-04-16 15:20:36 -07:00
|
|
|
{
|
2017-03-13 12:07:26 -07:00
|
|
|
struct device *dev = &pdev->dev;
|
2013-08-27 03:06:03 -07:00
|
|
|
struct s3c2410_wdt *wdt;
|
2007-06-14 04:08:54 -07:00
|
|
|
unsigned int wtcon;
|
2021-12-16 14:47:47 -07:00
|
|
|
int wdt_irq;
|
2005-04-16 15:20:36 -07:00
|
|
|
int ret;
|
|
|
|
|
2013-08-27 03:06:03 -07:00
|
|
|
wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
|
|
|
|
if (!wdt)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2017-03-13 12:07:26 -07:00
|
|
|
wdt->dev = dev;
|
2013-08-27 03:06:03 -07:00
|
|
|
spin_lock_init(&wdt->lock);
|
|
|
|
wdt->wdt_device = s3c2410_wdd;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2023-03-06 23:56:02 -07:00
|
|
|
ret = s3c2410_get_wdt_drv_data(pdev, wdt);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2021-11-21 09:56:47 -07:00
|
|
|
|
2013-12-06 14:08:07 -07:00
|
|
|
if (wdt->drv_data->quirks & QUIRKS_HAVE_PMUREG) {
|
2024-02-20 15:06:13 -07:00
|
|
|
wdt->pmureg = exynos_get_pmu_regmap_by_phandle(dev->of_node,
|
|
|
|
"samsung,syscon-phandle");
|
2023-03-06 23:56:03 -07:00
|
|
|
if (IS_ERR(wdt->pmureg))
|
|
|
|
return dev_err_probe(dev, PTR_ERR(wdt->pmureg),
|
2024-02-20 15:06:13 -07:00
|
|
|
"PMU regmap lookup failed.\n");
|
2013-12-05 22:47:47 -07:00
|
|
|
}
|
|
|
|
|
2021-12-16 14:47:47 -07:00
|
|
|
wdt_irq = platform_get_irq(pdev, 0);
|
|
|
|
if (wdt_irq < 0)
|
|
|
|
return wdt_irq;
|
2012-01-12 22:14:23 -07:00
|
|
|
|
|
|
|
/* get the memory region for the watchdog timer */
|
watchdog: Convert to use devm_platform_ioremap_resource
Use devm_platform_ioremap_resource to reduce source code size,
improve readability, and reduce the likelyhood of bugs.
The conversion was done automatically with coccinelle using the
following semantic patch.
@r@
identifier res, pdev;
expression a;
expression index;
expression e;
@@
<+...
- res = platform_get_resource(pdev, IORESOURCE_MEM, index);
- a = devm_ioremap_resource(e, res);
+ a = devm_platform_ioremap_resource(pdev, index);
...+>
@depends on r@
identifier r.res;
@@
- struct resource *res;
... when != res
@@
identifier res, pdev;
expression index;
expression a;
@@
- struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, index);
- a = devm_ioremap_resource(&pdev->dev, res);
+ a = devm_platform_ioremap_resource(pdev, index);
Cc: Joel Stanley <joel@jms.id.au>
Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Baruch Siach <baruch@tkos.co.il>
Cc: Keguang Zhang <keguang.zhang@gmail.com>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Kevin Hilman <khilman@baylibre.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Avi Fishman <avifishman70@gmail.com>
Cc: Nancy Yuen <yuenn@google.com>
Cc: Brendan Higgins <brendanhiggins@google.com>
Cc: Wan ZongShun <mcuos.com@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Sylvain Lemieux <slemieux.tyco@gmail.com>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Barry Song <baohua@kernel.org>
Cc: Orson Zhai <orsonzhai@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Maxime Ripard <maxime.ripard@bootlin.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Marc Gonzalez <marc.w.gonzalez@free.fr>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Tested-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Michal Simek <michal.simek@xilinx.com> (cadence/xilinx wdts)
Acked-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
2019-04-02 12:01:53 -07:00
|
|
|
wdt->reg_base = devm_platform_ioremap_resource(pdev, 0);
|
2021-11-21 09:56:46 -07:00
|
|
|
if (IS_ERR(wdt->reg_base))
|
|
|
|
return PTR_ERR(wdt->reg_base);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2023-03-04 09:56:52 -07:00
|
|
|
wdt->bus_clk = devm_clk_get_enabled(dev, "watchdog");
|
|
|
|
if (IS_ERR(wdt->bus_clk))
|
|
|
|
return dev_err_probe(dev, PTR_ERR(wdt->bus_clk), "failed to get bus clock\n");
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2021-11-21 09:56:45 -07:00
|
|
|
/*
|
|
|
|
* "watchdog_src" clock is optional; if it's not present -- just skip it
|
|
|
|
* and use "watchdog" clock as both bus and source clock.
|
|
|
|
*/
|
2023-03-04 09:56:52 -07:00
|
|
|
wdt->src_clk = devm_clk_get_optional_enabled(dev, "watchdog_src");
|
|
|
|
if (IS_ERR(wdt->src_clk))
|
|
|
|
return dev_err_probe(dev, PTR_ERR(wdt->src_clk), "failed to get source clock\n");
|
2021-11-21 09:56:45 -07:00
|
|
|
|
2016-03-01 09:45:17 -07:00
|
|
|
wdt->wdt_device.min_timeout = 1;
|
2021-11-21 09:56:45 -07:00
|
|
|
wdt->wdt_device.max_timeout = s3c2410wdt_max_timeout(wdt);
|
2016-03-01 09:45:17 -07:00
|
|
|
|
2013-08-27 03:06:03 -07:00
|
|
|
watchdog_set_drvdata(&wdt->wdt_device, wdt);
|
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
/* see if we can actually set the requested timer margin, and if
|
|
|
|
* not, try the default value */
|
|
|
|
|
2017-03-13 12:07:26 -07:00
|
|
|
watchdog_init_timeout(&wdt->wdt_device, tmr_margin, dev);
|
2013-08-27 03:06:03 -07:00
|
|
|
ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
|
|
|
|
wdt->wdt_device.timeout);
|
|
|
|
if (ret) {
|
2021-11-21 09:56:38 -07:00
|
|
|
ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
|
|
|
|
S3C2410_WATCHDOG_DEFAULT_TIME);
|
2023-03-06 23:56:03 -07:00
|
|
|
if (ret == 0)
|
2021-11-21 09:56:38 -07:00
|
|
|
dev_warn(dev, "tmr_margin value out of range, default %d used\n",
|
2017-03-13 12:07:26 -07:00
|
|
|
S3C2410_WATCHDOG_DEFAULT_TIME);
|
2023-03-06 23:56:03 -07:00
|
|
|
else
|
|
|
|
return dev_err_probe(dev, ret, "failed to use default timeout\n");
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
2021-12-16 14:47:47 -07:00
|
|
|
ret = devm_request_irq(dev, wdt_irq, s3c2410wdt_irq, 0,
|
|
|
|
pdev->name, pdev);
|
2023-03-06 23:56:03 -07:00
|
|
|
if (ret != 0)
|
|
|
|
return dev_err_probe(dev, ret, "failed to install irq (%d)\n", ret);
|
2012-01-12 22:14:23 -07:00
|
|
|
|
2013-08-27 03:06:03 -07:00
|
|
|
watchdog_set_nowayout(&wdt->wdt_device, nowayout);
|
2015-11-16 10:28:10 -07:00
|
|
|
watchdog_set_restart_priority(&wdt->wdt_device, 128);
|
2011-11-29 08:24:16 -07:00
|
|
|
|
2013-12-06 14:08:07 -07:00
|
|
|
wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt);
|
2017-03-13 12:07:26 -07:00
|
|
|
wdt->wdt_device.parent = dev;
|
2013-12-06 14:08:07 -07:00
|
|
|
|
2023-12-11 09:23:25 -07:00
|
|
|
s3c2410wdt_mask_dbgack(wdt);
|
|
|
|
|
2021-11-21 09:56:39 -07:00
|
|
|
/*
|
|
|
|
* If "tmr_atboot" param is non-zero, start the watchdog right now. Also
|
|
|
|
* set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog.
|
|
|
|
*
|
|
|
|
* If we're not enabling the watchdog, then ensure it is disabled if it
|
|
|
|
* has been left running from the bootloader or other source.
|
|
|
|
*/
|
|
|
|
if (tmr_atboot) {
|
|
|
|
dev_info(dev, "starting watchdog timer\n");
|
|
|
|
s3c2410wdt_start(&wdt->wdt_device);
|
|
|
|
set_bit(WDOG_HW_RUNNING, &wdt->wdt_device.status);
|
|
|
|
} else {
|
|
|
|
s3c2410wdt_stop(&wdt->wdt_device);
|
|
|
|
}
|
|
|
|
|
2023-03-04 09:56:53 -07:00
|
|
|
ret = devm_watchdog_register_device(dev, &wdt->wdt_device);
|
2019-05-18 14:27:50 -07:00
|
|
|
if (ret)
|
2023-03-04 09:56:52 -07:00
|
|
|
return ret;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2021-11-23 16:26:13 -07:00
|
|
|
ret = s3c2410wdt_enable(wdt, true);
|
2013-12-05 22:47:47 -07:00
|
|
|
if (ret < 0)
|
2023-03-04 09:56:53 -07:00
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = devm_add_action_or_reset(dev, s3c2410wdt_wdt_disable_action, wdt);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2013-12-05 22:47:47 -07:00
|
|
|
|
2013-08-27 03:06:03 -07:00
|
|
|
platform_set_drvdata(pdev, wdt);
|
|
|
|
|
2007-06-14 04:08:54 -07:00
|
|
|
/* print out a statement of readiness */
|
|
|
|
|
2013-08-27 03:06:03 -07:00
|
|
|
wtcon = readl(wdt->reg_base + S3C2410_WTCON);
|
2007-06-14 04:08:54 -07:00
|
|
|
|
2007-06-14 04:08:55 -07:00
|
|
|
dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n",
|
2007-06-14 04:08:54 -07:00
|
|
|
(wtcon & S3C2410_WTCON_ENABLE) ? "" : "in",
|
2011-11-16 01:46:13 -07:00
|
|
|
(wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis",
|
|
|
|
(wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis");
|
2008-08-04 09:54:46 -07:00
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2005-11-09 15:32:44 -07:00
|
|
|
static void s3c2410wdt_shutdown(struct platform_device *dev)
|
2005-08-17 00:04:52 -07:00
|
|
|
{
|
2013-08-27 03:06:03 -07:00
|
|
|
struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
|
|
|
|
|
2021-11-23 16:26:13 -07:00
|
|
|
s3c2410wdt_enable(wdt, false);
|
2013-08-27 03:06:03 -07:00
|
|
|
s3c2410wdt_stop(&wdt->wdt_device);
|
2005-08-17 00:04:52 -07:00
|
|
|
}
|
|
|
|
|
2013-03-13 18:31:21 -07:00
|
|
|
static int s3c2410wdt_suspend(struct device *dev)
|
2005-08-17 00:03:23 -07:00
|
|
|
{
|
2013-12-05 22:47:47 -07:00
|
|
|
int ret;
|
2013-08-27 03:06:03 -07:00
|
|
|
struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
|
|
|
|
|
2005-10-28 09:52:56 -07:00
|
|
|
/* Save watchdog state, and turn it off. */
|
2013-08-27 03:06:03 -07:00
|
|
|
wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON);
|
|
|
|
wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT);
|
2005-08-17 00:03:23 -07:00
|
|
|
|
2021-11-23 16:26:13 -07:00
|
|
|
ret = s3c2410wdt_enable(wdt, false);
|
2013-12-05 22:47:47 -07:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2005-10-28 09:52:56 -07:00
|
|
|
/* Note that WTCNT doesn't need to be saved. */
|
2013-08-27 03:06:03 -07:00
|
|
|
s3c2410wdt_stop(&wdt->wdt_device);
|
2005-08-17 00:03:23 -07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-03-13 18:31:21 -07:00
|
|
|
static int s3c2410wdt_resume(struct device *dev)
|
2005-08-17 00:03:23 -07:00
|
|
|
{
|
2013-12-05 22:47:47 -07:00
|
|
|
int ret;
|
2013-08-27 03:06:03 -07:00
|
|
|
struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
|
2005-08-17 00:03:23 -07:00
|
|
|
|
2013-08-27 03:06:03 -07:00
|
|
|
/* Restore watchdog state. */
|
|
|
|
writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT);
|
|
|
|
writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */
|
|
|
|
writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON);
|
2005-08-17 00:03:23 -07:00
|
|
|
|
2021-11-23 16:26:13 -07:00
|
|
|
ret = s3c2410wdt_enable(wdt, true);
|
2013-12-05 22:47:47 -07:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2013-03-13 18:31:21 -07:00
|
|
|
dev_info(dev, "watchdog %sabled\n",
|
2013-08-27 03:06:03 -07:00
|
|
|
(wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
|
2005-08-17 00:03:23 -07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2022-06-28 12:34:45 -07:00
|
|
|
static DEFINE_SIMPLE_DEV_PM_OPS(s3c2410wdt_pm_ops,
|
|
|
|
s3c2410wdt_suspend, s3c2410wdt_resume);
|
2005-08-17 00:03:23 -07:00
|
|
|
|
2005-11-09 15:32:44 -07:00
|
|
|
static struct platform_driver s3c2410wdt_driver = {
|
2005-04-16 15:20:36 -07:00
|
|
|
.probe = s3c2410wdt_probe,
|
2005-08-17 00:04:52 -07:00
|
|
|
.shutdown = s3c2410wdt_shutdown,
|
2013-12-05 22:47:47 -07:00
|
|
|
.id_table = s3c2410_wdt_ids,
|
2005-11-09 15:32:44 -07:00
|
|
|
.driver = {
|
|
|
|
.name = "s3c2410-wdt",
|
2022-06-28 12:34:45 -07:00
|
|
|
.pm = pm_sleep_ptr(&s3c2410wdt_pm_ops),
|
2012-05-02 22:24:17 -07:00
|
|
|
.of_match_table = of_match_ptr(s3c2410_wdt_match),
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2005-11-09 15:32:44 -07:00
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},
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2005-04-16 15:20:36 -07:00
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};
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2012-07-12 04:47:40 -07:00
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module_platform_driver(s3c2410wdt_driver);
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2005-04-16 15:20:36 -07:00
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2017-03-13 12:07:26 -07:00
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MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Dimitry Andric <dimitry.andric@tomtom.com>");
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2005-04-16 15:20:36 -07:00
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MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
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MODULE_LICENSE("GPL");
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