2006-01-18 18:44:13 -07:00
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/*
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* MC kernel module
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* (C) 2003 Linux Networx (http://lnxi.com)
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* This file may be distributed under the terms of the
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* GNU General Public License.
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*
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* Written by Thayne Harbaugh
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* Based on work by Dan Hollis <goemon at anime dot net> and others.
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* http://www.anime.net/~goemon/linux-ecc/
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*
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* NMI handling support added by
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* Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
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*
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* $Id: edac_mc.h,v 1.4.2.10 2005/10/05 00:43:44 dsp_llnl Exp $
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*
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*/
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#ifndef _EDAC_MC_H_
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#define _EDAC_MC_H_
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/smp.h>
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#include <linux/pci.h>
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#include <linux/time.h>
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#include <linux/nmi.h>
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#include <linux/rcupdate.h>
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#include <linux/completion.h>
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#include <linux/kobject.h>
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2006-08-05 12:13:45 -07:00
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#include <linux/platform_device.h>
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2006-01-18 18:44:13 -07:00
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#define EDAC_MC_LABEL_LEN 31
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#define MC_PROC_NAME_MAX_LEN 7
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#if PAGE_SHIFT < 20
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#define PAGES_TO_MiB( pages ) ( ( pages ) >> ( 20 - PAGE_SHIFT ) )
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#else /* PAGE_SHIFT > 20 */
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#define PAGES_TO_MiB( pages ) ( ( pages ) << ( PAGE_SHIFT - 20 ) )
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#endif
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2006-03-26 02:38:40 -07:00
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#define edac_printk(level, prefix, fmt, arg...) \
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2006-03-26 02:38:52 -07:00
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printk(level "EDAC " prefix ": " fmt, ##arg)
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2006-03-26 02:38:40 -07:00
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#define edac_mc_printk(mci, level, fmt, arg...) \
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2006-03-26 02:38:52 -07:00
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printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)
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2006-03-26 02:38:40 -07:00
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#define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
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2006-03-26 02:38:52 -07:00
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printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)
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2006-03-26 02:38:40 -07:00
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/* prefixes for edac_printk() and edac_mc_printk() */
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#define EDAC_MC "MC"
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#define EDAC_PCI "PCI"
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#define EDAC_DEBUG "DEBUG"
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2006-01-18 18:44:13 -07:00
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#ifdef CONFIG_EDAC_DEBUG
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extern int edac_debug_level;
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2006-03-26 02:38:40 -07:00
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#define edac_debug_printk(level, fmt, arg...) \
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do { \
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if (level <= edac_debug_level) \
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edac_printk(KERN_DEBUG, EDAC_DEBUG, fmt, ##arg); \
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} while(0)
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2006-01-18 18:44:13 -07:00
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#define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
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#define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
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#define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
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#define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
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#define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )
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2006-03-26 02:38:52 -07:00
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#else /* !CONFIG_EDAC_DEBUG */
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2006-01-18 18:44:13 -07:00
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#define debugf0( ... )
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#define debugf1( ... )
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#define debugf2( ... )
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#define debugf3( ... )
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#define debugf4( ... )
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2006-03-26 02:38:52 -07:00
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#endif /* !CONFIG_EDAC_DEBUG */
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2006-01-18 18:44:13 -07:00
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#define BIT(x) (1 << (x))
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2006-03-26 02:38:52 -07:00
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#define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
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PCI_DEVICE_ID_ ## vend ## _ ## dev
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2006-01-18 18:44:13 -07:00
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2006-06-30 01:56:07 -07:00
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#if defined(CONFIG_X86) && defined(CONFIG_PCI)
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#define dev_name(dev) pci_name(to_pci_dev(dev))
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#else
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#define dev_name(dev) to_platform_device(dev)->name
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#endif
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2006-01-18 18:44:13 -07:00
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/* memory devices */
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enum dev_type {
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DEV_UNKNOWN = 0,
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DEV_X1,
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DEV_X2,
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DEV_X4,
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DEV_X8,
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DEV_X16,
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DEV_X32, /* Do these parts exist? */
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DEV_X64 /* Do these parts exist? */
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};
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#define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
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#define DEV_FLAG_X1 BIT(DEV_X1)
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#define DEV_FLAG_X2 BIT(DEV_X2)
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#define DEV_FLAG_X4 BIT(DEV_X4)
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#define DEV_FLAG_X8 BIT(DEV_X8)
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#define DEV_FLAG_X16 BIT(DEV_X16)
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#define DEV_FLAG_X32 BIT(DEV_X32)
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#define DEV_FLAG_X64 BIT(DEV_X64)
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/* memory types */
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enum mem_type {
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MEM_EMPTY = 0, /* Empty csrow */
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MEM_RESERVED, /* Reserved csrow type */
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MEM_UNKNOWN, /* Unknown csrow type */
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MEM_FPM, /* Fast page mode */
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MEM_EDO, /* Extended data out */
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MEM_BEDO, /* Burst Extended data out */
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MEM_SDR, /* Single data rate SDRAM */
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MEM_RDR, /* Registered single data rate SDRAM */
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MEM_DDR, /* Double data rate SDRAM */
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MEM_RDDR, /* Registered Double data rate SDRAM */
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2007-02-12 01:53:08 -07:00
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MEM_RMBS, /* Rambus DRAM */
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MEM_DDR2, /* DDR2 RAM */
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MEM_FB_DDR2, /* fully buffered DDR2 */
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2006-01-18 18:44:13 -07:00
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};
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#define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
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#define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
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#define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN)
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#define MEM_FLAG_FPM BIT(MEM_FPM)
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#define MEM_FLAG_EDO BIT(MEM_EDO)
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#define MEM_FLAG_BEDO BIT(MEM_BEDO)
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#define MEM_FLAG_SDR BIT(MEM_SDR)
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#define MEM_FLAG_RDR BIT(MEM_RDR)
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#define MEM_FLAG_DDR BIT(MEM_DDR)
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#define MEM_FLAG_RDDR BIT(MEM_RDDR)
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#define MEM_FLAG_RMBS BIT(MEM_RMBS)
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#define MEM_FLAG_DDR2 BIT(MEM_DDR2)
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#define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2)
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2006-01-18 18:44:13 -07:00
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/* chipset Error Detection and Correction capabilities and mode */
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enum edac_type {
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EDAC_UNKNOWN = 0, /* Unknown if ECC is available */
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EDAC_NONE, /* Doesnt support ECC */
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EDAC_RESERVED, /* Reserved ECC type */
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EDAC_PARITY, /* Detects parity errors */
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EDAC_EC, /* Error Checking - no correction */
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EDAC_SECDED, /* Single bit error correction, Double detection */
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EDAC_S2ECD2ED, /* Chipkill x2 devices - do these exist? */
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EDAC_S4ECD4ED, /* Chipkill x4 devices */
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EDAC_S8ECD8ED, /* Chipkill x8 devices */
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EDAC_S16ECD16ED, /* Chipkill x16 devices */
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};
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#define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
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#define EDAC_FLAG_NONE BIT(EDAC_NONE)
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#define EDAC_FLAG_PARITY BIT(EDAC_PARITY)
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#define EDAC_FLAG_EC BIT(EDAC_EC)
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#define EDAC_FLAG_SECDED BIT(EDAC_SECDED)
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#define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED)
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#define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED)
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#define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
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#define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
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/* scrubbing capabilities */
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enum scrub_type {
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SCRUB_UNKNOWN = 0, /* Unknown if scrubber is available */
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SCRUB_NONE, /* No scrubber */
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SCRUB_SW_PROG, /* SW progressive (sequential) scrubbing */
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SCRUB_SW_SRC, /* Software scrub only errors */
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SCRUB_SW_PROG_SRC, /* Progressive software scrub from an error */
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SCRUB_SW_TUNABLE, /* Software scrub frequency is tunable */
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SCRUB_HW_PROG, /* HW progressive (sequential) scrubbing */
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SCRUB_HW_SRC, /* Hardware scrub only errors */
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SCRUB_HW_PROG_SRC, /* Progressive hardware scrub from an error */
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SCRUB_HW_TUNABLE /* Hardware scrub frequency is tunable */
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};
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#define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
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#define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC_CORR)
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#define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC_CORR)
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#define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE)
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#define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG)
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#define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC_CORR)
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#define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC_CORR)
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#define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE)
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/* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
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/*
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* There are several things to be aware of that aren't at all obvious:
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*
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*
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* SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
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*
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* These are some of the many terms that are thrown about that don't always
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* mean what people think they mean (Inconceivable!). In the interest of
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* creating a common ground for discussion, terms and their definitions
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* will be established.
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*
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* Memory devices: The individual chip on a memory stick. These devices
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* commonly output 4 and 8 bits each. Grouping several
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* of these in parallel provides 64 bits which is common
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* for a memory stick.
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*
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* Memory Stick: A printed circuit board that agregates multiple
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* memory devices in parallel. This is the atomic
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* memory component that is purchaseable by Joe consumer
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* and loaded into a memory socket.
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*
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* Socket: A physical connector on the motherboard that accepts
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* a single memory stick.
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*
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* Channel: Set of memory devices on a memory stick that must be
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* grouped in parallel with one or more additional
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* channels from other memory sticks. This parallel
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* grouping of the output from multiple channels are
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* necessary for the smallest granularity of memory access.
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* Some memory controllers are capable of single channel -
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* which means that memory sticks can be loaded
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* individually. Other memory controllers are only
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* capable of dual channel - which means that memory
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* sticks must be loaded as pairs (see "socket set").
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*
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* Chip-select row: All of the memory devices that are selected together.
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* for a single, minimum grain of memory access.
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* This selects all of the parallel memory devices across
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* all of the parallel channels. Common chip-select rows
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* for single channel are 64 bits, for dual channel 128
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* bits.
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*
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* Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memmory.
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* Motherboards commonly drive two chip-select pins to
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* a memory stick. A single-ranked stick, will occupy
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* only one of those rows. The other will be unused.
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*
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* Double-Ranked stick: A double-ranked stick has two chip-select rows which
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* access different sets of memory devices. The two
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* rows cannot be accessed concurrently.
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*
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* Double-sided stick: DEPRECATED TERM, see Double-Ranked stick.
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* A double-sided stick has two chip-select rows which
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* access different sets of memory devices. The two
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* rows cannot be accessed concurrently. "Double-sided"
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* is irrespective of the memory devices being mounted
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* on both sides of the memory stick.
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*
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* Socket set: All of the memory sticks that are required for for
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* a single memory access or all of the memory sticks
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* spanned by a chip-select row. A single socket set
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* has two chip-select rows and if double-sided sticks
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* are used these will occupy those chip-select rows.
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*
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* Bank: This term is avoided because it is unclear when
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* needing to distinguish between chip-select rows and
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* socket sets.
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*
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* Controller pages:
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*
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* Physical pages:
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*
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* Virtual pages:
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*
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*
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* STRUCTURE ORGANIZATION AND CHOICES
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*
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*
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*
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* PS - I enjoyed writing all that about as much as you enjoyed reading it.
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*/
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struct channel_info {
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int chan_idx; /* channel index */
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u32 ce_count; /* Correctable Errors for this CHANNEL */
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2006-03-26 02:38:52 -07:00
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char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */
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2006-01-18 18:44:13 -07:00
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struct csrow_info *csrow; /* the parent */
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};
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struct csrow_info {
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unsigned long first_page; /* first page number in dimm */
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unsigned long last_page; /* last page number in dimm */
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unsigned long page_mask; /* used for interleaving -
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2006-03-26 02:38:52 -07:00
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* 0UL for non intlv
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*/
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2006-01-18 18:44:13 -07:00
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u32 nr_pages; /* number of pages in csrow */
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u32 grain; /* granularity of reported error in bytes */
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int csrow_idx; /* the chip-select row */
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enum dev_type dtype; /* memory device type */
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u32 ue_count; /* Uncorrectable Errors for this csrow */
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u32 ce_count; /* Correctable Errors for this csrow */
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enum mem_type mtype; /* memory csrow type */
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enum edac_type edac_mode; /* EDAC mode for this csrow */
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struct mem_ctl_info *mci; /* the parent */
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struct kobject kobj; /* sysfs kobject for this csrow */
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2006-03-26 02:38:49 -07:00
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struct completion kobj_complete;
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2006-01-18 18:44:13 -07:00
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/* FIXME the number of CHANNELs might need to become dynamic */
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u32 nr_channels;
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struct channel_info *channels;
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};
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struct mem_ctl_info {
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struct list_head link; /* for global list of mem_ctl_info structs */
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unsigned long mtype_cap; /* memory types supported by mc */
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unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */
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unsigned long edac_cap; /* configuration capabilities - this is
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2006-03-26 02:38:52 -07:00
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* closely related to edac_ctl_cap. The
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* difference is that the controller may be
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* capable of s4ecd4ed which would be listed
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* in edac_ctl_cap, but if channels aren't
|
|
|
|
* capable of s4ecd4ed then the edac_cap would
|
|
|
|
* not have that capability.
|
|
|
|
*/
|
2006-01-18 18:44:13 -07:00
|
|
|
unsigned long scrub_cap; /* chipset scrub capabilities */
|
|
|
|
enum scrub_type scrub_mode; /* current scrub mode */
|
|
|
|
|
[PATCH] EDAC: Add memory scrubbing controls API to core
This is an attempt of providing an interface for memory scrubbing control in
EDAC.
This patch modifies the EDAC Core to provide the Interface for memory
controller modules to implment.
The following things are still outstanding:
- K8 is the first implemenation,
The patch provide a method of configuring the K8 hardware memory scrubber
via the 'mcX' sysfs directory. There should be some fallback to a generic
scrubber implemented in software if the hardware does not support
scrubbing.
Or .. the scrubbing sysfs entry should not be visible at all.
- Only works with SDRAM, not cache,
The K8 can scrub cache and l2cache also - but I think this is not so
useful as the cache is busy all the time (one hopes).
One would also expect that cache scrubbing requires hardware support.
- Error Handling,
I would like that errors are returned to the user in "terms of file
system".
- Presentation,
I chose Bandwidth in Bytes/Second as a representation of the scrubbing
rate for the following reasons:
I like that the sysfs entries are sort-of textual, related to something
that makes sense instead of magical values that must be looked up.
"My People" wants "% main memory scrubbed per hour" others prefer "%
memory bandwidth used" as representation, "bandwith used" makes it easy to
calculate both versions in one-liner scripts.
If one later wants to scrub cache, the scaling becomes wierd for K8
changing from "blocks of 64 byte memory" to "blocks of 64 cache lines" to
"blocks of 64 bit". Using "bandwidth used" makes sense in all three cases,
(I.M.O. anyway ;-).
- Discovery,
There is no way to discover the possible settings and what they do
without reading the code and the documentation.
*I* do not know how to make that work in a practical way.
- Bugs(??),
other tools can set invalid values in the memory scrub control register,
those will read back as '-1', requiring the user to reset the scrub rate.
This is how *I* think it should be.
- Afflicting other areas of code,
I made changes to edac_mc.c and edac_mc.h which will show up globally -
this is not nice, it would be better that the memory scrubbing fuctionality
and interface could be entirely contained within the memory controller it
applies to.
Frithiof Jensen
edac_mc.c and its .h file is a CORE helper module for EDAC
driver modules. This provides the abstraction for device specific
drivers. It is fine to modify this CORE to provide help for
new features of the the drivers
doug thompson
Signed-off-by: Frithiof Jensen <frithiof.jensen@ericson.com>
Signed-off-by: doug thompson <norsk5@xmission.com>
Acked-by: Alan Cox <alan@redhat.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-02-12 01:53:07 -07:00
|
|
|
/* Translates sdram memory scrub rate given in bytes/sec to the
|
|
|
|
internal representation and configures whatever else needs
|
|
|
|
to be configured.
|
|
|
|
*/
|
|
|
|
int (*set_sdram_scrub_rate) (struct mem_ctl_info *mci, u32 *bw);
|
|
|
|
|
|
|
|
/* Get the current sdram memory scrub rate from the internal
|
|
|
|
representation and converts it to the closest matching
|
|
|
|
bandwith in bytes/sec.
|
|
|
|
*/
|
|
|
|
int (*get_sdram_scrub_rate) (struct mem_ctl_info *mci, u32 *bw);
|
|
|
|
|
2006-01-18 18:44:13 -07:00
|
|
|
/* pointer to edac checking routine */
|
|
|
|
void (*edac_check) (struct mem_ctl_info * mci);
|
2007-02-12 01:53:08 -07:00
|
|
|
|
2006-01-18 18:44:13 -07:00
|
|
|
/*
|
|
|
|
* Remaps memory pages: controller pages to physical pages.
|
|
|
|
* For most MC's, this will be NULL.
|
|
|
|
*/
|
|
|
|
/* FIXME - why not send the phys page to begin with? */
|
|
|
|
unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
|
2006-03-26 02:38:52 -07:00
|
|
|
unsigned long page);
|
2006-01-18 18:44:13 -07:00
|
|
|
int mc_idx;
|
|
|
|
int nr_csrows;
|
|
|
|
struct csrow_info *csrows;
|
|
|
|
/*
|
|
|
|
* FIXME - what about controllers on other busses? - IDs must be
|
2006-06-30 01:56:07 -07:00
|
|
|
* unique. dev pointer should be sufficiently unique, but
|
2006-01-18 18:44:13 -07:00
|
|
|
* BUS:SLOT.FUNC numbers may not be unique.
|
|
|
|
*/
|
2006-06-30 01:56:07 -07:00
|
|
|
struct device *dev;
|
2006-01-18 18:44:13 -07:00
|
|
|
const char *mod_name;
|
|
|
|
const char *mod_ver;
|
|
|
|
const char *ctl_name;
|
|
|
|
char proc_name[MC_PROC_NAME_MAX_LEN + 1];
|
|
|
|
void *pvt_info;
|
|
|
|
u32 ue_noinfo_count; /* Uncorrectable Errors w/o info */
|
|
|
|
u32 ce_noinfo_count; /* Correctable Errors w/o info */
|
|
|
|
u32 ue_count; /* Total Uncorrectable Errors for this MC */
|
|
|
|
u32 ce_count; /* Total Correctable Errors for this MC */
|
|
|
|
unsigned long start_time; /* mci load start time (in jiffies) */
|
|
|
|
|
|
|
|
/* this stuff is for safe removal of mc devices from global list while
|
|
|
|
* NMI handlers may be traversing list
|
|
|
|
*/
|
|
|
|
struct rcu_head rcu;
|
|
|
|
struct completion complete;
|
|
|
|
|
|
|
|
/* edac sysfs device control */
|
|
|
|
struct kobject edac_mci_kobj;
|
2006-03-26 02:38:49 -07:00
|
|
|
struct completion kobj_complete;
|
2006-01-18 18:44:13 -07:00
|
|
|
};
|
|
|
|
|
2006-06-30 01:56:07 -07:00
|
|
|
#ifdef CONFIG_PCI
|
|
|
|
|
2006-01-18 18:44:13 -07:00
|
|
|
/* write all or some bits in a byte-register*/
|
2006-03-26 02:38:52 -07:00
|
|
|
static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
|
|
|
|
u8 mask)
|
2006-01-18 18:44:13 -07:00
|
|
|
{
|
|
|
|
if (mask != 0xff) {
|
|
|
|
u8 buf;
|
2006-03-26 02:38:52 -07:00
|
|
|
|
2006-01-18 18:44:13 -07:00
|
|
|
pci_read_config_byte(pdev, offset, &buf);
|
|
|
|
value &= mask;
|
|
|
|
buf &= ~mask;
|
|
|
|
value |= buf;
|
|
|
|
}
|
2006-03-26 02:38:52 -07:00
|
|
|
|
2006-01-18 18:44:13 -07:00
|
|
|
pci_write_config_byte(pdev, offset, value);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* write all or some bits in a word-register*/
|
|
|
|
static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
|
2006-03-26 02:38:52 -07:00
|
|
|
u16 value, u16 mask)
|
2006-01-18 18:44:13 -07:00
|
|
|
{
|
|
|
|
if (mask != 0xffff) {
|
|
|
|
u16 buf;
|
2006-03-26 02:38:52 -07:00
|
|
|
|
2006-01-18 18:44:13 -07:00
|
|
|
pci_read_config_word(pdev, offset, &buf);
|
|
|
|
value &= mask;
|
|
|
|
buf &= ~mask;
|
|
|
|
value |= buf;
|
|
|
|
}
|
2006-03-26 02:38:52 -07:00
|
|
|
|
2006-01-18 18:44:13 -07:00
|
|
|
pci_write_config_word(pdev, offset, value);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* write all or some bits in a dword-register*/
|
|
|
|
static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
|
2006-03-26 02:38:52 -07:00
|
|
|
u32 value, u32 mask)
|
2006-01-18 18:44:13 -07:00
|
|
|
{
|
|
|
|
if (mask != 0xffff) {
|
|
|
|
u32 buf;
|
2006-03-26 02:38:52 -07:00
|
|
|
|
2006-01-18 18:44:13 -07:00
|
|
|
pci_read_config_dword(pdev, offset, &buf);
|
|
|
|
value &= mask;
|
|
|
|
buf &= ~mask;
|
|
|
|
value |= buf;
|
|
|
|
}
|
2006-03-26 02:38:52 -07:00
|
|
|
|
2006-01-18 18:44:13 -07:00
|
|
|
pci_write_config_dword(pdev, offset, value);
|
|
|
|
}
|
|
|
|
|
2006-06-30 01:56:07 -07:00
|
|
|
#endif /* CONFIG_PCI */
|
|
|
|
|
2006-01-18 18:44:13 -07:00
|
|
|
#ifdef CONFIG_EDAC_DEBUG
|
|
|
|
void edac_mc_dump_channel(struct channel_info *chan);
|
|
|
|
void edac_mc_dump_mci(struct mem_ctl_info *mci);
|
|
|
|
void edac_mc_dump_csrow(struct csrow_info *csrow);
|
2006-03-26 02:38:52 -07:00
|
|
|
#endif /* CONFIG_EDAC_DEBUG */
|
2006-01-18 18:44:13 -07:00
|
|
|
|
2006-06-30 01:56:08 -07:00
|
|
|
extern int edac_mc_add_mc(struct mem_ctl_info *mci,int mc_idx);
|
2006-06-30 01:56:07 -07:00
|
|
|
extern struct mem_ctl_info * edac_mc_del_mc(struct device *dev);
|
2006-01-18 18:44:13 -07:00
|
|
|
extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
|
2006-03-26 02:38:52 -07:00
|
|
|
unsigned long page);
|
|
|
|
extern void edac_mc_scrub_block(unsigned long page, unsigned long offset,
|
|
|
|
u32 size);
|
2006-01-18 18:44:13 -07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* The no info errors are used when error overflows are reported.
|
|
|
|
* There are a limited number of error logging registers that can
|
|
|
|
* be exausted. When all registers are exhausted and an additional
|
|
|
|
* error occurs then an error overflow register records that an
|
|
|
|
* error occured and the type of error, but doesn't have any
|
|
|
|
* further information. The ce/ue versions make for cleaner
|
|
|
|
* reporting logic and function interface - reduces conditional
|
|
|
|
* statement clutter and extra function arguments.
|
|
|
|
*/
|
|
|
|
extern void edac_mc_handle_ce(struct mem_ctl_info *mci,
|
2006-03-26 02:38:52 -07:00
|
|
|
unsigned long page_frame_number, unsigned long offset_in_page,
|
|
|
|
unsigned long syndrome, int row, int channel,
|
|
|
|
const char *msg);
|
2006-01-18 18:44:13 -07:00
|
|
|
extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci,
|
2006-03-26 02:38:52 -07:00
|
|
|
const char *msg);
|
2006-01-18 18:44:13 -07:00
|
|
|
extern void edac_mc_handle_ue(struct mem_ctl_info *mci,
|
2006-03-26 02:38:52 -07:00
|
|
|
unsigned long page_frame_number, unsigned long offset_in_page,
|
|
|
|
int row, const char *msg);
|
2006-01-18 18:44:13 -07:00
|
|
|
extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci,
|
2006-03-26 02:38:52 -07:00
|
|
|
const char *msg);
|
2007-02-12 01:53:08 -07:00
|
|
|
extern void edac_mc_handle_fbd_ue(struct mem_ctl_info *mci,
|
|
|
|
unsigned int csrow,
|
|
|
|
unsigned int channel0,
|
|
|
|
unsigned int channel1,
|
|
|
|
char *msg);
|
|
|
|
extern void edac_mc_handle_fbd_ce(struct mem_ctl_info *mci,
|
|
|
|
unsigned int csrow,
|
|
|
|
unsigned int channel,
|
|
|
|
char *msg);
|
2006-01-18 18:44:13 -07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* This kmalloc's and initializes all the structures.
|
|
|
|
* Can't be used if all structures don't have the same lifetime.
|
|
|
|
*/
|
2006-03-26 02:38:52 -07:00
|
|
|
extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
|
|
|
|
unsigned nr_chans);
|
2006-01-18 18:44:13 -07:00
|
|
|
|
|
|
|
/* Free an mc previously allocated by edac_mc_alloc() */
|
|
|
|
extern void edac_mc_free(struct mem_ctl_info *mci);
|
|
|
|
|
|
|
|
#endif /* _EDAC_MC_H_ */
|