453 lines
16 KiB
C
453 lines
16 KiB
C
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/*
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* xHCI host controller driver
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*
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* Copyright (C) 2008 Intel Corp.
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*
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* Author: Sarah Sharp
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* Some code borrowed from the Linux EHCI driver.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __LINUX_XHCI_HCD_H
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#define __LINUX_XHCI_HCD_H
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#include <linux/usb.h>
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#include "../core/hcd.h"
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/* Code sharing between pci-quirks and xhci hcd */
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#include "xhci-ext-caps.h"
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/* xHCI PCI Configuration Registers */
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#define XHCI_SBRN_OFFSET (0x60)
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/*
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* xHCI register interface.
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* This corresponds to the eXtensible Host Controller Interface (xHCI)
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* Revision 0.95 specification
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*
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* Registers should always be accessed with double word or quad word accesses.
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*
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* Some xHCI implementations may support 64-bit address pointers. Registers
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* with 64-bit address pointers should be written to with dword accesses by
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* writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
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* xHCI implementations that do not support 64-bit address pointers will ignore
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* the high dword, and write order is irrelevant.
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*/
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/**
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* struct xhci_cap_regs - xHCI Host Controller Capability Registers.
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* @hc_capbase: length of the capabilities register and HC version number
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* @hcs_params1: HCSPARAMS1 - Structural Parameters 1
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* @hcs_params2: HCSPARAMS2 - Structural Parameters 2
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* @hcs_params3: HCSPARAMS3 - Structural Parameters 3
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* @hcc_params: HCCPARAMS - Capability Parameters
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* @db_off: DBOFF - Doorbell array offset
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* @run_regs_off: RTSOFF - Runtime register space offset
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*/
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struct xhci_cap_regs {
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u32 hc_capbase;
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u32 hcs_params1;
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u32 hcs_params2;
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u32 hcs_params3;
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u32 hcc_params;
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u32 db_off;
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u32 run_regs_off;
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/* Reserved up to (CAPLENGTH - 0x1C) */
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} __attribute__ ((packed));
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/* hc_capbase bitmasks */
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/* bits 7:0 - how long is the Capabilities register */
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#define HC_LENGTH(p) XHCI_HC_LENGTH(p)
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/* bits 31:16 */
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#define HC_VERSION(p) (((p) >> 16) & 0xffff)
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/* HCSPARAMS1 - hcs_params1 - bitmasks */
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/* bits 0:7, Max Device Slots */
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#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
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#define HCS_SLOTS_MASK 0xff
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/* bits 8:18, Max Interrupters */
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#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
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/* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
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#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
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/* HCSPARAMS2 - hcs_params2 - bitmasks */
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/* bits 0:3, frames or uframes that SW needs to queue transactions
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* ahead of the HW to meet periodic deadlines */
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#define HCS_IST(p) (((p) >> 0) & 0xf)
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/* bits 4:7, max number of Event Ring segments */
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#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
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/* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
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/* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */
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/* HCSPARAMS3 - hcs_params3 - bitmasks */
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/* bits 0:7, Max U1 to U0 latency for the roothub ports */
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#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
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/* bits 16:31, Max U2 to U0 latency for the roothub ports */
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#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
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/* HCCPARAMS - hcc_params - bitmasks */
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/* true: HC can use 64-bit address pointers */
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#define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
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/* true: HC can do bandwidth negotiation */
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#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
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/* true: HC uses 64-byte Device Context structures
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* FIXME 64-byte context structures aren't supported yet.
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*/
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#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
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/* true: HC has port power switches */
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#define HCC_PPC(p) ((p) & (1 << 3))
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/* true: HC has port indicators */
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#define HCS_INDICATOR(p) ((p) & (1 << 4))
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/* true: HC has Light HC Reset Capability */
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#define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
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/* true: HC supports latency tolerance messaging */
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#define HCC_LTC(p) ((p) & (1 << 6))
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/* true: no secondary Stream ID Support */
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#define HCC_NSS(p) ((p) & (1 << 7))
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/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
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#define HCC_MAX_PSA (1 << ((((p) >> 12) & 0xf) + 1))
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/* Extended Capabilities pointer from PCI base - section 5.3.6 */
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#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
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/* db_off bitmask - bits 0:1 reserved */
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#define DBOFF_MASK (~0x3)
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/* run_regs_off bitmask - bits 0:4 reserved */
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#define RTSOFF_MASK (~0x1f)
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/* Number of registers per port */
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#define NUM_PORT_REGS 4
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/**
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* struct xhci_op_regs - xHCI Host Controller Operational Registers.
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* @command: USBCMD - xHC command register
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* @status: USBSTS - xHC status register
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* @page_size: This indicates the page size that the host controller
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* supports. If bit n is set, the HC supports a page size
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* of 2^(n+12), up to a 128MB page size.
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* 4K is the minimum page size.
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* @cmd_ring: CRP - 64-bit Command Ring Pointer
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* @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
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* @config_reg: CONFIG - Configure Register
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* @port_status_base: PORTSCn - base address for Port Status and Control
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* Each port has a Port Status and Control register,
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* followed by a Port Power Management Status and Control
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* register, a Port Link Info register, and a reserved
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* register.
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* @port_power_base: PORTPMSCn - base address for
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* Port Power Management Status and Control
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* @port_link_base: PORTLIn - base address for Port Link Info (current
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* Link PM state and control) for USB 2.1 and USB 3.0
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* devices.
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*/
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struct xhci_op_regs {
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u32 command;
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u32 status;
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u32 page_size;
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u32 reserved1;
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u32 reserved2;
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u32 dev_notification;
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u32 cmd_ring[2];
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/* rsvd: offset 0x20-2F */
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u32 reserved3[4];
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u32 dcbaa_ptr[2];
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u32 config_reg;
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/* rsvd: offset 0x3C-3FF */
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u32 reserved4[241];
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/* port 1 registers, which serve as a base address for other ports */
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u32 port_status_base;
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u32 port_power_base;
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u32 port_link_base;
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u32 reserved5;
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/* registers for ports 2-255 */
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u32 reserved6[NUM_PORT_REGS*254];
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} __attribute__ ((packed));
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/* USBCMD - USB command - command bitmasks */
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/* start/stop HC execution - do not write unless HC is halted*/
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#define CMD_RUN XHCI_CMD_RUN
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/* Reset HC - resets internal HC state machine and all registers (except
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* PCI config regs). HC does NOT drive a USB reset on the downstream ports.
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* The xHCI driver must reinitialize the xHC after setting this bit.
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*/
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#define CMD_RESET (1 << 1)
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/* Event Interrupt Enable - a '1' allows interrupts from the host controller */
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#define CMD_EIE XHCI_CMD_EIE
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/* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
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#define CMD_HSEIE XHCI_CMD_HSEIE
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/* bits 4:6 are reserved (and should be preserved on writes). */
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/* light reset (port status stays unchanged) - reset completed when this is 0 */
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#define CMD_LRESET (1 << 7)
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/* FIXME: ignoring host controller save/restore state for now. */
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#define CMD_CSS (1 << 8)
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#define CMD_CRS (1 << 9)
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/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
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#define CMD_EWE XHCI_CMD_EWE
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/* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
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* hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
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* '0' means the xHC can power it off if all ports are in the disconnect,
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* disabled, or powered-off state.
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*/
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#define CMD_PM_INDEX (1 << 11)
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/* bits 12:31 are reserved (and should be preserved on writes). */
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/* USBSTS - USB status - status bitmasks */
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/* HC not running - set to 1 when run/stop bit is cleared. */
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#define STS_HALT XHCI_STS_HALT
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/* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
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#define STS_FATAL (1 << 2)
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/* event interrupt - clear this prior to clearing any IP flags in IR set*/
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#define STS_EINT (1 << 3)
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/* port change detect */
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#define STS_PORT (1 << 4)
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/* bits 5:7 reserved and zeroed */
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/* save state status - '1' means xHC is saving state */
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#define STS_SAVE (1 << 8)
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/* restore state status - '1' means xHC is restoring state */
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#define STS_RESTORE (1 << 9)
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/* true: save or restore error */
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#define STS_SRE (1 << 10)
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/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
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#define STS_CNR XHCI_STS_CNR
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/* true: internal Host Controller Error - SW needs to reset and reinitialize */
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#define STS_HCE (1 << 12)
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/* bits 13:31 reserved and should be preserved */
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/*
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* DNCTRL - Device Notification Control Register - dev_notification bitmasks
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* Generate a device notification event when the HC sees a transaction with a
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* notification type that matches a bit set in this bit field.
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*/
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#define DEV_NOTE_MASK (0xffff)
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#define ENABLE_DEV_NOTE(x) (1 << x)
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/* Most of the device notification types should only be used for debug.
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* SW does need to pay attention to function wake notifications.
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*/
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#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
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/* CONFIG - Configure Register - config_reg bitmasks */
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/* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
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#define MAX_DEVS(p) ((p) & 0xff)
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/* bits 8:31 - reserved and should be preserved */
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/* PORTSC - Port Status and Control Register - port_status_base bitmasks */
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/* true: device connected */
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#define PORT_CONNECT (1 << 0)
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/* true: port enabled */
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#define PORT_PE (1 << 1)
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/* bit 2 reserved and zeroed */
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/* true: port has an over-current condition */
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#define PORT_OC (1 << 3)
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/* true: port reset signaling asserted */
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#define PORT_RESET (1 << 4)
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/* Port Link State - bits 5:8
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* A read gives the current link PM state of the port,
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* a write with Link State Write Strobe set sets the link state.
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*/
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/* true: port has power (see HCC_PPC) */
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#define PORT_POWER (1 << 9)
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/* bits 10:13 indicate device speed:
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* 0 - undefined speed - port hasn't be initialized by a reset yet
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* 1 - full speed
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* 2 - low speed
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* 3 - high speed
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* 4 - super speed
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* 5-15 reserved
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*/
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#define DEV_SPEED_MASK (0xf<<10)
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#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
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#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == (0x1<<10))
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#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == (0x2<<10))
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#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == (0x3<<10))
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#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == (0x4<<10))
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/* Port Indicator Control */
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#define PORT_LED_OFF (0 << 14)
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#define PORT_LED_AMBER (1 << 14)
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#define PORT_LED_GREEN (2 << 14)
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#define PORT_LED_MASK (3 << 14)
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/* Port Link State Write Strobe - set this when changing link state */
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#define PORT_LINK_STROBE (1 << 16)
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/* true: connect status change */
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#define PORT_CSC (1 << 17)
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/* true: port enable change */
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#define PORT_PEC (1 << 18)
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/* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
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* into an enabled state, and the device into the default state. A "warm" reset
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* also resets the link, forcing the device through the link training sequence.
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* SW can also look at the Port Reset register to see when warm reset is done.
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*/
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#define PORT_WRC (1 << 19)
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/* true: over-current change */
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#define PORT_OCC (1 << 20)
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/* true: reset change - 1 to 0 transition of PORT_RESET */
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#define PORT_RC (1 << 21)
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/* port link status change - set on some port link state transitions:
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* Transition Reason
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* ------------------------------------------------------------------------------
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* - U3 to Resume Wakeup signaling from a device
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* - Resume to Recovery to U0 USB 3.0 device resume
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* - Resume to U0 USB 2.0 device resume
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* - U3 to Recovery to U0 Software resume of USB 3.0 device complete
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* - U3 to U0 Software resume of USB 2.0 device complete
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* - U2 to U0 L1 resume of USB 2.1 device complete
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* - U0 to U0 (???) L1 entry rejection by USB 2.1 device
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* - U0 to disabled L1 entry error with USB 2.1 device
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* - Any state to inactive Error on USB 3.0 port
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*/
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#define PORT_PLC (1 << 22)
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/* port configure error change - port failed to configure its link partner */
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#define PORT_CEC (1 << 23)
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/* bit 24 reserved */
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/* wake on connect (enable) */
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#define PORT_WKCONN_E (1 << 25)
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/* wake on disconnect (enable) */
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#define PORT_WKDISC_E (1 << 26)
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/* wake on over-current (enable) */
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#define PORT_WKOC_E (1 << 27)
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/* bits 28:29 reserved */
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/* true: device is removable - for USB 3.0 roothub emulation */
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#define PORT_DEV_REMOVE (1 << 30)
|
||
|
|
/* Initiate a warm port reset - complete when PORT_WRC is '1' */
|
||
|
|
#define PORT_WR (1 << 31)
|
||
|
|
|
||
|
|
/* Port Power Management Status and Control - port_power_base bitmasks */
|
||
|
|
/* Inactivity timer value for transitions into U1, in microseconds.
|
||
|
|
* Timeout can be up to 127us. 0xFF means an infinite timeout.
|
||
|
|
*/
|
||
|
|
#define PORT_U1_TIMEOUT(p) ((p) & 0xff)
|
||
|
|
/* Inactivity timer value for transitions into U2 */
|
||
|
|
#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
|
||
|
|
/* Bits 24:31 for port testing */
|
||
|
|
|
||
|
|
|
||
|
|
/**
|
||
|
|
* struct intr_reg - Interrupt Register Set
|
||
|
|
* @irq_pending: IMAN - Interrupt Management Register. Used to enable
|
||
|
|
* interrupts and check for pending interrupts.
|
||
|
|
* @irq_control: IMOD - Interrupt Moderation Register.
|
||
|
|
* Used to throttle interrupts.
|
||
|
|
* @erst_size: Number of segments in the Event Ring Segment Table (ERST).
|
||
|
|
* @erst_base: ERST base address.
|
||
|
|
* @erst_dequeue: Event ring dequeue pointer.
|
||
|
|
*
|
||
|
|
* Each interrupter (defined by a MSI-X vector) has an event ring and an Event
|
||
|
|
* Ring Segment Table (ERST) associated with it. The event ring is comprised of
|
||
|
|
* multiple segments of the same size. The HC places events on the ring and
|
||
|
|
* "updates the Cycle bit in the TRBs to indicate to software the current
|
||
|
|
* position of the Enqueue Pointer." The HCD (Linux) processes those events and
|
||
|
|
* updates the dequeue pointer.
|
||
|
|
*/
|
||
|
|
struct intr_reg {
|
||
|
|
u32 irq_pending;
|
||
|
|
u32 irq_control;
|
||
|
|
u32 erst_size;
|
||
|
|
u32 rsvd;
|
||
|
|
u32 erst_base[2];
|
||
|
|
u32 erst_dequeue[2];
|
||
|
|
} __attribute__ ((packed));
|
||
|
|
|
||
|
|
#define ER_IRQ_PENDING(p) ((p) & 0x1)
|
||
|
|
#define ER_IRQ_ENABLE(p) ((p) | 0x2)
|
||
|
|
/* Preserve bits 16:31 of erst_size */
|
||
|
|
#define ERST_SIZE_MASK (0xffff<<16)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* struct xhci_run_regs
|
||
|
|
* @microframe_index:
|
||
|
|
* MFINDEX - current microframe number
|
||
|
|
*
|
||
|
|
* Section 5.5 Host Controller Runtime Registers:
|
||
|
|
* "Software should read and write these registers using only Dword (32 bit)
|
||
|
|
* or larger accesses"
|
||
|
|
*/
|
||
|
|
struct xhci_run_regs {
|
||
|
|
u32 microframe_index;
|
||
|
|
u32 rsvd[7];
|
||
|
|
struct intr_reg ir_set[128];
|
||
|
|
} __attribute__ ((packed));
|
||
|
|
|
||
|
|
|
||
|
|
/* There is one ehci_hci structure per controller */
|
||
|
|
struct xhci_hcd {
|
||
|
|
/* glue to PCI and HCD framework */
|
||
|
|
struct xhci_cap_regs __iomem *cap_regs;
|
||
|
|
struct xhci_op_regs __iomem *op_regs;
|
||
|
|
struct xhci_run_regs __iomem *run_regs;
|
||
|
|
|
||
|
|
/* Cached register copies of read-only HC data */
|
||
|
|
__u32 hcs_params1;
|
||
|
|
__u32 hcs_params2;
|
||
|
|
__u32 hcs_params3;
|
||
|
|
__u32 hcc_params;
|
||
|
|
|
||
|
|
spinlock_t lock;
|
||
|
|
|
||
|
|
/* packed release number */
|
||
|
|
u8 sbrn;
|
||
|
|
u16 hci_version;
|
||
|
|
u8 max_slots;
|
||
|
|
u8 max_interrupters;
|
||
|
|
u8 max_ports;
|
||
|
|
u8 isoc_threshold;
|
||
|
|
int event_ring_max;
|
||
|
|
int addr_64;
|
||
|
|
int page_size;
|
||
|
|
};
|
||
|
|
|
||
|
|
/* convert between an HCD pointer and the corresponding EHCI_HCD */
|
||
|
|
static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
|
||
|
|
{
|
||
|
|
return (struct xhci_hcd *) (hcd->hcd_priv);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
|
||
|
|
{
|
||
|
|
return container_of((void *) xhci, struct usb_hcd, hcd_priv);
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
|
||
|
|
#define XHCI_DEBUG 1
|
||
|
|
#else
|
||
|
|
#define XHCI_DEBUG 0
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#define xhci_dbg(xhci, fmt, args...) \
|
||
|
|
do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
|
||
|
|
#define xhci_info(xhci, fmt, args...) \
|
||
|
|
do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
|
||
|
|
#define xhci_err(xhci, fmt, args...) \
|
||
|
|
dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
|
||
|
|
#define xhci_warn(xhci, fmt, args...) \
|
||
|
|
dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
|
||
|
|
|
||
|
|
/* TODO: copied from ehci.h - can be refactored? */
|
||
|
|
/* xHCI spec says all registers are little endian */
|
||
|
|
static inline unsigned int xhci_readl(const struct xhci_hcd *xhci,
|
||
|
|
__u32 __iomem *regs)
|
||
|
|
{
|
||
|
|
return readl(regs);
|
||
|
|
}
|
||
|
|
static inline void xhci_writel(const struct xhci_hcd *xhci,
|
||
|
|
const unsigned int val, __u32 __iomem *regs)
|
||
|
|
{
|
||
|
|
if (!in_interrupt())
|
||
|
|
xhci_dbg(xhci, "`MEM_WRITE_DWORD(3'b000, 32'h%0x, 32'h%0x, 4'hf);\n",
|
||
|
|
(unsigned int) regs, val);
|
||
|
|
writel(val, regs);
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* __LINUX_XHCI_HCD_H */
|