2005-04-16 15:20:36 -07:00
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/*
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* sata_sx4.c - Promise SATA
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*
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* Maintained by: Jeff Garzik <jgarzik@pobox.com>
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* Please ALWAYS copy linux-ide@vger.kernel.org
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* on emails.
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*
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* Copyright 2003-2004 Red Hat, Inc.
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*
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2005-08-28 17:18:39 -07:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*
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* libata documentation is available via 'make {ps|pdf}docs',
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* as Documentation/DocBook/libata.*
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*
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* Hardware documentation available under NDA.
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2005-04-16 15:20:36 -07:00
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/sched.h>
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2005-10-30 12:39:11 -07:00
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#include <linux/device.h>
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2005-04-16 15:20:36 -07:00
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#include <scsi/scsi_host.h>
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2005-11-06 22:59:37 -07:00
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#include <scsi/scsi_cmnd.h>
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2005-04-16 15:20:36 -07:00
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#include <linux/libata.h>
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#include <asm/io.h>
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#include "sata_promise.h"
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#define DRV_NAME "sata_sx4"
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2005-11-16 09:06:59 -07:00
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#define DRV_VERSION "0.8"
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2005-04-16 15:20:36 -07:00
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enum {
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PDC_PRD_TBL = 0x44, /* Direct command DMA table addr */
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PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
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PDC_HDMA_PKT_SUBMIT = 0x100, /* Host DMA packet pointer addr */
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PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
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PDC_HDMA_CTLSTAT = 0x12C, /* Host DMA control / status */
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PDC_20621_SEQCTL = 0x400,
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PDC_20621_SEQMASK = 0x480,
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PDC_20621_GENERAL_CTL = 0x484,
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PDC_20621_PAGE_SIZE = (32 * 1024),
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/* chosen, not constant, values; we design our own DIMM mem map */
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PDC_20621_DIMM_WINDOW = 0x0C, /* page# for 32K DIMM window */
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PDC_20621_DIMM_BASE = 0x00200000,
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PDC_20621_DIMM_DATA = (64 * 1024),
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PDC_DIMM_DATA_STEP = (256 * 1024),
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PDC_DIMM_WINDOW_STEP = (8 * 1024),
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PDC_DIMM_HOST_PRD = (6 * 1024),
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PDC_DIMM_HOST_PKT = (128 * 0),
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PDC_DIMM_HPKT_PRD = (128 * 1),
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PDC_DIMM_ATA_PKT = (128 * 2),
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PDC_DIMM_APKT_PRD = (128 * 3),
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PDC_DIMM_HEADER_SZ = PDC_DIMM_APKT_PRD + 128,
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PDC_PAGE_WINDOW = 0x40,
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PDC_PAGE_DATA = PDC_PAGE_WINDOW +
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(PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE),
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PDC_PAGE_SET = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE,
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PDC_CHIP0_OFS = 0xC0000, /* offset of chip #0 */
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PDC_20621_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
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(1<<23),
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board_20621 = 0, /* FastTrak S150 SX4 */
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PDC_RESET = (1 << 11), /* HDMA reset */
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PDC_MAX_HDMA = 32,
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PDC_HDMA_Q_MASK = (PDC_MAX_HDMA - 1),
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PDC_DIMM0_SPD_DEV_ADDRESS = 0x50,
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PDC_DIMM1_SPD_DEV_ADDRESS = 0x51,
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PDC_MAX_DIMM_MODULE = 0x02,
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PDC_I2C_CONTROL_OFFSET = 0x48,
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PDC_I2C_ADDR_DATA_OFFSET = 0x4C,
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PDC_DIMM0_CONTROL_OFFSET = 0x80,
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PDC_DIMM1_CONTROL_OFFSET = 0x84,
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PDC_SDRAM_CONTROL_OFFSET = 0x88,
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PDC_I2C_WRITE = 0x00000000,
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2005-07-31 10:13:24 -07:00
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PDC_I2C_READ = 0x00000040,
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2005-04-16 15:20:36 -07:00
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PDC_I2C_START = 0x00000080,
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PDC_I2C_MASK_INT = 0x00000020,
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PDC_I2C_COMPLETE = 0x00010000,
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PDC_I2C_NO_ACK = 0x00100000,
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PDC_DIMM_SPD_SUBADDRESS_START = 0x00,
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PDC_DIMM_SPD_SUBADDRESS_END = 0x7F,
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PDC_DIMM_SPD_ROW_NUM = 3,
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PDC_DIMM_SPD_COLUMN_NUM = 4,
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PDC_DIMM_SPD_MODULE_ROW = 5,
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PDC_DIMM_SPD_TYPE = 11,
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2005-07-31 10:13:24 -07:00
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PDC_DIMM_SPD_FRESH_RATE = 12,
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PDC_DIMM_SPD_BANK_NUM = 17,
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2005-04-16 15:20:36 -07:00
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PDC_DIMM_SPD_CAS_LATENCY = 18,
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2005-07-31 10:13:24 -07:00
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PDC_DIMM_SPD_ATTRIBUTE = 21,
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2005-04-16 15:20:36 -07:00
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PDC_DIMM_SPD_ROW_PRE_CHARGE = 27,
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2005-07-31 10:13:24 -07:00
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PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28,
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2005-04-16 15:20:36 -07:00
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PDC_DIMM_SPD_RAS_CAS_DELAY = 29,
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PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30,
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PDC_DIMM_SPD_SYSTEM_FREQ = 126,
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2005-07-31 10:13:24 -07:00
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PDC_CTL_STATUS = 0x08,
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2005-04-16 15:20:36 -07:00
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PDC_DIMM_WINDOW_CTLR = 0x0C,
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PDC_TIME_CONTROL = 0x3C,
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PDC_TIME_PERIOD = 0x40,
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PDC_TIME_COUNTER = 0x44,
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PDC_GENERAL_CTLR = 0x484,
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PCI_PLL_INIT = 0x8A531824,
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PCI_X_TCOUNT = 0xEE1E5CFF
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};
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struct pdc_port_priv {
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u8 dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512];
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u8 *pkt;
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dma_addr_t pkt_dma;
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};
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struct pdc_host_priv {
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2005-10-20 22:46:02 -07:00
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void __iomem *dimm_mmio;
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2005-04-16 15:20:36 -07:00
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unsigned int doing_hdma;
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unsigned int hdma_prod;
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unsigned int hdma_cons;
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struct {
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struct ata_queued_cmd *qc;
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unsigned int seq;
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unsigned long pkt_ofs;
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} hdma[32];
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};
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static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
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static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
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static void pdc_eng_timeout(struct ata_port *ap);
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static void pdc_20621_phy_reset (struct ata_port *ap);
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static int pdc_port_start(struct ata_port *ap);
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static void pdc_port_stop(struct ata_port *ap);
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static void pdc20621_qc_prep(struct ata_queued_cmd *qc);
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2005-10-22 11:27:05 -07:00
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static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
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static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
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2005-04-16 15:20:36 -07:00
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static void pdc20621_host_stop(struct ata_host_set *host_set);
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static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe);
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static int pdc20621_detect_dimm(struct ata_probe_ent *pe);
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2005-07-31 10:13:24 -07:00
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static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe,
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2005-04-16 15:20:36 -07:00
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u32 device, u32 subaddr, u32 *pdata);
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static int pdc20621_prog_dimm0(struct ata_probe_ent *pe);
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static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe);
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#ifdef ATA_VERBOSE_DEBUG
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2005-07-31 10:13:24 -07:00
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static void pdc20621_get_from_dimm(struct ata_probe_ent *pe,
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2005-04-16 15:20:36 -07:00
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void *psource, u32 offset, u32 size);
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#endif
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2005-07-31 10:13:24 -07:00
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static void pdc20621_put_to_dimm(struct ata_probe_ent *pe,
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2005-04-16 15:20:36 -07:00
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void *psource, u32 offset, u32 size);
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static void pdc20621_irq_clear(struct ata_port *ap);
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static int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc);
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2005-11-06 22:59:37 -07:00
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static struct scsi_host_template pdc_sata_sht = {
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2005-04-16 15:20:36 -07:00
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.eh_strategy_handler = ata_scsi_error,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_MAX_PRD,
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.max_sectors = ATA_MAX_SECTORS,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.bios_param = ata_std_bios_param,
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};
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2005-10-22 11:27:05 -07:00
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static const struct ata_port_operations pdc_20621_ops = {
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2005-04-16 15:20:36 -07:00
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.port_disable = ata_port_disable,
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.tf_load = pdc_tf_load_mmio,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = pdc_exec_command_mmio,
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.dev_select = ata_std_dev_select,
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.phy_reset = pdc_20621_phy_reset,
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.qc_prep = pdc20621_qc_prep,
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.qc_issue = pdc20621_qc_issue_prot,
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.eng_timeout = pdc_eng_timeout,
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.irq_handler = pdc20621_interrupt,
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.irq_clear = pdc20621_irq_clear,
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.port_start = pdc_port_start,
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.port_stop = pdc_port_stop,
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.host_stop = pdc20621_host_stop,
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};
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2005-11-28 02:06:23 -07:00
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static const struct ata_port_info pdc_port_info[] = {
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2005-04-16 15:20:36 -07:00
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/* board_20621 */
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{
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.sht = &pdc_sata_sht,
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.host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
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2005-12-13 00:29:45 -07:00
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ATA_FLAG_SRST | ATA_FLAG_MMIO |
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ATA_FLAG_NO_ATAPI,
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2005-04-16 15:20:36 -07:00
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x7f, /* udma0-6 ; FIXME */
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.port_ops = &pdc_20621_ops,
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},
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};
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2005-11-10 09:04:11 -07:00
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static const struct pci_device_id pdc_sata_pci_tbl[] = {
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2005-04-16 15:20:36 -07:00
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{ PCI_VENDOR_ID_PROMISE, 0x6622, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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board_20621 },
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{ } /* terminate list */
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};
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static struct pci_driver pdc_sata_pci_driver = {
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.name = DRV_NAME,
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.id_table = pdc_sata_pci_tbl,
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.probe = pdc_sata_init_one,
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.remove = ata_pci_remove_one,
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};
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static void pdc20621_host_stop(struct ata_host_set *host_set)
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{
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2005-08-30 02:42:52 -07:00
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struct pci_dev *pdev = to_pci_dev(host_set->dev);
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2005-04-16 15:20:36 -07:00
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struct pdc_host_priv *hpriv = host_set->private_data;
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2005-10-20 22:46:02 -07:00
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void __iomem *dimm_mmio = hpriv->dimm_mmio;
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2005-04-16 15:20:36 -07:00
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2005-08-30 02:42:52 -07:00
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pci_iounmap(pdev, dimm_mmio);
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2005-04-16 15:20:36 -07:00
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kfree(hpriv);
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2005-05-26 18:54:27 -07:00
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2005-08-30 02:42:52 -07:00
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pci_iounmap(pdev, host_set->mmio_base);
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2005-04-16 15:20:36 -07:00
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}
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static int pdc_port_start(struct ata_port *ap)
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{
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struct device *dev = ap->host_set->dev;
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struct pdc_port_priv *pp;
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int rc;
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rc = ata_port_start(ap);
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if (rc)
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return rc;
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pp = kmalloc(sizeof(*pp), GFP_KERNEL);
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if (!pp) {
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rc = -ENOMEM;
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goto err_out;
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}
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memset(pp, 0, sizeof(*pp));
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pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
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if (!pp->pkt) {
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rc = -ENOMEM;
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goto err_out_kfree;
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}
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ap->private_data = pp;
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return 0;
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err_out_kfree:
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kfree(pp);
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err_out:
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ata_port_stop(ap);
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return rc;
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}
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static void pdc_port_stop(struct ata_port *ap)
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{
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struct device *dev = ap->host_set->dev;
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|
|
struct pdc_port_priv *pp = ap->private_data;
|
|
|
|
|
|
|
|
ap->private_data = NULL;
|
|
|
|
dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
|
|
|
|
kfree(pp);
|
|
|
|
ata_port_stop(ap);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void pdc_20621_phy_reset (struct ata_port *ap)
|
|
|
|
{
|
|
|
|
VPRINTK("ENTER\n");
|
|
|
|
ap->cbl = ATA_CBL_SATA;
|
|
|
|
ata_port_probe(ap);
|
|
|
|
ata_bus_reset(ap);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf,
|
|
|
|
unsigned int portno,
|
|
|
|
unsigned int total_len)
|
|
|
|
{
|
|
|
|
u32 addr;
|
|
|
|
unsigned int dw = PDC_DIMM_APKT_PRD >> 2;
|
|
|
|
u32 *buf32 = (u32 *) buf;
|
|
|
|
|
|
|
|
/* output ATA packet S/G table */
|
|
|
|
addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
|
|
|
|
(PDC_DIMM_DATA_STEP * portno);
|
|
|
|
VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr);
|
|
|
|
buf32[dw] = cpu_to_le32(addr);
|
|
|
|
buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
|
|
|
|
|
|
|
|
VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
|
|
|
|
PDC_20621_DIMM_BASE +
|
|
|
|
(PDC_DIMM_WINDOW_STEP * portno) +
|
|
|
|
PDC_DIMM_APKT_PRD,
|
|
|
|
buf32[dw], buf32[dw + 1]);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void pdc20621_host_sg(struct ata_taskfile *tf, u8 *buf,
|
|
|
|
unsigned int portno,
|
|
|
|
unsigned int total_len)
|
|
|
|
{
|
|
|
|
u32 addr;
|
|
|
|
unsigned int dw = PDC_DIMM_HPKT_PRD >> 2;
|
|
|
|
u32 *buf32 = (u32 *) buf;
|
|
|
|
|
|
|
|
/* output Host DMA packet S/G table */
|
|
|
|
addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
|
|
|
|
(PDC_DIMM_DATA_STEP * portno);
|
|
|
|
|
|
|
|
buf32[dw] = cpu_to_le32(addr);
|
|
|
|
buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
|
|
|
|
|
|
|
|
VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
|
|
|
|
PDC_20621_DIMM_BASE +
|
|
|
|
(PDC_DIMM_WINDOW_STEP * portno) +
|
|
|
|
PDC_DIMM_HPKT_PRD,
|
|
|
|
buf32[dw], buf32[dw + 1]);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
|
|
|
|
unsigned int devno, u8 *buf,
|
|
|
|
unsigned int portno)
|
|
|
|
{
|
|
|
|
unsigned int i, dw;
|
|
|
|
u32 *buf32 = (u32 *) buf;
|
|
|
|
u8 dev_reg;
|
|
|
|
|
|
|
|
unsigned int dimm_sg = PDC_20621_DIMM_BASE +
|
|
|
|
(PDC_DIMM_WINDOW_STEP * portno) +
|
|
|
|
PDC_DIMM_APKT_PRD;
|
|
|
|
VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
|
|
|
|
|
|
|
|
i = PDC_DIMM_ATA_PKT;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set up ATA packet
|
|
|
|
*/
|
|
|
|
if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
|
|
|
|
buf[i++] = PDC_PKT_READ;
|
|
|
|
else if (tf->protocol == ATA_PROT_NODATA)
|
|
|
|
buf[i++] = PDC_PKT_NODATA;
|
|
|
|
else
|
|
|
|
buf[i++] = 0;
|
|
|
|
buf[i++] = 0; /* reserved */
|
|
|
|
buf[i++] = portno + 1; /* seq. id */
|
|
|
|
buf[i++] = 0xff; /* delay seq. id */
|
|
|
|
|
|
|
|
/* dimm dma S/G, and next-pkt */
|
|
|
|
dw = i >> 2;
|
|
|
|
if (tf->protocol == ATA_PROT_NODATA)
|
|
|
|
buf32[dw] = 0;
|
|
|
|
else
|
|
|
|
buf32[dw] = cpu_to_le32(dimm_sg);
|
|
|
|
buf32[dw + 1] = 0;
|
|
|
|
i += 8;
|
|
|
|
|
|
|
|
if (devno == 0)
|
|
|
|
dev_reg = ATA_DEVICE_OBS;
|
|
|
|
else
|
|
|
|
dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
|
|
|
|
|
|
|
|
/* select device */
|
|
|
|
buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
|
|
|
|
buf[i++] = dev_reg;
|
|
|
|
|
|
|
|
/* device control register */
|
|
|
|
buf[i++] = (1 << 5) | PDC_REG_DEVCTL;
|
|
|
|
buf[i++] = tf->ctl;
|
|
|
|
|
|
|
|
return i;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
|
|
|
|
unsigned int portno)
|
|
|
|
{
|
|
|
|
unsigned int dw;
|
|
|
|
u32 tmp, *buf32 = (u32 *) buf;
|
|
|
|
|
|
|
|
unsigned int host_sg = PDC_20621_DIMM_BASE +
|
|
|
|
(PDC_DIMM_WINDOW_STEP * portno) +
|
|
|
|
PDC_DIMM_HOST_PRD;
|
|
|
|
unsigned int dimm_sg = PDC_20621_DIMM_BASE +
|
|
|
|
(PDC_DIMM_WINDOW_STEP * portno) +
|
|
|
|
PDC_DIMM_HPKT_PRD;
|
|
|
|
VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
|
|
|
|
VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg);
|
|
|
|
|
|
|
|
dw = PDC_DIMM_HOST_PKT >> 2;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set up Host DMA packet
|
|
|
|
*/
|
|
|
|
if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
|
|
|
|
tmp = PDC_PKT_READ;
|
|
|
|
else
|
|
|
|
tmp = 0;
|
|
|
|
tmp |= ((portno + 1 + 4) << 16); /* seq. id */
|
|
|
|
tmp |= (0xff << 24); /* delay seq. id */
|
|
|
|
buf32[dw + 0] = cpu_to_le32(tmp);
|
|
|
|
buf32[dw + 1] = cpu_to_le32(host_sg);
|
|
|
|
buf32[dw + 2] = cpu_to_le32(dimm_sg);
|
|
|
|
buf32[dw + 3] = 0;
|
|
|
|
|
|
|
|
VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
|
|
|
|
PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) +
|
|
|
|
PDC_DIMM_HOST_PKT,
|
|
|
|
buf32[dw + 0],
|
|
|
|
buf32[dw + 1],
|
|
|
|
buf32[dw + 2],
|
|
|
|
buf32[dw + 3]);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pdc20621_dma_prep(struct ata_queued_cmd *qc)
|
|
|
|
{
|
2005-10-05 04:13:30 -07:00
|
|
|
struct scatterlist *sg;
|
2005-04-16 15:20:36 -07:00
|
|
|
struct ata_port *ap = qc->ap;
|
|
|
|
struct pdc_port_priv *pp = ap->private_data;
|
2005-08-30 02:18:18 -07:00
|
|
|
void __iomem *mmio = ap->host_set->mmio_base;
|
2005-04-16 15:20:36 -07:00
|
|
|
struct pdc_host_priv *hpriv = ap->host_set->private_data;
|
2005-08-30 02:18:18 -07:00
|
|
|
void __iomem *dimm_mmio = hpriv->dimm_mmio;
|
2005-04-16 15:20:36 -07:00
|
|
|
unsigned int portno = ap->port_no;
|
2005-10-05 04:13:30 -07:00
|
|
|
unsigned int i, idx, total_len = 0, sgt_len;
|
2005-04-16 15:20:36 -07:00
|
|
|
u32 *buf = (u32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ];
|
|
|
|
|
|
|
|
assert(qc->flags & ATA_QCFLAG_DMAMAP);
|
|
|
|
|
|
|
|
VPRINTK("ata%u: ENTER\n", ap->id);
|
|
|
|
|
|
|
|
/* hard-code chip #0 */
|
|
|
|
mmio += PDC_CHIP0_OFS;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Build S/G table
|
|
|
|
*/
|
|
|
|
idx = 0;
|
2005-10-05 04:13:30 -07:00
|
|
|
ata_for_each_sg(sg, qc) {
|
|
|
|
buf[idx++] = cpu_to_le32(sg_dma_address(sg));
|
|
|
|
buf[idx++] = cpu_to_le32(sg_dma_len(sg));
|
|
|
|
total_len += sg_dma_len(sg);
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT);
|
|
|
|
sgt_len = idx * 4;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Build ATA, host DMA packets
|
|
|
|
*/
|
|
|
|
pdc20621_host_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
|
|
|
|
pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno);
|
|
|
|
|
|
|
|
pdc20621_ata_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
|
|
|
|
i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
|
|
|
|
|
|
|
|
if (qc->tf.flags & ATA_TFLAG_LBA48)
|
|
|
|
i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
|
|
|
|
else
|
|
|
|
i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
|
|
|
|
|
|
|
|
pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
|
|
|
|
|
|
|
|
/* copy three S/G tables and two packets to DIMM MMIO window */
|
|
|
|
memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
|
|
|
|
&pp->dimm_buf, PDC_DIMM_HEADER_SZ);
|
|
|
|
memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) +
|
|
|
|
PDC_DIMM_HOST_PRD,
|
|
|
|
&pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len);
|
|
|
|
|
|
|
|
/* force host FIFO dump */
|
|
|
|
writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
|
|
|
|
|
|
|
|
readl(dimm_mmio); /* MMIO PCI posting flush */
|
|
|
|
|
|
|
|
VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pdc20621_nodata_prep(struct ata_queued_cmd *qc)
|
|
|
|
{
|
|
|
|
struct ata_port *ap = qc->ap;
|
|
|
|
struct pdc_port_priv *pp = ap->private_data;
|
2005-08-30 02:18:18 -07:00
|
|
|
void __iomem *mmio = ap->host_set->mmio_base;
|
2005-04-16 15:20:36 -07:00
|
|
|
struct pdc_host_priv *hpriv = ap->host_set->private_data;
|
2005-08-30 02:18:18 -07:00
|
|
|
void __iomem *dimm_mmio = hpriv->dimm_mmio;
|
2005-04-16 15:20:36 -07:00
|
|
|
unsigned int portno = ap->port_no;
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
VPRINTK("ata%u: ENTER\n", ap->id);
|
|
|
|
|
|
|
|
/* hard-code chip #0 */
|
|
|
|
mmio += PDC_CHIP0_OFS;
|
|
|
|
|
|
|
|
i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
|
|
|
|
|
|
|
|
if (qc->tf.flags & ATA_TFLAG_LBA48)
|
|
|
|
i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
|
|
|
|
else
|
|
|
|
i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
|
|
|
|
|
|
|
|
pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
|
|
|
|
|
|
|
|
/* copy three S/G tables and two packets to DIMM MMIO window */
|
|
|
|
memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
|
|
|
|
&pp->dimm_buf, PDC_DIMM_HEADER_SZ);
|
|
|
|
|
|
|
|
/* force host FIFO dump */
|
|
|
|
writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
|
|
|
|
|
|
|
|
readl(dimm_mmio); /* MMIO PCI posting flush */
|
|
|
|
|
|
|
|
VPRINTK("ata pkt buf ofs %u, mmio copied\n", i);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pdc20621_qc_prep(struct ata_queued_cmd *qc)
|
|
|
|
{
|
|
|
|
switch (qc->tf.protocol) {
|
|
|
|
case ATA_PROT_DMA:
|
|
|
|
pdc20621_dma_prep(qc);
|
|
|
|
break;
|
|
|
|
case ATA_PROT_NODATA:
|
|
|
|
pdc20621_nodata_prep(qc);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __pdc20621_push_hdma(struct ata_queued_cmd *qc,
|
|
|
|
unsigned int seq,
|
|
|
|
u32 pkt_ofs)
|
|
|
|
{
|
|
|
|
struct ata_port *ap = qc->ap;
|
|
|
|
struct ata_host_set *host_set = ap->host_set;
|
2005-08-30 02:18:18 -07:00
|
|
|
void __iomem *mmio = host_set->mmio_base;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
/* hard-code chip #0 */
|
|
|
|
mmio += PDC_CHIP0_OFS;
|
|
|
|
|
|
|
|
writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
|
|
|
|
readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
|
|
|
|
|
|
|
|
writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
|
|
|
|
readl(mmio + PDC_HDMA_PKT_SUBMIT); /* flush */
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pdc20621_push_hdma(struct ata_queued_cmd *qc,
|
|
|
|
unsigned int seq,
|
|
|
|
u32 pkt_ofs)
|
|
|
|
{
|
|
|
|
struct ata_port *ap = qc->ap;
|
|
|
|
struct pdc_host_priv *pp = ap->host_set->private_data;
|
|
|
|
unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK;
|
|
|
|
|
|
|
|
if (!pp->doing_hdma) {
|
|
|
|
__pdc20621_push_hdma(qc, seq, pkt_ofs);
|
|
|
|
pp->doing_hdma = 1;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
pp->hdma[idx].qc = qc;
|
|
|
|
pp->hdma[idx].seq = seq;
|
|
|
|
pp->hdma[idx].pkt_ofs = pkt_ofs;
|
|
|
|
pp->hdma_prod++;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pdc20621_pop_hdma(struct ata_queued_cmd *qc)
|
|
|
|
{
|
|
|
|
struct ata_port *ap = qc->ap;
|
|
|
|
struct pdc_host_priv *pp = ap->host_set->private_data;
|
|
|
|
unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK;
|
|
|
|
|
|
|
|
/* if nothing on queue, we're done */
|
|
|
|
if (pp->hdma_prod == pp->hdma_cons) {
|
|
|
|
pp->doing_hdma = 0;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
__pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq,
|
|
|
|
pp->hdma[idx].pkt_ofs);
|
|
|
|
pp->hdma_cons++;
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef ATA_VERBOSE_DEBUG
|
|
|
|
static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
|
|
|
|
{
|
|
|
|
struct ata_port *ap = qc->ap;
|
|
|
|
unsigned int port_no = ap->port_no;
|
|
|
|
struct pdc_host_priv *hpriv = ap->host_set->private_data;
|
|
|
|
void *dimm_mmio = hpriv->dimm_mmio;
|
|
|
|
|
|
|
|
dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
|
|
|
|
dimm_mmio += PDC_DIMM_HOST_PKT;
|
|
|
|
|
|
|
|
printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));
|
|
|
|
printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));
|
|
|
|
printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));
|
|
|
|
printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { }
|
|
|
|
#endif /* ATA_VERBOSE_DEBUG */
|
|
|
|
|
|
|
|
static void pdc20621_packet_start(struct ata_queued_cmd *qc)
|
|
|
|
{
|
|
|
|
struct ata_port *ap = qc->ap;
|
|
|
|
struct ata_host_set *host_set = ap->host_set;
|
|
|
|
unsigned int port_no = ap->port_no;
|
2005-08-30 02:18:18 -07:00
|
|
|
void __iomem *mmio = host_set->mmio_base;
|
2005-04-16 15:20:36 -07:00
|
|
|
unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
|
|
|
|
u8 seq = (u8) (port_no + 1);
|
|
|
|
unsigned int port_ofs;
|
|
|
|
|
|
|
|
/* hard-code chip #0 */
|
|
|
|
mmio += PDC_CHIP0_OFS;
|
|
|
|
|
|
|
|
VPRINTK("ata%u: ENTER\n", ap->id);
|
|
|
|
|
|
|
|
wmb(); /* flush PRD, pkt writes */
|
|
|
|
|
|
|
|
port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
|
|
|
|
|
|
|
|
/* if writing, we (1) DMA to DIMM, then (2) do ATA command */
|
|
|
|
if (rw && qc->tf.protocol == ATA_PROT_DMA) {
|
|
|
|
seq += 4;
|
|
|
|
|
|
|
|
pdc20621_dump_hdma(qc);
|
|
|
|
pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT);
|
|
|
|
VPRINTK("queued ofs 0x%x (%u), seq %u\n",
|
|
|
|
port_ofs + PDC_DIMM_HOST_PKT,
|
|
|
|
port_ofs + PDC_DIMM_HOST_PKT,
|
|
|
|
seq);
|
|
|
|
} else {
|
|
|
|
writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
|
|
|
|
readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
|
|
|
|
|
|
|
|
writel(port_ofs + PDC_DIMM_ATA_PKT,
|
2005-10-20 22:46:02 -07:00
|
|
|
(void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
|
|
|
|
readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
|
2005-04-16 15:20:36 -07:00
|
|
|
VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
|
|
|
|
port_ofs + PDC_DIMM_ATA_PKT,
|
|
|
|
port_ofs + PDC_DIMM_ATA_PKT,
|
|
|
|
seq);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc)
|
|
|
|
{
|
|
|
|
switch (qc->tf.protocol) {
|
|
|
|
case ATA_PROT_DMA:
|
|
|
|
case ATA_PROT_NODATA:
|
|
|
|
pdc20621_packet_start(qc);
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
case ATA_PROT_ATAPI_DMA:
|
|
|
|
BUG();
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ata_qc_issue_prot(qc);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline unsigned int pdc20621_host_intr( struct ata_port *ap,
|
|
|
|
struct ata_queued_cmd *qc,
|
|
|
|
unsigned int doing_hdma,
|
2005-08-30 02:18:18 -07:00
|
|
|
void __iomem *mmio)
|
2005-04-16 15:20:36 -07:00
|
|
|
{
|
|
|
|
unsigned int port_no = ap->port_no;
|
|
|
|
unsigned int port_ofs =
|
|
|
|
PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
|
|
|
|
u8 status;
|
|
|
|
unsigned int handled = 0;
|
|
|
|
|
|
|
|
VPRINTK("ENTER\n");
|
|
|
|
|
|
|
|
if ((qc->tf.protocol == ATA_PROT_DMA) && /* read */
|
|
|
|
(!(qc->tf.flags & ATA_TFLAG_WRITE))) {
|
|
|
|
|
|
|
|
/* step two - DMA from DIMM to host */
|
|
|
|
if (doing_hdma) {
|
|
|
|
VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->id,
|
|
|
|
readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
|
|
|
|
/* get drive status; clear intr; complete txn */
|
2005-12-05 00:38:02 -07:00
|
|
|
qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
|
|
|
|
ata_qc_complete(qc);
|
2005-04-16 15:20:36 -07:00
|
|
|
pdc20621_pop_hdma(qc);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* step one - exec ATA command */
|
|
|
|
else {
|
|
|
|
u8 seq = (u8) (port_no + 1 + 4);
|
|
|
|
VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->id,
|
|
|
|
readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
|
|
|
|
|
|
|
|
/* submit hdma pkt */
|
|
|
|
pdc20621_dump_hdma(qc);
|
|
|
|
pdc20621_push_hdma(qc, seq,
|
|
|
|
port_ofs + PDC_DIMM_HOST_PKT);
|
|
|
|
}
|
|
|
|
handled = 1;
|
|
|
|
|
|
|
|
} else if (qc->tf.protocol == ATA_PROT_DMA) { /* write */
|
|
|
|
|
|
|
|
/* step one - DMA from host to DIMM */
|
|
|
|
if (doing_hdma) {
|
|
|
|
u8 seq = (u8) (port_no + 1);
|
|
|
|
VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->id,
|
|
|
|
readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
|
|
|
|
|
|
|
|
/* submit ata pkt */
|
|
|
|
writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
|
|
|
|
readl(mmio + PDC_20621_SEQCTL + (seq * 4));
|
|
|
|
writel(port_ofs + PDC_DIMM_ATA_PKT,
|
2005-10-20 22:46:02 -07:00
|
|
|
(void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
|
|
|
|
readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
/* step two - execute ATA command */
|
|
|
|
else {
|
|
|
|
VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->id,
|
|
|
|
readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
|
|
|
|
/* get drive status; clear intr; complete txn */
|
2005-12-05 00:38:02 -07:00
|
|
|
qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
|
|
|
|
ata_qc_complete(qc);
|
2005-04-16 15:20:36 -07:00
|
|
|
pdc20621_pop_hdma(qc);
|
|
|
|
}
|
|
|
|
handled = 1;
|
|
|
|
|
|
|
|
/* command completion, but no data xfer */
|
|
|
|
} else if (qc->tf.protocol == ATA_PROT_NODATA) {
|
|
|
|
|
|
|
|
status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
|
|
|
|
DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
|
2005-12-05 00:38:02 -07:00
|
|
|
qc->err_mask |= ac_err_mask(status);
|
|
|
|
ata_qc_complete(qc);
|
2005-04-16 15:20:36 -07:00
|
|
|
handled = 1;
|
|
|
|
|
|
|
|
} else {
|
|
|
|
ap->stats.idle_irq++;
|
|
|
|
}
|
|
|
|
|
|
|
|
return handled;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pdc20621_irq_clear(struct ata_port *ap)
|
|
|
|
{
|
|
|
|
struct ata_host_set *host_set = ap->host_set;
|
2005-08-30 02:18:18 -07:00
|
|
|
void __iomem *mmio = host_set->mmio_base;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
mmio += PDC_CHIP0_OFS;
|
|
|
|
|
|
|
|
readl(mmio + PDC_20621_SEQMASK);
|
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
struct ata_host_set *host_set = dev_instance;
|
|
|
|
struct ata_port *ap;
|
|
|
|
u32 mask = 0;
|
|
|
|
unsigned int i, tmp, port_no;
|
|
|
|
unsigned int handled = 0;
|
2005-08-30 02:18:18 -07:00
|
|
|
void __iomem *mmio_base;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
VPRINTK("ENTER\n");
|
|
|
|
|
|
|
|
if (!host_set || !host_set->mmio_base) {
|
|
|
|
VPRINTK("QUICK EXIT\n");
|
|
|
|
return IRQ_NONE;
|
|
|
|
}
|
|
|
|
|
|
|
|
mmio_base = host_set->mmio_base;
|
|
|
|
|
|
|
|
/* reading should also clear interrupts */
|
|
|
|
mmio_base += PDC_CHIP0_OFS;
|
|
|
|
mask = readl(mmio_base + PDC_20621_SEQMASK);
|
|
|
|
VPRINTK("mask == 0x%x\n", mask);
|
|
|
|
|
|
|
|
if (mask == 0xffffffff) {
|
|
|
|
VPRINTK("QUICK EXIT 2\n");
|
|
|
|
return IRQ_NONE;
|
|
|
|
}
|
|
|
|
mask &= 0xffff; /* only 16 tags possible */
|
|
|
|
if (!mask) {
|
|
|
|
VPRINTK("QUICK EXIT 3\n");
|
|
|
|
return IRQ_NONE;
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_lock(&host_set->lock);
|
|
|
|
|
|
|
|
for (i = 1; i < 9; i++) {
|
|
|
|
port_no = i - 1;
|
|
|
|
if (port_no > 3)
|
|
|
|
port_no -= 4;
|
|
|
|
if (port_no >= host_set->n_ports)
|
|
|
|
ap = NULL;
|
|
|
|
else
|
|
|
|
ap = host_set->ports[port_no];
|
|
|
|
tmp = mask & (1 << i);
|
|
|
|
VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp);
|
2005-08-21 22:59:24 -07:00
|
|
|
if (tmp && ap &&
|
|
|
|
!(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
|
2005-04-16 15:20:36 -07:00
|
|
|
struct ata_queued_cmd *qc;
|
|
|
|
|
|
|
|
qc = ata_qc_from_tag(ap, ap->active_tag);
|
|
|
|
if (qc && (!(qc->tf.ctl & ATA_NIEN)))
|
|
|
|
handled += pdc20621_host_intr(ap, qc, (i > 4),
|
|
|
|
mmio_base);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock(&host_set->lock);
|
|
|
|
|
|
|
|
VPRINTK("mask == 0x%x\n", mask);
|
|
|
|
|
|
|
|
VPRINTK("EXIT\n");
|
|
|
|
|
|
|
|
return IRQ_RETVAL(handled);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pdc_eng_timeout(struct ata_port *ap)
|
|
|
|
{
|
|
|
|
u8 drv_stat;
|
2005-08-25 19:01:20 -07:00
|
|
|
struct ata_host_set *host_set = ap->host_set;
|
2005-04-16 15:20:36 -07:00
|
|
|
struct ata_queued_cmd *qc;
|
2005-08-25 19:01:20 -07:00
|
|
|
unsigned long flags;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
DPRINTK("ENTER\n");
|
|
|
|
|
2005-08-25 19:01:20 -07:00
|
|
|
spin_lock_irqsave(&host_set->lock, flags);
|
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
qc = ata_qc_from_tag(ap, ap->active_tag);
|
|
|
|
if (!qc) {
|
|
|
|
printk(KERN_ERR "ata%u: BUG: timeout without command\n",
|
|
|
|
ap->id);
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* hack alert! We cannot use the supplied completion
|
|
|
|
* function from inside the ->eh_strategy_handler() thread.
|
|
|
|
* libata is the only user of ->eh_strategy_handler() in
|
|
|
|
* any kernel, so the default scsi_done() assumes it is
|
|
|
|
* not being called from the SCSI EH.
|
|
|
|
*/
|
|
|
|
qc->scsidone = scsi_finish_command;
|
|
|
|
|
|
|
|
switch (qc->tf.protocol) {
|
|
|
|
case ATA_PROT_DMA:
|
|
|
|
case ATA_PROT_NODATA:
|
|
|
|
printk(KERN_ERR "ata%u: command timeout\n", ap->id);
|
2005-12-05 00:38:02 -07:00
|
|
|
qc->err_mask |= __ac_err_mask(ata_wait_idle(ap));
|
|
|
|
ata_qc_complete(qc);
|
2005-04-16 15:20:36 -07:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
|
|
|
|
|
|
|
|
printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
|
|
|
|
ap->id, qc->tf.command, drv_stat);
|
|
|
|
|
2005-12-05 00:38:02 -07:00
|
|
|
qc->err_mask |= ac_err_mask(drv_stat);
|
|
|
|
ata_qc_complete(qc);
|
2005-04-16 15:20:36 -07:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
out:
|
2005-08-25 19:01:20 -07:00
|
|
|
spin_unlock_irqrestore(&host_set->lock, flags);
|
2005-04-16 15:20:36 -07:00
|
|
|
DPRINTK("EXIT\n");
|
|
|
|
}
|
|
|
|
|
2005-10-22 11:27:05 -07:00
|
|
|
static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
|
2005-04-16 15:20:36 -07:00
|
|
|
{
|
|
|
|
WARN_ON (tf->protocol == ATA_PROT_DMA ||
|
|
|
|
tf->protocol == ATA_PROT_NODATA);
|
|
|
|
ata_tf_load(ap, tf);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-10-22 11:27:05 -07:00
|
|
|
static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
|
2005-04-16 15:20:36 -07:00
|
|
|
{
|
|
|
|
WARN_ON (tf->protocol == ATA_PROT_DMA ||
|
|
|
|
tf->protocol == ATA_PROT_NODATA);
|
|
|
|
ata_exec_command(ap, tf);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void pdc_sata_setup_port(struct ata_ioports *port, unsigned long base)
|
|
|
|
{
|
|
|
|
port->cmd_addr = base;
|
|
|
|
port->data_addr = base;
|
|
|
|
port->feature_addr =
|
|
|
|
port->error_addr = base + 0x4;
|
|
|
|
port->nsect_addr = base + 0x8;
|
|
|
|
port->lbal_addr = base + 0xc;
|
|
|
|
port->lbam_addr = base + 0x10;
|
|
|
|
port->lbah_addr = base + 0x14;
|
|
|
|
port->device_addr = base + 0x18;
|
|
|
|
port->command_addr =
|
|
|
|
port->status_addr = base + 0x1c;
|
|
|
|
port->altstatus_addr =
|
|
|
|
port->ctl_addr = base + 0x38;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
#ifdef ATA_VERBOSE_DEBUG
|
2005-07-31 10:13:24 -07:00
|
|
|
static void pdc20621_get_from_dimm(struct ata_probe_ent *pe, void *psource,
|
2005-04-16 15:20:36 -07:00
|
|
|
u32 offset, u32 size)
|
|
|
|
{
|
|
|
|
u32 window_size;
|
|
|
|
u16 idx;
|
|
|
|
u8 page_mask;
|
|
|
|
long dist;
|
2005-08-30 02:18:18 -07:00
|
|
|
void __iomem *mmio = pe->mmio_base;
|
2005-04-16 15:20:36 -07:00
|
|
|
struct pdc_host_priv *hpriv = pe->private_data;
|
2005-08-30 02:18:18 -07:00
|
|
|
void __iomem *dimm_mmio = hpriv->dimm_mmio;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
/* hard-code chip #0 */
|
|
|
|
mmio += PDC_CHIP0_OFS;
|
|
|
|
|
2005-07-31 10:13:24 -07:00
|
|
|
page_mask = 0x00;
|
|
|
|
window_size = 0x2000 * 4; /* 32K byte uchar size */
|
|
|
|
idx = (u16) (offset / window_size);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
writel(0x01, mmio + PDC_GENERAL_CTLR);
|
|
|
|
readl(mmio + PDC_GENERAL_CTLR);
|
|
|
|
writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
|
|
|
|
readl(mmio + PDC_DIMM_WINDOW_CTLR);
|
|
|
|
|
|
|
|
offset -= (idx * window_size);
|
|
|
|
idx++;
|
2005-07-31 10:13:24 -07:00
|
|
|
dist = ((long) (window_size - (offset + size))) >= 0 ? size :
|
2005-04-16 15:20:36 -07:00
|
|
|
(long) (window_size - offset);
|
2005-07-31 10:13:24 -07:00
|
|
|
memcpy_fromio((char *) psource, (char *) (dimm_mmio + offset / 4),
|
2005-04-16 15:20:36 -07:00
|
|
|
dist);
|
|
|
|
|
2005-07-31 10:13:24 -07:00
|
|
|
psource += dist;
|
2005-04-16 15:20:36 -07:00
|
|
|
size -= dist;
|
|
|
|
for (; (long) size >= (long) window_size ;) {
|
|
|
|
writel(0x01, mmio + PDC_GENERAL_CTLR);
|
|
|
|
readl(mmio + PDC_GENERAL_CTLR);
|
|
|
|
writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
|
|
|
|
readl(mmio + PDC_DIMM_WINDOW_CTLR);
|
2005-07-31 10:13:24 -07:00
|
|
|
memcpy_fromio((char *) psource, (char *) (dimm_mmio),
|
2005-04-16 15:20:36 -07:00
|
|
|
window_size / 4);
|
|
|
|
psource += window_size;
|
|
|
|
size -= window_size;
|
|
|
|
idx ++;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (size) {
|
|
|
|
writel(0x01, mmio + PDC_GENERAL_CTLR);
|
|
|
|
readl(mmio + PDC_GENERAL_CTLR);
|
|
|
|
writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
|
|
|
|
readl(mmio + PDC_DIMM_WINDOW_CTLR);
|
2005-07-31 10:13:24 -07:00
|
|
|
memcpy_fromio((char *) psource, (char *) (dimm_mmio),
|
2005-04-16 15:20:36 -07:00
|
|
|
size / 4);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
2005-07-31 10:13:24 -07:00
|
|
|
static void pdc20621_put_to_dimm(struct ata_probe_ent *pe, void *psource,
|
2005-04-16 15:20:36 -07:00
|
|
|
u32 offset, u32 size)
|
|
|
|
{
|
|
|
|
u32 window_size;
|
|
|
|
u16 idx;
|
|
|
|
u8 page_mask;
|
|
|
|
long dist;
|
2005-08-30 02:18:18 -07:00
|
|
|
void __iomem *mmio = pe->mmio_base;
|
2005-04-16 15:20:36 -07:00
|
|
|
struct pdc_host_priv *hpriv = pe->private_data;
|
2005-08-30 02:18:18 -07:00
|
|
|
void __iomem *dimm_mmio = hpriv->dimm_mmio;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2005-07-31 10:13:24 -07:00
|
|
|
/* hard-code chip #0 */
|
2005-04-16 15:20:36 -07:00
|
|
|
mmio += PDC_CHIP0_OFS;
|
|
|
|
|
2005-07-31 10:13:24 -07:00
|
|
|
page_mask = 0x00;
|
|
|
|
window_size = 0x2000 * 4; /* 32K byte uchar size */
|
2005-04-16 15:20:36 -07:00
|
|
|
idx = (u16) (offset / window_size);
|
|
|
|
|
|
|
|
writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
|
|
|
|
readl(mmio + PDC_DIMM_WINDOW_CTLR);
|
2005-07-31 10:13:24 -07:00
|
|
|
offset -= (idx * window_size);
|
2005-04-16 15:20:36 -07:00
|
|
|
idx++;
|
|
|
|
dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size :
|
|
|
|
(long) (window_size - offset);
|
2005-10-20 22:46:02 -07:00
|
|
|
memcpy_toio(dimm_mmio + offset / 4, psource, dist);
|
2005-04-16 15:20:36 -07:00
|
|
|
writel(0x01, mmio + PDC_GENERAL_CTLR);
|
|
|
|
readl(mmio + PDC_GENERAL_CTLR);
|
|
|
|
|
2005-07-31 10:13:24 -07:00
|
|
|
psource += dist;
|
2005-04-16 15:20:36 -07:00
|
|
|
size -= dist;
|
|
|
|
for (; (long) size >= (long) window_size ;) {
|
|
|
|
writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
|
|
|
|
readl(mmio + PDC_DIMM_WINDOW_CTLR);
|
2005-10-20 22:46:02 -07:00
|
|
|
memcpy_toio(dimm_mmio, psource, window_size / 4);
|
2005-04-16 15:20:36 -07:00
|
|
|
writel(0x01, mmio + PDC_GENERAL_CTLR);
|
|
|
|
readl(mmio + PDC_GENERAL_CTLR);
|
|
|
|
psource += window_size;
|
|
|
|
size -= window_size;
|
|
|
|
idx ++;
|
|
|
|
}
|
2005-07-31 10:13:24 -07:00
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
if (size) {
|
|
|
|
writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
|
|
|
|
readl(mmio + PDC_DIMM_WINDOW_CTLR);
|
2005-10-20 22:46:02 -07:00
|
|
|
memcpy_toio(dimm_mmio, psource, size / 4);
|
2005-04-16 15:20:36 -07:00
|
|
|
writel(0x01, mmio + PDC_GENERAL_CTLR);
|
|
|
|
readl(mmio + PDC_GENERAL_CTLR);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-07-31 10:13:24 -07:00
|
|
|
static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe, u32 device,
|
2005-04-16 15:20:36 -07:00
|
|
|
u32 subaddr, u32 *pdata)
|
|
|
|
{
|
2005-08-30 02:18:18 -07:00
|
|
|
void __iomem *mmio = pe->mmio_base;
|
2005-04-16 15:20:36 -07:00
|
|
|
u32 i2creg = 0;
|
2005-07-31 10:13:24 -07:00
|
|
|
u32 status;
|
2005-04-16 15:20:36 -07:00
|
|
|
u32 count =0;
|
|
|
|
|
|
|
|
/* hard-code chip #0 */
|
|
|
|
mmio += PDC_CHIP0_OFS;
|
|
|
|
|
|
|
|
i2creg |= device << 24;
|
|
|
|
i2creg |= subaddr << 16;
|
|
|
|
|
|
|
|
/* Set the device and subaddress */
|
|
|
|
writel(i2creg, mmio + PDC_I2C_ADDR_DATA_OFFSET);
|
|
|
|
readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
|
|
|
|
|
|
|
|
/* Write Control to perform read operation, mask int */
|
2005-07-31 10:13:24 -07:00
|
|
|
writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
|
2005-04-16 15:20:36 -07:00
|
|
|
mmio + PDC_I2C_CONTROL_OFFSET);
|
|
|
|
|
|
|
|
for (count = 0; count <= 1000; count ++) {
|
|
|
|
status = readl(mmio + PDC_I2C_CONTROL_OFFSET);
|
|
|
|
if (status & PDC_I2C_COMPLETE) {
|
|
|
|
status = readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
|
|
|
|
break;
|
|
|
|
} else if (count == 1000)
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
*pdata = (status >> 8) & 0x000000ff;
|
2005-07-31 10:13:24 -07:00
|
|
|
return 1;
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static int pdc20621_detect_dimm(struct ata_probe_ent *pe)
|
|
|
|
{
|
|
|
|
u32 data=0 ;
|
2005-07-31 10:13:24 -07:00
|
|
|
if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
|
2005-04-16 15:20:36 -07:00
|
|
|
PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
|
|
|
|
if (data == 100)
|
|
|
|
return 100;
|
|
|
|
} else
|
|
|
|
return 0;
|
2005-07-31 10:13:24 -07:00
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
|
2005-07-31 10:13:24 -07:00
|
|
|
if(data <= 0x75)
|
2005-04-16 15:20:36 -07:00
|
|
|
return 133;
|
|
|
|
} else
|
|
|
|
return 0;
|
2005-07-31 10:13:24 -07:00
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static int pdc20621_prog_dimm0(struct ata_probe_ent *pe)
|
|
|
|
{
|
|
|
|
u32 spd0[50];
|
|
|
|
u32 data = 0;
|
|
|
|
int size, i;
|
2005-07-31 10:13:24 -07:00
|
|
|
u8 bdimmsize;
|
2005-08-30 02:18:18 -07:00
|
|
|
void __iomem *mmio = pe->mmio_base;
|
2005-04-16 15:20:36 -07:00
|
|
|
static const struct {
|
|
|
|
unsigned int reg;
|
|
|
|
unsigned int ofs;
|
|
|
|
} pdc_i2c_read_data [] = {
|
2005-07-31 10:13:24 -07:00
|
|
|
{ PDC_DIMM_SPD_TYPE, 11 },
|
2005-04-16 15:20:36 -07:00
|
|
|
{ PDC_DIMM_SPD_FRESH_RATE, 12 },
|
2005-07-31 10:13:24 -07:00
|
|
|
{ PDC_DIMM_SPD_COLUMN_NUM, 4 },
|
2005-04-16 15:20:36 -07:00
|
|
|
{ PDC_DIMM_SPD_ATTRIBUTE, 21 },
|
|
|
|
{ PDC_DIMM_SPD_ROW_NUM, 3 },
|
|
|
|
{ PDC_DIMM_SPD_BANK_NUM, 17 },
|
|
|
|
{ PDC_DIMM_SPD_MODULE_ROW, 5 },
|
|
|
|
{ PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 },
|
|
|
|
{ PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 },
|
|
|
|
{ PDC_DIMM_SPD_RAS_CAS_DELAY, 29 },
|
|
|
|
{ PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 },
|
2005-07-31 10:13:24 -07:00
|
|
|
{ PDC_DIMM_SPD_CAS_LATENCY, 18 },
|
2005-04-16 15:20:36 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
/* hard-code chip #0 */
|
|
|
|
mmio += PDC_CHIP0_OFS;
|
|
|
|
|
|
|
|
for(i=0; i<ARRAY_SIZE(pdc_i2c_read_data); i++)
|
|
|
|
pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
|
2005-07-31 10:13:24 -07:00
|
|
|
pdc_i2c_read_data[i].reg,
|
2005-04-16 15:20:36 -07:00
|
|
|
&spd0[pdc_i2c_read_data[i].ofs]);
|
2005-07-31 10:13:24 -07:00
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
|
2005-07-31 10:13:24 -07:00
|
|
|
data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
|
2005-04-16 15:20:36 -07:00
|
|
|
((((spd0[27] + 9) / 10) - 1) << 8) ;
|
2005-07-31 10:13:24 -07:00
|
|
|
data |= (((((spd0[29] > spd0[28])
|
|
|
|
? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10;
|
2005-04-16 15:20:36 -07:00
|
|
|
data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
|
2005-07-31 10:13:24 -07:00
|
|
|
|
|
|
|
if (spd0[18] & 0x08)
|
2005-04-16 15:20:36 -07:00
|
|
|
data |= ((0x03) << 14);
|
|
|
|
else if (spd0[18] & 0x04)
|
|
|
|
data |= ((0x02) << 14);
|
|
|
|
else if (spd0[18] & 0x01)
|
|
|
|
data |= ((0x01) << 14);
|
|
|
|
else
|
|
|
|
data |= (0 << 14);
|
|
|
|
|
2005-07-31 10:13:24 -07:00
|
|
|
/*
|
2005-04-16 15:20:36 -07:00
|
|
|
Calculate the size of bDIMMSize (power of 2) and
|
|
|
|
merge the DIMM size by program start/end address.
|
|
|
|
*/
|
|
|
|
|
|
|
|
bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
|
|
|
|
size = (1 << bdimmsize) >> 20; /* size = xxx(MB) */
|
|
|
|
data |= (((size / 16) - 1) << 16);
|
|
|
|
data |= (0 << 23);
|
|
|
|
data |= 8;
|
2005-07-31 10:13:24 -07:00
|
|
|
writel(data, mmio + PDC_DIMM0_CONTROL_OFFSET);
|
2005-04-16 15:20:36 -07:00
|
|
|
readl(mmio + PDC_DIMM0_CONTROL_OFFSET);
|
2005-07-31 10:13:24 -07:00
|
|
|
return size;
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe)
|
|
|
|
{
|
|
|
|
u32 data, spd0;
|
|
|
|
int error, i;
|
2005-08-30 02:18:18 -07:00
|
|
|
void __iomem *mmio = pe->mmio_base;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
/* hard-code chip #0 */
|
|
|
|
mmio += PDC_CHIP0_OFS;
|
|
|
|
|
|
|
|
/*
|
|
|
|
Set To Default : DIMM Module Global Control Register (0x022259F1)
|
|
|
|
DIMM Arbitration Disable (bit 20)
|
|
|
|
DIMM Data/Control Output Driving Selection (bit12 - bit15)
|
|
|
|
Refresh Enable (bit 17)
|
|
|
|
*/
|
|
|
|
|
2005-07-31 10:13:24 -07:00
|
|
|
data = 0x022259F1;
|
2005-04-16 15:20:36 -07:00
|
|
|
writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
|
|
|
|
readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
|
|
|
|
|
|
|
|
/* Turn on for ECC */
|
2005-07-31 10:13:24 -07:00
|
|
|
pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
|
2005-04-16 15:20:36 -07:00
|
|
|
PDC_DIMM_SPD_TYPE, &spd0);
|
|
|
|
if (spd0 == 0x02) {
|
|
|
|
data |= (0x01 << 16);
|
|
|
|
writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
|
|
|
|
readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
|
|
|
|
printk(KERN_ERR "Local DIMM ECC Enabled\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
/* DIMM Initialization Select/Enable (bit 18/19) */
|
|
|
|
data &= (~(1<<18));
|
|
|
|
data |= (1<<19);
|
|
|
|
writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
|
|
|
|
|
2005-07-31 10:13:24 -07:00
|
|
|
error = 1;
|
2005-04-16 15:20:36 -07:00
|
|
|
for (i = 1; i <= 10; i++) { /* polling ~5 secs */
|
|
|
|
data = readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
|
|
|
|
if (!(data & (1<<19))) {
|
|
|
|
error = 0;
|
2005-07-31 10:13:24 -07:00
|
|
|
break;
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
msleep(i*100);
|
|
|
|
}
|
|
|
|
return error;
|
|
|
|
}
|
2005-07-31 10:13:24 -07:00
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe)
|
|
|
|
{
|
2005-07-31 10:13:24 -07:00
|
|
|
int speed, size, length;
|
2005-04-16 15:20:36 -07:00
|
|
|
u32 addr,spd0,pci_status;
|
|
|
|
u32 tmp=0;
|
|
|
|
u32 time_period=0;
|
|
|
|
u32 tcount=0;
|
|
|
|
u32 ticks=0;
|
|
|
|
u32 clock=0;
|
|
|
|
u32 fparam=0;
|
2005-08-30 02:18:18 -07:00
|
|
|
void __iomem *mmio = pe->mmio_base;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
/* hard-code chip #0 */
|
|
|
|
mmio += PDC_CHIP0_OFS;
|
|
|
|
|
|
|
|
/* Initialize PLL based upon PCI Bus Frequency */
|
|
|
|
|
|
|
|
/* Initialize Time Period Register */
|
|
|
|
writel(0xffffffff, mmio + PDC_TIME_PERIOD);
|
|
|
|
time_period = readl(mmio + PDC_TIME_PERIOD);
|
|
|
|
VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);
|
|
|
|
|
|
|
|
/* Enable timer */
|
|
|
|
writel(0x00001a0, mmio + PDC_TIME_CONTROL);
|
|
|
|
readl(mmio + PDC_TIME_CONTROL);
|
|
|
|
|
|
|
|
/* Wait 3 seconds */
|
|
|
|
msleep(3000);
|
|
|
|
|
2005-07-31 10:13:24 -07:00
|
|
|
/*
|
2005-04-16 15:20:36 -07:00
|
|
|
When timer is enabled, counter is decreased every internal
|
|
|
|
clock cycle.
|
|
|
|
*/
|
|
|
|
|
|
|
|
tcount = readl(mmio + PDC_TIME_COUNTER);
|
|
|
|
VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount);
|
|
|
|
|
2005-07-31 10:13:24 -07:00
|
|
|
/*
|
2005-04-16 15:20:36 -07:00
|
|
|
If SX4 is on PCI-X bus, after 3 seconds, the timer counter
|
|
|
|
register should be >= (0xffffffff - 3x10^8).
|
|
|
|
*/
|
|
|
|
if(tcount >= PCI_X_TCOUNT) {
|
|
|
|
ticks = (time_period - tcount);
|
|
|
|
VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks);
|
2005-07-31 10:13:24 -07:00
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
clock = (ticks / 300000);
|
|
|
|
VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock);
|
2005-07-31 10:13:24 -07:00
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
clock = (clock * 33);
|
|
|
|
VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock);
|
|
|
|
|
|
|
|
/* PLL F Param (bit 22:16) */
|
|
|
|
fparam = (1400000 / clock) - 2;
|
|
|
|
VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam);
|
2005-07-31 10:13:24 -07:00
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
/* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
|
|
|
|
pci_status = (0x8a001824 | (fparam << 16));
|
|
|
|
} else
|
|
|
|
pci_status = PCI_PLL_INIT;
|
|
|
|
|
|
|
|
/* Initialize PLL. */
|
|
|
|
VPRINTK("pci_status: 0x%x\n", pci_status);
|
|
|
|
writel(pci_status, mmio + PDC_CTL_STATUS);
|
|
|
|
readl(mmio + PDC_CTL_STATUS);
|
|
|
|
|
2005-07-31 10:13:24 -07:00
|
|
|
/*
|
2005-04-16 15:20:36 -07:00
|
|
|
Read SPD of DIMM by I2C interface,
|
|
|
|
and program the DIMM Module Controller.
|
|
|
|
*/
|
|
|
|
if (!(speed = pdc20621_detect_dimm(pe))) {
|
2005-07-31 10:13:24 -07:00
|
|
|
printk(KERN_ERR "Detect Local DIMM Fail\n");
|
2005-04-16 15:20:36 -07:00
|
|
|
return 1; /* DIMM error */
|
|
|
|
}
|
|
|
|
VPRINTK("Local DIMM Speed = %d\n", speed);
|
|
|
|
|
2005-07-31 10:13:24 -07:00
|
|
|
/* Programming DIMM0 Module Control Register (index_CID0:80h) */
|
2005-04-16 15:20:36 -07:00
|
|
|
size = pdc20621_prog_dimm0(pe);
|
|
|
|
VPRINTK("Local DIMM Size = %dMB\n",size);
|
|
|
|
|
2005-07-31 10:13:24 -07:00
|
|
|
/* Programming DIMM Module Global Control Register (index_CID0:88h) */
|
2005-04-16 15:20:36 -07:00
|
|
|
if (pdc20621_prog_dimm_global(pe)) {
|
|
|
|
printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef ATA_VERBOSE_DEBUG
|
|
|
|
{
|
|
|
|
u8 test_parttern1[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ',
|
|
|
|
'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ',
|
|
|
|
'1','.','1','0',
|
|
|
|
'9','8','0','3','1','6','1','2',0,0};
|
|
|
|
u8 test_parttern2[40] = {0};
|
|
|
|
|
|
|
|
pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x10040, 40);
|
|
|
|
pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x40, 40);
|
|
|
|
|
|
|
|
pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x10040, 40);
|
|
|
|
pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
|
2005-07-31 10:13:24 -07:00
|
|
|
printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
|
2005-04-16 15:20:36 -07:00
|
|
|
test_parttern2[1], &(test_parttern2[2]));
|
2005-07-31 10:13:24 -07:00
|
|
|
pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x10040,
|
2005-04-16 15:20:36 -07:00
|
|
|
40);
|
2005-07-31 10:13:24 -07:00
|
|
|
printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
|
2005-04-16 15:20:36 -07:00
|
|
|
test_parttern2[1], &(test_parttern2[2]));
|
|
|
|
|
|
|
|
pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x40, 40);
|
|
|
|
pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
|
2005-07-31 10:13:24 -07:00
|
|
|
printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
|
2005-04-16 15:20:36 -07:00
|
|
|
test_parttern2[1], &(test_parttern2[2]));
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* ECC initiliazation. */
|
|
|
|
|
2005-07-31 10:13:24 -07:00
|
|
|
pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
|
2005-04-16 15:20:36 -07:00
|
|
|
PDC_DIMM_SPD_TYPE, &spd0);
|
|
|
|
if (spd0 == 0x02) {
|
|
|
|
VPRINTK("Start ECC initialization\n");
|
|
|
|
addr = 0;
|
|
|
|
length = size * 1024 * 1024;
|
|
|
|
while (addr < length) {
|
2005-07-31 10:13:24 -07:00
|
|
|
pdc20621_put_to_dimm(pe, (void *) &tmp, addr,
|
2005-04-16 15:20:36 -07:00
|
|
|
sizeof(u32));
|
|
|
|
addr += sizeof(u32);
|
|
|
|
}
|
|
|
|
VPRINTK("Finish ECC initialization\n");
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void pdc_20621_init(struct ata_probe_ent *pe)
|
|
|
|
{
|
|
|
|
u32 tmp;
|
2005-08-30 02:18:18 -07:00
|
|
|
void __iomem *mmio = pe->mmio_base;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
/* hard-code chip #0 */
|
|
|
|
mmio += PDC_CHIP0_OFS;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Select page 0x40 for our 32k DIMM window
|
|
|
|
*/
|
|
|
|
tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
|
|
|
|
tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */
|
|
|
|
writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Reset Host DMA
|
|
|
|
*/
|
|
|
|
tmp = readl(mmio + PDC_HDMA_CTLSTAT);
|
|
|
|
tmp |= PDC_RESET;
|
|
|
|
writel(tmp, mmio + PDC_HDMA_CTLSTAT);
|
|
|
|
readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
|
|
|
|
|
|
|
|
udelay(10);
|
|
|
|
|
|
|
|
tmp = readl(mmio + PDC_HDMA_CTLSTAT);
|
|
|
|
tmp &= ~PDC_RESET;
|
|
|
|
writel(tmp, mmio + PDC_HDMA_CTLSTAT);
|
|
|
|
readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
|
|
|
|
}
|
|
|
|
|
|
|
|
static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
|
|
{
|
|
|
|
static int printed_version;
|
|
|
|
struct ata_probe_ent *probe_ent = NULL;
|
|
|
|
unsigned long base;
|
2005-08-30 02:18:18 -07:00
|
|
|
void __iomem *mmio_base;
|
|
|
|
void __iomem *dimm_mmio = NULL;
|
2005-04-16 15:20:36 -07:00
|
|
|
struct pdc_host_priv *hpriv = NULL;
|
|
|
|
unsigned int board_idx = (unsigned int) ent->driver_data;
|
|
|
|
int pci_dev_busy = 0;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
if (!printed_version++)
|
2005-10-30 12:39:11 -07:00
|
|
|
dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* If this driver happens to only be useful on Apple's K2, then
|
|
|
|
* we should check that here as it has a normal Serverworks ID
|
|
|
|
*/
|
|
|
|
rc = pci_enable_device(pdev);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
rc = pci_request_regions(pdev, DRV_NAME);
|
|
|
|
if (rc) {
|
|
|
|
pci_dev_busy = 1;
|
|
|
|
goto err_out;
|
|
|
|
}
|
|
|
|
|
|
|
|
rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
|
|
|
|
if (rc)
|
|
|
|
goto err_out_regions;
|
|
|
|
rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
|
|
|
|
if (rc)
|
|
|
|
goto err_out_regions;
|
|
|
|
|
|
|
|
probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
|
|
|
|
if (probe_ent == NULL) {
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto err_out_regions;
|
|
|
|
}
|
|
|
|
|
|
|
|
memset(probe_ent, 0, sizeof(*probe_ent));
|
|
|
|
probe_ent->dev = pci_dev_to_dev(pdev);
|
|
|
|
INIT_LIST_HEAD(&probe_ent->node);
|
|
|
|
|
2005-08-30 02:42:52 -07:00
|
|
|
mmio_base = pci_iomap(pdev, 3, 0);
|
2005-04-16 15:20:36 -07:00
|
|
|
if (mmio_base == NULL) {
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto err_out_free_ent;
|
|
|
|
}
|
|
|
|
base = (unsigned long) mmio_base;
|
|
|
|
|
|
|
|
hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
|
|
|
|
if (!hpriv) {
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto err_out_iounmap;
|
|
|
|
}
|
|
|
|
memset(hpriv, 0, sizeof(*hpriv));
|
|
|
|
|
2005-08-30 02:42:52 -07:00
|
|
|
dimm_mmio = pci_iomap(pdev, 4, 0);
|
2005-04-16 15:20:36 -07:00
|
|
|
if (!dimm_mmio) {
|
|
|
|
kfree(hpriv);
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto err_out_iounmap;
|
|
|
|
}
|
|
|
|
|
|
|
|
hpriv->dimm_mmio = dimm_mmio;
|
|
|
|
|
|
|
|
probe_ent->sht = pdc_port_info[board_idx].sht;
|
|
|
|
probe_ent->host_flags = pdc_port_info[board_idx].host_flags;
|
|
|
|
probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
|
|
|
|
probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
|
|
|
|
probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
|
|
|
|
probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
|
|
|
|
|
|
|
|
probe_ent->irq = pdev->irq;
|
|
|
|
probe_ent->irq_flags = SA_SHIRQ;
|
|
|
|
probe_ent->mmio_base = mmio_base;
|
|
|
|
|
|
|
|
probe_ent->private_data = hpriv;
|
|
|
|
base += PDC_CHIP0_OFS;
|
|
|
|
|
|
|
|
probe_ent->n_ports = 4;
|
|
|
|
pdc_sata_setup_port(&probe_ent->port[0], base + 0x200);
|
|
|
|
pdc_sata_setup_port(&probe_ent->port[1], base + 0x280);
|
|
|
|
pdc_sata_setup_port(&probe_ent->port[2], base + 0x300);
|
|
|
|
pdc_sata_setup_port(&probe_ent->port[3], base + 0x380);
|
|
|
|
|
|
|
|
pci_set_master(pdev);
|
|
|
|
|
|
|
|
/* initialize adapter */
|
|
|
|
/* initialize local dimm */
|
|
|
|
if (pdc20621_dimm_init(probe_ent)) {
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto err_out_iounmap_dimm;
|
|
|
|
}
|
|
|
|
pdc_20621_init(probe_ent);
|
|
|
|
|
|
|
|
/* FIXME: check ata_device_add return value */
|
|
|
|
ata_device_add(probe_ent);
|
|
|
|
kfree(probe_ent);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_out_iounmap_dimm: /* only get to this label if 20621 */
|
|
|
|
kfree(hpriv);
|
2005-08-30 02:42:52 -07:00
|
|
|
pci_iounmap(pdev, dimm_mmio);
|
2005-04-16 15:20:36 -07:00
|
|
|
err_out_iounmap:
|
2005-08-30 02:42:52 -07:00
|
|
|
pci_iounmap(pdev, mmio_base);
|
2005-04-16 15:20:36 -07:00
|
|
|
err_out_free_ent:
|
|
|
|
kfree(probe_ent);
|
|
|
|
err_out_regions:
|
|
|
|
pci_release_regions(pdev);
|
|
|
|
err_out:
|
|
|
|
if (!pci_dev_busy)
|
|
|
|
pci_disable_device(pdev);
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static int __init pdc_sata_init(void)
|
|
|
|
{
|
|
|
|
return pci_module_init(&pdc_sata_pci_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void __exit pdc_sata_exit(void)
|
|
|
|
{
|
|
|
|
pci_unregister_driver(&pdc_sata_pci_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Jeff Garzik");
|
|
|
|
MODULE_DESCRIPTION("Promise SATA low-level driver");
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
|
|
|
|
MODULE_VERSION(DRV_VERSION);
|
|
|
|
|
|
|
|
module_init(pdc_sata_init);
|
|
|
|
module_exit(pdc_sata_exit);
|