2005-04-16 15:20:36 -07:00
|
|
|
/*
|
|
|
|
* Local APIC handling, local APIC timers
|
|
|
|
*
|
|
|
|
* (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
|
|
|
|
*
|
|
|
|
* Fixes
|
|
|
|
* Maciej W. Rozycki : Bits for genuine 82489DX APICs;
|
|
|
|
* thanks to Eric Gilmore
|
|
|
|
* and Rolf G. Tews
|
|
|
|
* for testing these extensively.
|
|
|
|
* Maciej W. Rozycki : Various updates and fixes.
|
|
|
|
* Mikael Pettersson : Power Management for UP-APIC.
|
|
|
|
* Pavel Machek and
|
|
|
|
* Mikael Pettersson : PM converted to driver model.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <linux/init.h>
|
|
|
|
|
|
|
|
#include <linux/mm.h>
|
|
|
|
#include <linux/delay.h>
|
|
|
|
#include <linux/bootmem.h>
|
|
|
|
#include <linux/interrupt.h>
|
|
|
|
#include <linux/mc146818rtc.h>
|
|
|
|
#include <linux/kernel_stat.h>
|
|
|
|
#include <linux/sysdev.h>
|
2005-06-25 14:54:50 -07:00
|
|
|
#include <linux/cpu.h>
|
2007-02-16 02:28:04 -07:00
|
|
|
#include <linux/clockchips.h>
|
2007-02-16 02:28:06 -07:00
|
|
|
#include <linux/acpi_pmtmr.h>
|
2006-01-11 14:44:21 -07:00
|
|
|
#include <linux/module.h>
|
2007-03-22 01:11:21 -07:00
|
|
|
#include <linux/dmi.h>
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
#include <asm/atomic.h>
|
|
|
|
#include <asm/smp.h>
|
|
|
|
#include <asm/mtrr.h>
|
|
|
|
#include <asm/mpspec.h>
|
|
|
|
#include <asm/desc.h>
|
|
|
|
#include <asm/arch_hooks.h>
|
|
|
|
#include <asm/hpet.h>
|
2005-06-30 02:58:55 -07:00
|
|
|
#include <asm/i8253.h>
|
2006-06-26 04:57:01 -07:00
|
|
|
#include <asm/nmi.h>
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
#include <mach_apic.h>
|
2006-03-23 03:59:49 -07:00
|
|
|
#include <mach_apicdef.h>
|
2006-01-11 14:44:21 -07:00
|
|
|
#include <mach_ipi.h>
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
|
|
|
* Sanity check
|
|
|
|
*/
|
2008-01-30 05:32:36 -07:00
|
|
|
#if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
|
2007-02-16 02:27:58 -07:00
|
|
|
# error SPURIOUS_APIC_VECTOR definition error
|
|
|
|
#endif
|
|
|
|
|
2008-03-27 13:54:38 -07:00
|
|
|
unsigned long mp_lapic_addr;
|
|
|
|
|
2005-06-25 14:57:41 -07:00
|
|
|
/*
|
|
|
|
* Knob to control our willingness to enable the local APIC.
|
2007-02-16 02:27:58 -07:00
|
|
|
*
|
2008-06-29 00:06:37 -07:00
|
|
|
* +1=force-enable
|
2005-06-25 14:57:41 -07:00
|
|
|
*/
|
2008-06-29 00:06:37 -07:00
|
|
|
static int force_enable_local_apic;
|
|
|
|
int disable_apic;
|
2005-06-25 14:57:41 -07:00
|
|
|
|
2007-02-16 02:28:06 -07:00
|
|
|
/* Local APIC timer verification ok */
|
|
|
|
static int local_apic_timer_verify_ok;
|
2008-06-09 10:15:00 -07:00
|
|
|
/* Disable local APIC timer from the kernel commandline or via dmi quirk */
|
|
|
|
static int local_apic_timer_disabled;
|
2007-03-23 08:08:01 -07:00
|
|
|
/* Local APIC timer works in C2 */
|
|
|
|
int local_apic_timer_c2_ok;
|
|
|
|
EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
|
2007-02-16 02:28:04 -07:00
|
|
|
|
2008-04-16 13:17:20 -07:00
|
|
|
int first_system_vector = 0xfe;
|
|
|
|
|
|
|
|
char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
|
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
/*
|
2007-02-16 02:27:58 -07:00
|
|
|
* Debug level, exported for io_apic.c
|
2005-04-16 15:20:36 -07:00
|
|
|
*/
|
2008-07-14 10:44:51 -07:00
|
|
|
unsigned int apic_verbosity;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2008-05-22 14:54:51 -07:00
|
|
|
int pic_mode;
|
|
|
|
|
2008-05-19 08:47:03 -07:00
|
|
|
/* Have we found an MP table */
|
|
|
|
int smp_found_config;
|
|
|
|
|
2008-07-01 10:43:52 -07:00
|
|
|
static struct resource lapic_resource = {
|
|
|
|
.name = "Local APIC",
|
|
|
|
.flags = IORESOURCE_MEM | IORESOURCE_BUSY,
|
|
|
|
};
|
|
|
|
|
2007-02-16 02:28:04 -07:00
|
|
|
static unsigned int calibration_result;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:28:04 -07:00
|
|
|
static int lapic_next_event(unsigned long delta,
|
|
|
|
struct clock_event_device *evt);
|
|
|
|
static void lapic_timer_setup(enum clock_event_mode mode,
|
|
|
|
struct clock_event_device *evt);
|
|
|
|
static void lapic_timer_broadcast(cpumask_t mask);
|
|
|
|
static void apic_pm_activate(void);
|
2007-02-16 02:27:58 -07:00
|
|
|
|
2007-02-16 02:28:04 -07:00
|
|
|
/*
|
|
|
|
* The local apic timer can be used for any function which is CPU local.
|
|
|
|
*/
|
|
|
|
static struct clock_event_device lapic_clockevent = {
|
|
|
|
.name = "lapic",
|
|
|
|
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
|
2007-02-16 02:28:06 -07:00
|
|
|
| CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
|
2007-02-16 02:28:04 -07:00
|
|
|
.shift = 32,
|
|
|
|
.set_mode = lapic_timer_setup,
|
|
|
|
.set_next_event = lapic_next_event,
|
|
|
|
.broadcast = lapic_timer_broadcast,
|
|
|
|
.rating = 100,
|
|
|
|
.irq = -1,
|
|
|
|
};
|
|
|
|
static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
|
2007-02-16 02:27:58 -07:00
|
|
|
|
|
|
|
/* Local APIC was disabled by the BIOS and enabled by the kernel */
|
|
|
|
static int enabled_via_apicbase;
|
|
|
|
|
2008-01-30 05:33:17 -07:00
|
|
|
static unsigned long apic_phys;
|
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
|
|
|
* Get the LAPIC version
|
|
|
|
*/
|
|
|
|
static inline int lapic_get_version(void)
|
2006-04-07 10:49:45 -07:00
|
|
|
{
|
2007-02-16 02:27:58 -07:00
|
|
|
return GET_APIC_VERSION(apic_read(APIC_LVR));
|
2006-04-07 10:49:45 -07:00
|
|
|
}
|
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
/*
|
2008-01-30 05:31:42 -07:00
|
|
|
* Check, if the APIC is integrated or a separate chip
|
2005-04-16 15:20:36 -07:00
|
|
|
*/
|
2007-02-16 02:27:58 -07:00
|
|
|
static inline int lapic_is_integrated(void)
|
2005-04-16 15:20:36 -07:00
|
|
|
{
|
2007-02-16 02:27:58 -07:00
|
|
|
return APIC_INTEGRATED(lapic_get_version());
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
|
|
|
* Check, whether this is a modern or a first generation APIC
|
|
|
|
*/
|
|
|
|
static int modern_apic(void)
|
2005-04-16 15:20:36 -07:00
|
|
|
{
|
2007-02-16 02:27:58 -07:00
|
|
|
/* AMD systems use old APIC versions, so check the CPU */
|
|
|
|
if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
|
|
|
|
boot_cpu_data.x86 >= 0xf)
|
|
|
|
return 1;
|
|
|
|
return lapic_get_version() >= 0x14;
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
2008-07-18 09:59:40 -07:00
|
|
|
/*
|
|
|
|
* Paravirt kernels also might be using these below ops. So we still
|
|
|
|
* use generic apic_read()/apic_write(), which might be pointing to different
|
|
|
|
* ops in PARAVIRT case.
|
|
|
|
*/
|
2008-07-11 18:41:54 -07:00
|
|
|
void xapic_wait_icr_idle(void)
|
[PATCH] i386: safe_apic_wait_icr_idle - i386
apic_wait_icr_idle looks like this:
static __inline__ void apic_wait_icr_idle(void)
{
while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
cpu_relax();
}
The busy loop in this function would not be problematic if the
corresponding status bit in the ICR were always updated, but that does
not seem to be the case under certain crash scenarios. Kdump uses an IPI
to stop the other CPUs in the event of a crash, but when any of the
other CPUs are locked-up inside the NMI handler the CPU that sends the
IPI will end up looping forever in the ICR check, effectively
hard-locking the whole system.
Quoting from Intel's "MultiProcessor Specification" (Version 1.4), B-3:
"A local APIC unit indicates successful dispatch of an IPI by
resetting the Delivery Status bit in the Interrupt Command
Register (ICR). The operating system polls the delivery status
bit after sending an INIT or STARTUP IPI until the command has
been dispatched.
A period of 20 microseconds should be sufficient for IPI dispatch
to complete under normal operating conditions. If the IPI is not
successfully dispatched, the operating system can abort the
command. Alternatively, the operating system can retry the IPI by
writing the lower 32-bit double word of the ICR. This “time-out”
mechanism can be implemented through an external interrupt, if
interrupts are enabled on the processor, or through execution of
an instruction or time-stamp counter spin loop."
Intel's documentation suggests the implementation of a time-out
mechanism, which, by the way, is already being open-coded in some parts
of the kernel that tinker with ICR.
Create a apic_wait_icr_idle replacement that implements the time-out
mechanism and that can be used to solve the aforementioned problem.
AK: moved both functions out of line
AK: added improved loop from Keith Owens
Signed-off-by: Fernando Luis Vazquez Cao <fernando@oss.ntt.co.jp>
Signed-off-by: Andi Kleen <ak@suse.de>
2007-05-02 10:27:17 -07:00
|
|
|
{
|
|
|
|
while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
|
|
|
|
cpu_relax();
|
|
|
|
}
|
|
|
|
|
2008-07-11 18:41:54 -07:00
|
|
|
u32 safe_xapic_wait_icr_idle(void)
|
[PATCH] i386: safe_apic_wait_icr_idle - i386
apic_wait_icr_idle looks like this:
static __inline__ void apic_wait_icr_idle(void)
{
while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
cpu_relax();
}
The busy loop in this function would not be problematic if the
corresponding status bit in the ICR were always updated, but that does
not seem to be the case under certain crash scenarios. Kdump uses an IPI
to stop the other CPUs in the event of a crash, but when any of the
other CPUs are locked-up inside the NMI handler the CPU that sends the
IPI will end up looping forever in the ICR check, effectively
hard-locking the whole system.
Quoting from Intel's "MultiProcessor Specification" (Version 1.4), B-3:
"A local APIC unit indicates successful dispatch of an IPI by
resetting the Delivery Status bit in the Interrupt Command
Register (ICR). The operating system polls the delivery status
bit after sending an INIT or STARTUP IPI until the command has
been dispatched.
A period of 20 microseconds should be sufficient for IPI dispatch
to complete under normal operating conditions. If the IPI is not
successfully dispatched, the operating system can abort the
command. Alternatively, the operating system can retry the IPI by
writing the lower 32-bit double word of the ICR. This “time-out”
mechanism can be implemented through an external interrupt, if
interrupts are enabled on the processor, or through execution of
an instruction or time-stamp counter spin loop."
Intel's documentation suggests the implementation of a time-out
mechanism, which, by the way, is already being open-coded in some parts
of the kernel that tinker with ICR.
Create a apic_wait_icr_idle replacement that implements the time-out
mechanism and that can be used to solve the aforementioned problem.
AK: moved both functions out of line
AK: added improved loop from Keith Owens
Signed-off-by: Fernando Luis Vazquez Cao <fernando@oss.ntt.co.jp>
Signed-off-by: Andi Kleen <ak@suse.de>
2007-05-02 10:27:17 -07:00
|
|
|
{
|
2008-01-30 05:30:15 -07:00
|
|
|
u32 send_status;
|
[PATCH] i386: safe_apic_wait_icr_idle - i386
apic_wait_icr_idle looks like this:
static __inline__ void apic_wait_icr_idle(void)
{
while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
cpu_relax();
}
The busy loop in this function would not be problematic if the
corresponding status bit in the ICR were always updated, but that does
not seem to be the case under certain crash scenarios. Kdump uses an IPI
to stop the other CPUs in the event of a crash, but when any of the
other CPUs are locked-up inside the NMI handler the CPU that sends the
IPI will end up looping forever in the ICR check, effectively
hard-locking the whole system.
Quoting from Intel's "MultiProcessor Specification" (Version 1.4), B-3:
"A local APIC unit indicates successful dispatch of an IPI by
resetting the Delivery Status bit in the Interrupt Command
Register (ICR). The operating system polls the delivery status
bit after sending an INIT or STARTUP IPI until the command has
been dispatched.
A period of 20 microseconds should be sufficient for IPI dispatch
to complete under normal operating conditions. If the IPI is not
successfully dispatched, the operating system can abort the
command. Alternatively, the operating system can retry the IPI by
writing the lower 32-bit double word of the ICR. This “time-out”
mechanism can be implemented through an external interrupt, if
interrupts are enabled on the processor, or through execution of
an instruction or time-stamp counter spin loop."
Intel's documentation suggests the implementation of a time-out
mechanism, which, by the way, is already being open-coded in some parts
of the kernel that tinker with ICR.
Create a apic_wait_icr_idle replacement that implements the time-out
mechanism and that can be used to solve the aforementioned problem.
AK: moved both functions out of line
AK: added improved loop from Keith Owens
Signed-off-by: Fernando Luis Vazquez Cao <fernando@oss.ntt.co.jp>
Signed-off-by: Andi Kleen <ak@suse.de>
2007-05-02 10:27:17 -07:00
|
|
|
int timeout;
|
|
|
|
|
|
|
|
timeout = 0;
|
|
|
|
do {
|
|
|
|
send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
|
|
|
|
if (!send_status)
|
|
|
|
break;
|
|
|
|
udelay(100);
|
|
|
|
} while (timeout++ < 1000);
|
|
|
|
|
|
|
|
return send_status;
|
|
|
|
}
|
|
|
|
|
2008-07-11 18:41:54 -07:00
|
|
|
void xapic_icr_write(u32 low, u32 id)
|
|
|
|
{
|
|
|
|
apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(id));
|
|
|
|
apic_write_around(APIC_ICR, low);
|
|
|
|
}
|
|
|
|
|
|
|
|
u64 xapic_icr_read(void)
|
|
|
|
{
|
|
|
|
u32 icr1, icr2;
|
|
|
|
|
|
|
|
icr2 = apic_read(APIC_ICR2);
|
|
|
|
icr1 = apic_read(APIC_ICR);
|
|
|
|
|
|
|
|
return icr1 | ((u64)icr2 << 32);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct apic_ops xapic_ops = {
|
|
|
|
.read = native_apic_mem_read,
|
|
|
|
.write = native_apic_mem_write,
|
|
|
|
.write_atomic = native_apic_mem_write_atomic,
|
|
|
|
.icr_read = xapic_icr_read,
|
|
|
|
.icr_write = xapic_icr_write,
|
|
|
|
.wait_icr_idle = xapic_wait_icr_idle,
|
|
|
|
.safe_wait_icr_idle = safe_xapic_wait_icr_idle,
|
|
|
|
};
|
|
|
|
|
|
|
|
struct apic_ops __read_mostly *apic_ops = &xapic_ops;
|
|
|
|
EXPORT_SYMBOL_GPL(apic_ops);
|
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/**
|
|
|
|
* enable_NMI_through_LVT0 - enable NMI through local vector table 0
|
|
|
|
*/
|
2008-01-30 05:31:24 -07:00
|
|
|
void __cpuinit enable_NMI_through_LVT0(void)
|
2005-04-16 15:20:36 -07:00
|
|
|
{
|
2007-02-16 02:27:58 -07:00
|
|
|
unsigned int v = APIC_DM_NMI;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/* Level triggered for 82489DX */
|
|
|
|
if (!lapic_is_integrated())
|
2005-04-16 15:20:36 -07:00
|
|
|
v |= APIC_LVT_LEVEL_TRIGGER;
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_LVT0, v);
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/**
|
|
|
|
* get_physical_broadcast - Get number of physical broadcast IDs
|
|
|
|
*/
|
2005-04-16 15:20:36 -07:00
|
|
|
int get_physical_broadcast(void)
|
|
|
|
{
|
2007-02-16 02:27:58 -07:00
|
|
|
return modern_apic() ? 0xff : 0xf;
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/**
|
|
|
|
* lapic_get_maxlvt - get the maximum number of local vector table entries
|
|
|
|
*/
|
|
|
|
int lapic_get_maxlvt(void)
|
2005-04-16 15:20:36 -07:00
|
|
|
{
|
2007-02-16 02:27:58 -07:00
|
|
|
unsigned int v = apic_read(APIC_LVR);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
/* 82489DXs do not report # of LVT entries. */
|
2007-02-16 02:27:58 -07:00
|
|
|
return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
|
|
|
* Local APIC timer
|
|
|
|
*/
|
|
|
|
|
2007-02-16 02:28:06 -07:00
|
|
|
/* Clock divisor is set to 16 */
|
|
|
|
#define APIC_DIVISOR 16
|
2007-02-16 02:27:58 -07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* This function sets up the local APIC timer, with a timeout of
|
|
|
|
* 'clocks' APIC bus clock. During calibration we actually call
|
|
|
|
* this function twice on the boot CPU, once with a bogus timeout
|
|
|
|
* value, second time for real. The other (noncalibrating) CPUs
|
|
|
|
* call this function only once, with the real, calibrated value.
|
|
|
|
*/
|
2007-02-16 02:28:04 -07:00
|
|
|
static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
|
2005-04-16 15:20:36 -07:00
|
|
|
{
|
2007-02-16 02:27:58 -07:00
|
|
|
unsigned int lvtt_value, tmp_value;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:28:04 -07:00
|
|
|
lvtt_value = LOCAL_TIMER_VECTOR;
|
|
|
|
if (!oneshot)
|
|
|
|
lvtt_value |= APIC_LVT_TIMER_PERIODIC;
|
2007-02-16 02:27:58 -07:00
|
|
|
if (!lapic_is_integrated())
|
|
|
|
lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
|
|
|
|
|
2007-02-16 02:28:04 -07:00
|
|
|
if (!irqen)
|
2007-02-16 02:27:58 -07:00
|
|
|
lvtt_value |= APIC_LVT_MASKED;
|
|
|
|
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_LVTT, lvtt_value);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
/*
|
2007-02-16 02:27:58 -07:00
|
|
|
* Divide PICLK by 16
|
2005-04-16 15:20:36 -07:00
|
|
|
*/
|
2007-02-16 02:27:58 -07:00
|
|
|
tmp_value = apic_read(APIC_TDCR);
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_TDCR,
|
|
|
|
(tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
|
|
|
|
APIC_TDR_DIV_16);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:28:04 -07:00
|
|
|
if (!oneshot)
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
|
2007-02-16 02:28:04 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Program the next event, relative to now
|
|
|
|
*/
|
|
|
|
static int lapic_next_event(unsigned long delta,
|
|
|
|
struct clock_event_device *evt)
|
|
|
|
{
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_TMICT, delta);
|
2007-02-16 02:28:04 -07:00
|
|
|
return 0;
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
2007-02-16 02:28:04 -07:00
|
|
|
/*
|
|
|
|
* Setup the lapic timer in periodic or oneshot mode
|
|
|
|
*/
|
|
|
|
static void lapic_timer_setup(enum clock_event_mode mode,
|
|
|
|
struct clock_event_device *evt)
|
2005-04-16 15:20:36 -07:00
|
|
|
{
|
2007-02-16 02:27:58 -07:00
|
|
|
unsigned long flags;
|
2007-02-16 02:28:04 -07:00
|
|
|
unsigned int v;
|
2007-02-16 02:27:58 -07:00
|
|
|
|
2007-02-16 02:28:06 -07:00
|
|
|
/* Lapic used for broadcast ? */
|
|
|
|
if (!local_apic_timer_verify_ok)
|
|
|
|
return;
|
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
local_irq_save(flags);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:28:04 -07:00
|
|
|
switch (mode) {
|
|
|
|
case CLOCK_EVT_MODE_PERIODIC:
|
|
|
|
case CLOCK_EVT_MODE_ONESHOT:
|
|
|
|
__setup_APIC_LVTT(calibration_result,
|
|
|
|
mode != CLOCK_EVT_MODE_PERIODIC, 1);
|
|
|
|
break;
|
|
|
|
case CLOCK_EVT_MODE_UNUSED:
|
|
|
|
case CLOCK_EVT_MODE_SHUTDOWN:
|
|
|
|
v = apic_read(APIC_LVTT);
|
|
|
|
v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_LVTT, v);
|
2007-02-16 02:28:04 -07:00
|
|
|
break;
|
2007-07-21 04:37:34 -07:00
|
|
|
case CLOCK_EVT_MODE_RESUME:
|
|
|
|
/* Nothing to do here */
|
|
|
|
break;
|
2007-02-16 02:28:04 -07:00
|
|
|
}
|
2007-02-16 02:27:58 -07:00
|
|
|
|
|
|
|
local_irq_restore(flags);
|
|
|
|
}
|
|
|
|
|
2007-02-16 02:28:04 -07:00
|
|
|
/*
|
|
|
|
* Local APIC timer broadcast function
|
|
|
|
*/
|
|
|
|
static void lapic_timer_broadcast(cpumask_t mask)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Setup the local APIC timer for this CPU. Copy the initilized values
|
|
|
|
* of the boot CPU and register the clock event in the framework.
|
|
|
|
*/
|
|
|
|
static void __devinit setup_APIC_timer(void)
|
|
|
|
{
|
|
|
|
struct clock_event_device *levt = &__get_cpu_var(lapic_events);
|
|
|
|
|
|
|
|
memcpy(levt, &lapic_clockevent, sizeof(*levt));
|
|
|
|
levt->cpumask = cpumask_of_cpu(smp_processor_id());
|
|
|
|
|
|
|
|
clockevents_register_device(levt);
|
|
|
|
}
|
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
2007-02-16 02:28:06 -07:00
|
|
|
* In this functions we calibrate APIC bus clocks to the external timer.
|
|
|
|
*
|
|
|
|
* We want to do the calibration only once since we want to have local timer
|
|
|
|
* irqs syncron. CPUs connected by the same APIC bus have the very same bus
|
|
|
|
* frequency.
|
|
|
|
*
|
|
|
|
* This was previously done by reading the PIT/HPET and waiting for a wrap
|
|
|
|
* around to find out, that a tick has elapsed. I have a box, where the PIT
|
|
|
|
* readout is broken, so it never gets out of the wait loop again. This was
|
|
|
|
* also reported by others.
|
2007-02-16 02:27:58 -07:00
|
|
|
*
|
2007-02-16 02:28:06 -07:00
|
|
|
* Monitoring the jiffies value is inaccurate and the clockevents
|
|
|
|
* infrastructure allows us to do a simple substitution of the interrupt
|
|
|
|
* handler.
|
2007-02-16 02:28:04 -07:00
|
|
|
*
|
2007-02-16 02:28:06 -07:00
|
|
|
* The calibration routine also uses the pm_timer when possible, as the PIT
|
|
|
|
* happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
|
|
|
|
* back to normal later in the boot process).
|
2007-02-16 02:27:58 -07:00
|
|
|
*/
|
|
|
|
|
2007-02-16 02:28:06 -07:00
|
|
|
#define LAPIC_CAL_LOOPS (HZ/10)
|
2007-02-16 02:27:58 -07:00
|
|
|
|
2007-07-21 08:11:32 -07:00
|
|
|
static __initdata int lapic_cal_loops = -1;
|
2007-02-16 02:28:06 -07:00
|
|
|
static __initdata long lapic_cal_t1, lapic_cal_t2;
|
|
|
|
static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
|
|
|
|
static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
|
|
|
|
static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:28:06 -07:00
|
|
|
/*
|
|
|
|
* Temporary interrupt handler.
|
|
|
|
*/
|
|
|
|
static void __init lapic_cal_handler(struct clock_event_device *dev)
|
|
|
|
{
|
|
|
|
unsigned long long tsc = 0;
|
|
|
|
long tapic = apic_read(APIC_TMCCT);
|
|
|
|
unsigned long pm = acpi_pm_read_early();
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:28:06 -07:00
|
|
|
if (cpu_has_tsc)
|
|
|
|
rdtscll(tsc);
|
|
|
|
|
|
|
|
switch (lapic_cal_loops++) {
|
|
|
|
case 0:
|
|
|
|
lapic_cal_t1 = tapic;
|
|
|
|
lapic_cal_tsc1 = tsc;
|
|
|
|
lapic_cal_pm1 = pm;
|
|
|
|
lapic_cal_j1 = jiffies;
|
|
|
|
break;
|
2007-02-16 02:27:58 -07:00
|
|
|
|
2007-02-16 02:28:06 -07:00
|
|
|
case LAPIC_CAL_LOOPS:
|
|
|
|
lapic_cal_t2 = tapic;
|
|
|
|
lapic_cal_tsc2 = tsc;
|
|
|
|
if (pm < lapic_cal_pm1)
|
|
|
|
pm += ACPI_PM_OVRRUN;
|
|
|
|
lapic_cal_pm2 = pm;
|
|
|
|
lapic_cal_j2 = jiffies;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2008-07-15 10:02:55 -07:00
|
|
|
static int __init calibrate_APIC_clock(void)
|
2007-02-16 02:28:06 -07:00
|
|
|
{
|
|
|
|
struct clock_event_device *levt = &__get_cpu_var(lapic_events);
|
|
|
|
const long pm_100ms = PMTMR_TICKS_PER_SEC/10;
|
|
|
|
const long pm_thresh = pm_100ms/100;
|
|
|
|
void (*real_handler)(struct clock_event_device *dev);
|
|
|
|
unsigned long deltaj;
|
|
|
|
long delta, deltapm;
|
2007-03-18 02:26:13 -07:00
|
|
|
int pm_referenced = 0;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:28:06 -07:00
|
|
|
local_irq_disable();
|
|
|
|
|
|
|
|
/* Replace the global interrupt handler */
|
|
|
|
real_handler = global_clock_event->event_handler;
|
|
|
|
global_clock_event->event_handler = lapic_cal_handler;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
/*
|
2007-02-16 02:28:06 -07:00
|
|
|
* Setup the APIC counter to 1e9. There is no way the lapic
|
|
|
|
* can underflow in the 100ms detection time frame
|
2005-04-16 15:20:36 -07:00
|
|
|
*/
|
2007-02-16 02:28:06 -07:00
|
|
|
__setup_APIC_LVTT(1000000000, 0, 0);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:28:06 -07:00
|
|
|
/* Let the interrupts run */
|
|
|
|
local_irq_enable();
|
|
|
|
|
2007-03-18 02:26:13 -07:00
|
|
|
while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
|
|
|
|
cpu_relax();
|
2007-02-16 02:28:06 -07:00
|
|
|
|
|
|
|
local_irq_disable();
|
|
|
|
|
|
|
|
/* Restore the real event handler */
|
|
|
|
global_clock_event->event_handler = real_handler;
|
|
|
|
|
|
|
|
/* Build delta t1-t2 as apic timer counts down */
|
|
|
|
delta = lapic_cal_t1 - lapic_cal_t2;
|
|
|
|
apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
|
|
|
|
|
|
|
|
/* Check, if the PM timer is available */
|
|
|
|
deltapm = lapic_cal_pm2 - lapic_cal_pm1;
|
|
|
|
apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm);
|
|
|
|
|
|
|
|
if (deltapm) {
|
|
|
|
unsigned long mult;
|
|
|
|
u64 res;
|
|
|
|
|
|
|
|
mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
|
|
|
|
|
|
|
|
if (deltapm > (pm_100ms - pm_thresh) &&
|
|
|
|
deltapm < (pm_100ms + pm_thresh)) {
|
|
|
|
apic_printk(APIC_VERBOSE, "... PM timer result ok\n");
|
|
|
|
} else {
|
|
|
|
res = (((u64) deltapm) * mult) >> 22;
|
|
|
|
do_div(res, 1000000);
|
|
|
|
printk(KERN_WARNING "APIC calibration not consistent "
|
|
|
|
"with PM Timer: %ldms instead of 100ms\n",
|
|
|
|
(long)res);
|
|
|
|
/* Correct the lapic counter value */
|
2008-01-30 05:32:36 -07:00
|
|
|
res = (((u64) delta) * pm_100ms);
|
2007-02-16 02:28:06 -07:00
|
|
|
do_div(res, deltapm);
|
|
|
|
printk(KERN_INFO "APIC delta adjusted to PM-Timer: "
|
|
|
|
"%lu (%ld)\n", (unsigned long) res, delta);
|
|
|
|
delta = (long) res;
|
|
|
|
}
|
2007-03-18 02:26:13 -07:00
|
|
|
pm_referenced = 1;
|
2007-02-16 02:28:06 -07:00
|
|
|
}
|
2007-02-16 02:27:58 -07:00
|
|
|
|
2007-02-16 02:28:04 -07:00
|
|
|
/* Calculate the scaled math multiplication factor */
|
2008-04-19 07:55:16 -07:00
|
|
|
lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
|
|
|
|
lapic_clockevent.shift);
|
2007-02-16 02:28:04 -07:00
|
|
|
lapic_clockevent.max_delta_ns =
|
|
|
|
clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
|
|
|
|
lapic_clockevent.min_delta_ns =
|
|
|
|
clockevent_delta2ns(0xF, &lapic_clockevent);
|
|
|
|
|
2007-02-16 02:28:06 -07:00
|
|
|
calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
|
|
|
|
|
|
|
|
apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
|
2007-02-16 02:28:04 -07:00
|
|
|
apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
|
2007-02-16 02:28:06 -07:00
|
|
|
apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
|
|
|
|
calibration_result);
|
2007-02-16 02:28:04 -07:00
|
|
|
|
2007-02-16 02:28:06 -07:00
|
|
|
if (cpu_has_tsc) {
|
|
|
|
delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
|
2007-02-16 02:27:58 -07:00
|
|
|
apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
|
2007-02-16 02:28:06 -07:00
|
|
|
"%ld.%04ld MHz.\n",
|
|
|
|
(delta / LAPIC_CAL_LOOPS) / (1000000 / HZ),
|
|
|
|
(delta / LAPIC_CAL_LOOPS) % (1000000 / HZ));
|
|
|
|
}
|
2007-02-16 02:27:58 -07:00
|
|
|
|
|
|
|
apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
|
2007-02-16 02:28:06 -07:00
|
|
|
"%u.%04u MHz.\n",
|
|
|
|
calibration_result / (1000000 / HZ),
|
|
|
|
calibration_result % (1000000 / HZ));
|
2007-02-16 02:27:58 -07:00
|
|
|
|
2008-01-30 05:33:04 -07:00
|
|
|
/*
|
|
|
|
* Do a sanity check on the APIC calibration result
|
|
|
|
*/
|
|
|
|
if (calibration_result < (1000000 / HZ)) {
|
|
|
|
local_irq_enable();
|
|
|
|
printk(KERN_WARNING
|
|
|
|
"APIC frequency too slow, disabling apic timer\n");
|
2008-07-15 10:02:55 -07:00
|
|
|
return -1;
|
2008-01-30 05:33:04 -07:00
|
|
|
}
|
|
|
|
|
2008-07-15 10:02:55 -07:00
|
|
|
local_apic_timer_verify_ok = 1;
|
|
|
|
|
2007-03-18 02:26:13 -07:00
|
|
|
/* We trust the pm timer based calibration */
|
|
|
|
if (!pm_referenced) {
|
|
|
|
apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
|
2007-02-16 02:28:06 -07:00
|
|
|
|
2007-03-18 02:26:13 -07:00
|
|
|
/*
|
|
|
|
* Setup the apic timer manually
|
|
|
|
*/
|
|
|
|
levt->event_handler = lapic_cal_handler;
|
|
|
|
lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
|
|
|
|
lapic_cal_loops = -1;
|
2007-02-16 02:28:06 -07:00
|
|
|
|
2007-03-18 02:26:13 -07:00
|
|
|
/* Let the interrupts run */
|
|
|
|
local_irq_enable();
|
2007-02-16 02:28:06 -07:00
|
|
|
|
2007-07-21 08:11:32 -07:00
|
|
|
while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
|
2007-03-18 02:26:13 -07:00
|
|
|
cpu_relax();
|
2007-02-16 02:28:06 -07:00
|
|
|
|
2007-03-18 02:26:13 -07:00
|
|
|
local_irq_disable();
|
2007-02-16 02:28:06 -07:00
|
|
|
|
2007-03-18 02:26:13 -07:00
|
|
|
/* Stop the lapic timer */
|
|
|
|
lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
|
2007-02-16 02:28:06 -07:00
|
|
|
|
2007-03-18 02:26:13 -07:00
|
|
|
local_irq_enable();
|
2007-02-16 02:28:06 -07:00
|
|
|
|
2007-03-18 02:26:13 -07:00
|
|
|
/* Jiffies delta */
|
|
|
|
deltaj = lapic_cal_j2 - lapic_cal_j1;
|
|
|
|
apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
|
2007-02-16 02:28:06 -07:00
|
|
|
|
|
|
|
/* Check, if the jiffies result is consistent */
|
2007-03-18 02:26:13 -07:00
|
|
|
if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
|
2007-02-16 02:28:06 -07:00
|
|
|
apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
|
2007-03-18 02:26:13 -07:00
|
|
|
else
|
|
|
|
local_apic_timer_verify_ok = 0;
|
2007-03-22 02:31:19 -07:00
|
|
|
} else
|
|
|
|
local_irq_enable();
|
2007-02-16 02:27:58 -07:00
|
|
|
|
2007-02-16 02:28:06 -07:00
|
|
|
if (!local_apic_timer_verify_ok) {
|
|
|
|
printk(KERN_WARNING
|
|
|
|
"APIC timer disabled due to verification failure.\n");
|
2008-07-15 10:02:55 -07:00
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Setup the boot APIC
|
|
|
|
*
|
|
|
|
* Calibrate and verify the result.
|
|
|
|
*/
|
|
|
|
void __init setup_boot_APIC_clock(void)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* The local apic timer can be disabled via the kernel
|
|
|
|
* commandline or from the CPU detection code. Register the lapic
|
|
|
|
* timer as a dummy clock event source on SMP systems, so the
|
|
|
|
* broadcast mechanism is used. On UP systems simply ignore it.
|
|
|
|
*/
|
|
|
|
if (local_apic_timer_disabled) {
|
2007-02-16 02:28:06 -07:00
|
|
|
/* No broadcast on UP ! */
|
2008-07-15 10:02:55 -07:00
|
|
|
if (num_possible_cpus() > 1) {
|
|
|
|
lapic_clockevent.mult = 1;
|
|
|
|
setup_APIC_timer();
|
|
|
|
}
|
|
|
|
return;
|
2007-03-05 01:30:45 -07:00
|
|
|
}
|
2007-02-16 02:28:06 -07:00
|
|
|
|
2008-07-15 10:02:55 -07:00
|
|
|
apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
|
|
|
|
"calibrating APIC timer ...\n");
|
|
|
|
|
|
|
|
if (calibrate_APIC_clock()) {
|
|
|
|
/* No broadcast on UP ! */
|
|
|
|
if (num_possible_cpus() > 1)
|
|
|
|
setup_APIC_timer();
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If nmi_watchdog is set to IO_APIC, we need the
|
|
|
|
* PIT/HPET going. Otherwise register lapic as a dummy
|
|
|
|
* device.
|
|
|
|
*/
|
|
|
|
if (nmi_watchdog != NMI_IO_APIC)
|
|
|
|
lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
|
|
|
|
else
|
|
|
|
printk(KERN_WARNING "APIC timer registered as dummy,"
|
|
|
|
" due to nmi_watchdog=%d!\n", nmi_watchdog);
|
|
|
|
|
2007-02-16 02:28:06 -07:00
|
|
|
/* Setup the lapic or request the broadcast */
|
|
|
|
setup_APIC_timer();
|
2007-02-16 02:27:58 -07:00
|
|
|
}
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
void __devinit setup_secondary_APIC_clock(void)
|
|
|
|
{
|
2007-02-16 02:28:04 -07:00
|
|
|
setup_APIC_timer();
|
2007-02-16 02:27:58 -07:00
|
|
|
}
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
2007-02-16 02:28:04 -07:00
|
|
|
* The guts of the apic timer interrupt
|
2007-02-16 02:27:58 -07:00
|
|
|
*/
|
2007-02-16 02:28:04 -07:00
|
|
|
static void local_apic_timer_interrupt(void)
|
2007-02-16 02:27:58 -07:00
|
|
|
{
|
2007-02-16 02:28:04 -07:00
|
|
|
int cpu = smp_processor_id();
|
|
|
|
struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
/*
|
2007-02-16 02:28:06 -07:00
|
|
|
* Normally we should not be here till LAPIC has been initialized but
|
|
|
|
* in some cases like kdump, its possible that there is a pending LAPIC
|
|
|
|
* timer interrupt from previous kernel's context and is delivered in
|
|
|
|
* new kernel the moment interrupts are enabled.
|
2007-02-16 02:27:58 -07:00
|
|
|
*
|
2007-02-16 02:28:06 -07:00
|
|
|
* Interrupts are enabled early and LAPIC is setup much later, hence
|
|
|
|
* its possible that when we get here evt->event_handler is NULL.
|
|
|
|
* Check for event_handler being NULL and discard the interrupt as
|
|
|
|
* spurious.
|
2005-04-16 15:20:36 -07:00
|
|
|
*/
|
2007-02-16 02:28:04 -07:00
|
|
|
if (!evt->event_handler) {
|
|
|
|
printk(KERN_WARNING
|
|
|
|
"Spurious LAPIC timer interrupt on cpu %d\n", cpu);
|
|
|
|
/* Switch it off */
|
|
|
|
lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2008-01-30 05:30:20 -07:00
|
|
|
/*
|
|
|
|
* the NMI deadlock-detector uses this.
|
|
|
|
*/
|
2007-02-16 02:28:04 -07:00
|
|
|
per_cpu(irq_stat, cpu).apic_timer_irqs++;
|
|
|
|
|
|
|
|
evt->event_handler(evt);
|
2007-02-16 02:27:58 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Local APIC timer interrupt. This is the most natural way for doing
|
|
|
|
* local interrupts, but local timer interrupts can be emulated by
|
|
|
|
* broadcast interrupts too. [in case the hw doesn't support APIC timers]
|
|
|
|
*
|
|
|
|
* [ if a single-CPU system runs an SMP kernel then we call the local
|
|
|
|
* interrupt as well. Thus we cannot inline the local irq ... ]
|
|
|
|
*/
|
2008-01-30 05:31:17 -07:00
|
|
|
void smp_apic_timer_interrupt(struct pt_regs *regs)
|
2007-02-16 02:27:58 -07:00
|
|
|
{
|
|
|
|
struct pt_regs *old_regs = set_irq_regs(regs);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
/*
|
2007-02-16 02:27:58 -07:00
|
|
|
* NOTE! We'd better ACK the irq immediately,
|
|
|
|
* because timer handling can be slow.
|
2005-04-16 15:20:36 -07:00
|
|
|
*/
|
2007-02-16 02:27:58 -07:00
|
|
|
ack_APIC_irq();
|
2006-03-31 03:30:05 -07:00
|
|
|
/*
|
2007-02-16 02:27:58 -07:00
|
|
|
* update_process_times() expects us to have done irq_enter().
|
|
|
|
* Besides, if we don't timer interrupts ignore the global
|
|
|
|
* interrupt lock, which is the WrongThing (tm) to do.
|
2006-03-31 03:30:05 -07:00
|
|
|
*/
|
2007-02-16 02:27:58 -07:00
|
|
|
irq_enter();
|
2007-02-16 02:28:04 -07:00
|
|
|
local_apic_timer_interrupt();
|
2007-02-16 02:27:58 -07:00
|
|
|
irq_exit();
|
2006-03-31 03:30:05 -07:00
|
|
|
|
2007-02-16 02:28:04 -07:00
|
|
|
set_irq_regs(old_regs);
|
2007-02-16 02:27:58 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
int setup_profiling_timer(unsigned int multiplier)
|
|
|
|
{
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2008-02-13 08:19:36 -07:00
|
|
|
/*
|
|
|
|
* Setup extended LVT, AMD specific (K8, family 10h)
|
|
|
|
*
|
|
|
|
* Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
|
|
|
|
* MCE interrupts are supported. Thus MCE offset must be set to 0.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#define APIC_EILVT_LVTOFF_MCE 0
|
|
|
|
#define APIC_EILVT_LVTOFF_IBS 1
|
|
|
|
|
|
|
|
static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
|
|
|
|
{
|
|
|
|
unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
|
|
|
|
unsigned int v = (mask << 16) | (msg_type << 8) | vector;
|
|
|
|
apic_write(reg, v);
|
|
|
|
}
|
|
|
|
|
|
|
|
u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
|
|
|
|
{
|
|
|
|
setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
|
|
|
|
return APIC_EILVT_LVTOFF_MCE;
|
|
|
|
}
|
|
|
|
|
|
|
|
u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
|
|
|
|
{
|
|
|
|
setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
|
|
|
|
return APIC_EILVT_LVTOFF_IBS;
|
|
|
|
}
|
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
|
|
|
* Local APIC start and shutdown
|
|
|
|
*/
|
|
|
|
|
|
|
|
/**
|
|
|
|
* clear_local_APIC - shutdown the local APIC
|
|
|
|
*
|
|
|
|
* This is called, when a CPU is disabled and before rebooting, so the state of
|
|
|
|
* the local APIC has no dangling leftovers. Also used to cleanout any BIOS
|
|
|
|
* leftovers during boot.
|
|
|
|
*/
|
|
|
|
void clear_local_APIC(void)
|
|
|
|
{
|
2008-01-30 05:33:17 -07:00
|
|
|
int maxlvt;
|
2008-01-30 05:30:20 -07:00
|
|
|
u32 v;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2008-01-30 05:33:17 -07:00
|
|
|
/* APIC hasn't been mapped yet */
|
|
|
|
if (!apic_phys)
|
|
|
|
return;
|
|
|
|
|
|
|
|
maxlvt = lapic_get_maxlvt();
|
2005-04-16 15:20:36 -07:00
|
|
|
/*
|
2007-02-16 02:27:58 -07:00
|
|
|
* Masking an LVT entry can trigger a local APIC error
|
|
|
|
* if the vector is zero. Mask LVTERR first to prevent this.
|
2005-04-16 15:20:36 -07:00
|
|
|
*/
|
2007-02-16 02:27:58 -07:00
|
|
|
if (maxlvt >= 3) {
|
|
|
|
v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
|
2007-02-16 02:27:58 -07:00
|
|
|
}
|
2005-04-16 15:20:36 -07:00
|
|
|
/*
|
2007-02-16 02:27:58 -07:00
|
|
|
* Careful: we have to set masks only first to deassert
|
|
|
|
* any level-triggered sources.
|
2005-04-16 15:20:36 -07:00
|
|
|
*/
|
2007-02-16 02:27:58 -07:00
|
|
|
v = apic_read(APIC_LVTT);
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
|
2007-02-16 02:27:58 -07:00
|
|
|
v = apic_read(APIC_LVT0);
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
|
2007-02-16 02:27:58 -07:00
|
|
|
v = apic_read(APIC_LVT1);
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
|
2007-02-16 02:27:58 -07:00
|
|
|
if (maxlvt >= 4) {
|
|
|
|
v = apic_read(APIC_LVTPC);
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/* lets not touch this if we didn't frob it */
|
|
|
|
#ifdef CONFIG_X86_MCE_P4THERMAL
|
|
|
|
if (maxlvt >= 5) {
|
|
|
|
v = apic_read(APIC_LVTTHMR);
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
|
2007-02-16 02:27:58 -07:00
|
|
|
}
|
|
|
|
#endif
|
2005-04-16 15:20:36 -07:00
|
|
|
/*
|
2007-02-16 02:27:58 -07:00
|
|
|
* Clean APIC state for other OSs:
|
2005-04-16 15:20:36 -07:00
|
|
|
*/
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_LVTT, APIC_LVT_MASKED);
|
|
|
|
apic_write(APIC_LVT0, APIC_LVT_MASKED);
|
|
|
|
apic_write(APIC_LVT1, APIC_LVT_MASKED);
|
2007-02-16 02:27:58 -07:00
|
|
|
if (maxlvt >= 3)
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_LVTERR, APIC_LVT_MASKED);
|
2007-02-16 02:27:58 -07:00
|
|
|
if (maxlvt >= 4)
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_LVTPC, APIC_LVT_MASKED);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
#ifdef CONFIG_X86_MCE_P4THERMAL
|
|
|
|
if (maxlvt >= 5)
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_LVTTHMR, APIC_LVT_MASKED);
|
2007-02-16 02:27:58 -07:00
|
|
|
#endif
|
|
|
|
/* Integrated APIC (!82489DX) ? */
|
|
|
|
if (lapic_is_integrated()) {
|
2005-04-16 15:20:36 -07:00
|
|
|
if (maxlvt > 3)
|
2007-02-16 02:27:58 -07:00
|
|
|
/* Clear ESR due to Pentium errata 3AP and 11AP */
|
2005-04-16 15:20:36 -07:00
|
|
|
apic_write(APIC_ESR, 0);
|
2007-02-16 02:27:58 -07:00
|
|
|
apic_read(APIC_ESR);
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
2007-02-16 02:27:58 -07:00
|
|
|
}
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/**
|
|
|
|
* disable_local_APIC - clear and disable the local APIC
|
|
|
|
*/
|
|
|
|
void disable_local_APIC(void)
|
|
|
|
{
|
|
|
|
unsigned long value;
|
|
|
|
|
|
|
|
clear_local_APIC();
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Disable APIC (implies clearing of registers
|
|
|
|
* for 82489DX!).
|
|
|
|
*/
|
|
|
|
value = apic_read(APIC_SPIV);
|
|
|
|
value &= ~APIC_SPIV_APIC_ENABLED;
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_SPIV, value);
|
2007-02-16 02:27:58 -07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* When LAPIC was disabled by the BIOS and enabled by the kernel,
|
|
|
|
* restore the disabled state.
|
|
|
|
*/
|
|
|
|
if (enabled_via_apicbase) {
|
|
|
|
unsigned int l, h;
|
|
|
|
|
|
|
|
rdmsr(MSR_IA32_APICBASE, l, h);
|
|
|
|
l &= ~MSR_IA32_APICBASE_ENABLE;
|
|
|
|
wrmsr(MSR_IA32_APICBASE, l, h);
|
|
|
|
}
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
2007-02-16 02:27:58 -07:00
|
|
|
* If Linux enabled the LAPIC against the BIOS default disable it down before
|
|
|
|
* re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
|
|
|
|
* not power-off. Additionally clear all LVT entries before disable_local_APIC
|
2005-11-07 01:58:33 -07:00
|
|
|
* for the case where Linux didn't enable the LAPIC.
|
2005-04-16 15:20:36 -07:00
|
|
|
*/
|
|
|
|
void lapic_shutdown(void)
|
|
|
|
{
|
2006-03-14 02:33:14 -07:00
|
|
|
unsigned long flags;
|
|
|
|
|
2005-11-07 01:58:33 -07:00
|
|
|
if (!cpu_has_apic)
|
2005-04-16 15:20:36 -07:00
|
|
|
return;
|
|
|
|
|
2006-03-14 02:33:14 -07:00
|
|
|
local_irq_save(flags);
|
2005-11-07 01:58:33 -07:00
|
|
|
clear_local_APIC();
|
|
|
|
|
|
|
|
if (enabled_via_apicbase)
|
|
|
|
disable_local_APIC();
|
|
|
|
|
2006-03-14 02:33:14 -07:00
|
|
|
local_irq_restore(flags);
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
|
|
|
* This is to verify that we're looking at a real local APIC.
|
|
|
|
* Check these against your board if the CPUs aren't getting
|
|
|
|
* started for no apparent reason.
|
|
|
|
*/
|
|
|
|
int __init verify_local_APIC(void)
|
2005-04-16 15:20:36 -07:00
|
|
|
{
|
2007-02-16 02:27:58 -07:00
|
|
|
unsigned int reg0, reg1;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
|
|
|
* The version register is read-only in a real APIC.
|
|
|
|
*/
|
|
|
|
reg0 = apic_read(APIC_LVR);
|
|
|
|
apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
|
|
|
|
apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
|
|
|
|
reg1 = apic_read(APIC_LVR);
|
|
|
|
apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The two version reads above should print the same
|
|
|
|
* numbers. If the second one is different, then we
|
|
|
|
* poke at a non-APIC.
|
|
|
|
*/
|
|
|
|
if (reg1 != reg0)
|
2005-04-16 15:20:36 -07:00
|
|
|
return 0;
|
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
|
|
|
* Check if the version looks reasonably.
|
|
|
|
*/
|
|
|
|
reg1 = GET_APIC_VERSION(reg0);
|
|
|
|
if (reg1 == 0x00 || reg1 == 0xff)
|
|
|
|
return 0;
|
|
|
|
reg1 = lapic_get_maxlvt();
|
|
|
|
if (reg1 < 0x02 || reg1 == 0xff)
|
|
|
|
return 0;
|
2006-12-06 18:14:11 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
|
|
|
* The ID register is read/write in a real APIC.
|
|
|
|
*/
|
|
|
|
reg0 = apic_read(APIC_ID);
|
|
|
|
apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The next two are just to see if we have sane values.
|
|
|
|
* They're only really relevant if we're in Virtual Wire
|
|
|
|
* compatibility mode, but most boxes are anymore.
|
|
|
|
*/
|
|
|
|
reg0 = apic_read(APIC_LVT0);
|
|
|
|
apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
|
|
|
|
reg1 = apic_read(APIC_LVT1);
|
|
|
|
apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
|
|
|
|
|
|
|
|
return 1;
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/**
|
|
|
|
* sync_Arb_IDs - synchronize APIC bus arbitration IDs
|
|
|
|
*/
|
|
|
|
void __init sync_Arb_IDs(void)
|
2005-04-16 15:20:36 -07:00
|
|
|
{
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
|
|
|
* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
|
|
|
|
* needed on AMD.
|
|
|
|
*/
|
2007-11-26 12:42:20 -07:00
|
|
|
if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
|
2007-02-16 02:27:58 -07:00
|
|
|
return;
|
|
|
|
/*
|
|
|
|
* Wait for idle.
|
|
|
|
*/
|
|
|
|
apic_wait_icr_idle();
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_ICR,
|
|
|
|
APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | APIC_DM_INIT);
|
2007-02-16 02:27:58 -07:00
|
|
|
}
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
|
|
|
* An initial setup of the virtual wire mode.
|
|
|
|
*/
|
|
|
|
void __init init_bsp_APIC(void)
|
|
|
|
{
|
|
|
|
unsigned long value;
|
2006-12-06 18:14:11 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
|
|
|
* Don't do the setup now if we have a SMP BIOS as the
|
|
|
|
* through-I/O-APIC virtual wire mode might be active.
|
|
|
|
*/
|
|
|
|
if (smp_found_config || !cpu_has_apic)
|
|
|
|
return;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
/*
|
2007-02-16 02:27:58 -07:00
|
|
|
* Do not trust the local APIC being empty at bootup.
|
2005-04-16 15:20:36 -07:00
|
|
|
*/
|
2007-02-16 02:27:58 -07:00
|
|
|
clear_local_APIC();
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
|
|
|
* Enable APIC.
|
|
|
|
*/
|
|
|
|
value = apic_read(APIC_SPIV);
|
|
|
|
value &= ~APIC_VECTOR_MASK;
|
|
|
|
value |= APIC_SPIV_APIC_ENABLED;
|
|
|
|
|
|
|
|
/* This bit is reserved on P4/Xeon and should be cleared */
|
|
|
|
if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
|
|
|
|
(boot_cpu_data.x86 == 15))
|
|
|
|
value &= ~APIC_SPIV_FOCUS_DISABLED;
|
|
|
|
else
|
|
|
|
value |= APIC_SPIV_FOCUS_DISABLED;
|
|
|
|
value |= SPURIOUS_APIC_VECTOR;
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_SPIV, value);
|
2007-02-16 02:27:58 -07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Set up the virtual wire mode.
|
|
|
|
*/
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_LVT0, APIC_DM_EXTINT);
|
2007-02-16 02:27:58 -07:00
|
|
|
value = APIC_DM_NMI;
|
|
|
|
if (!lapic_is_integrated()) /* 82489DX */
|
|
|
|
value |= APIC_LVT_LEVEL_TRIGGER;
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_LVT1, value);
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
2008-04-23 04:20:56 -07:00
|
|
|
static void __cpuinit lapic_setup_esr(void)
|
2008-03-19 10:25:48 -07:00
|
|
|
{
|
|
|
|
unsigned long oldvalue, value, maxlvt;
|
|
|
|
if (lapic_is_integrated() && !esr_disable) {
|
|
|
|
/* !82489DX */
|
|
|
|
maxlvt = lapic_get_maxlvt();
|
|
|
|
if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
|
|
|
|
apic_write(APIC_ESR, 0);
|
|
|
|
oldvalue = apic_read(APIC_ESR);
|
|
|
|
|
|
|
|
/* enables sending errors */
|
|
|
|
value = ERROR_APIC_VECTOR;
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_LVTERR, value);
|
2008-03-19 10:25:48 -07:00
|
|
|
/*
|
|
|
|
* spec says clear errors after enabling vector.
|
|
|
|
*/
|
|
|
|
if (maxlvt > 3)
|
|
|
|
apic_write(APIC_ESR, 0);
|
|
|
|
value = apic_read(APIC_ESR);
|
|
|
|
if (value != oldvalue)
|
|
|
|
apic_printk(APIC_VERBOSE, "ESR value before enabling "
|
|
|
|
"vector: 0x%08lx after: 0x%08lx\n",
|
|
|
|
oldvalue, value);
|
|
|
|
} else {
|
|
|
|
if (esr_disable)
|
|
|
|
/*
|
|
|
|
* Something untraceable is creating bad interrupts on
|
|
|
|
* secondary quads ... for the moment, just leave the
|
|
|
|
* ESR disabled - we can't do anything useful with the
|
|
|
|
* errors anyway - mbligh
|
|
|
|
*/
|
|
|
|
printk(KERN_INFO "Leaving ESR disabled.\n");
|
|
|
|
else
|
|
|
|
printk(KERN_INFO "No ESR for 82489DX.\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/**
|
|
|
|
* setup_local_APIC - setup the local APIC
|
2005-04-16 15:20:36 -07:00
|
|
|
*/
|
2007-12-19 15:20:18 -07:00
|
|
|
void __cpuinit setup_local_APIC(void)
|
2007-02-16 02:27:58 -07:00
|
|
|
{
|
2008-03-19 10:25:48 -07:00
|
|
|
unsigned long value, integrated;
|
2007-02-16 02:27:58 -07:00
|
|
|
int i, j;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/* Pound the ESR really hard over the head with a big hammer - mbligh */
|
|
|
|
if (esr_disable) {
|
|
|
|
apic_write(APIC_ESR, 0);
|
|
|
|
apic_write(APIC_ESR, 0);
|
|
|
|
apic_write(APIC_ESR, 0);
|
|
|
|
apic_write(APIC_ESR, 0);
|
|
|
|
}
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
integrated = lapic_is_integrated();
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
|
|
|
* Double-check whether this APIC is really registered.
|
|
|
|
*/
|
|
|
|
if (!apic_id_registered())
|
2008-07-10 07:29:28 -07:00
|
|
|
WARN_ON_ONCE(1);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
|
|
|
* Intel recommends to set DFR, LDR and TPR before enabling
|
|
|
|
* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
|
|
|
|
* document number 292116). So here it goes...
|
|
|
|
*/
|
|
|
|
init_apic_ldr();
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
|
|
|
* Set Task Priority to 'accept all'. We never change this
|
|
|
|
* later on.
|
|
|
|
*/
|
|
|
|
value = apic_read(APIC_TASKPRI);
|
|
|
|
value &= ~APIC_TPRI_MASK;
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_TASKPRI, value);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
|
|
|
* After a crash, we no longer service the interrupts and a pending
|
|
|
|
* interrupt from previous kernel might still have ISR bit set.
|
|
|
|
*
|
|
|
|
* Most probably by now CPU has serviced that pending interrupt and
|
|
|
|
* it might not have done the ack_APIC_irq() because it thought,
|
|
|
|
* interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
|
|
|
|
* does not clear the ISR bit and cpu thinks it has already serivced
|
|
|
|
* the interrupt. Hence a vector might get locked. It was noticed
|
|
|
|
* for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
|
|
|
|
*/
|
|
|
|
for (i = APIC_ISR_NR - 1; i >= 0; i--) {
|
|
|
|
value = apic_read(APIC_ISR + i*0x10);
|
|
|
|
for (j = 31; j >= 0; j--) {
|
|
|
|
if (value & (1<<j))
|
|
|
|
ack_APIC_irq();
|
|
|
|
}
|
|
|
|
}
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
|
|
|
* Now that we are all set up, enable the APIC
|
|
|
|
*/
|
|
|
|
value = apic_read(APIC_SPIV);
|
|
|
|
value &= ~APIC_VECTOR_MASK;
|
|
|
|
/*
|
|
|
|
* Enable APIC
|
|
|
|
*/
|
|
|
|
value |= APIC_SPIV_APIC_ENABLED;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
|
|
|
* Some unknown Intel IO/APIC (or APIC) errata is biting us with
|
|
|
|
* certain networking cards. If high frequency interrupts are
|
|
|
|
* happening on a particular IOAPIC pin, plus the IOAPIC routing
|
|
|
|
* entry is masked/unmasked at a high rate as well then sooner or
|
|
|
|
* later IOAPIC line gets 'stuck', no more interrupts are received
|
|
|
|
* from the device. If focus CPU is disabled then the hang goes
|
|
|
|
* away, oh well :-(
|
|
|
|
*
|
|
|
|
* [ This bug can be reproduced easily with a level-triggered
|
|
|
|
* PCI Ne2000 networking cards and PII/PIII processors, dual
|
|
|
|
* BX chipset. ]
|
|
|
|
*/
|
|
|
|
/*
|
|
|
|
* Actually disabling the focus CPU check just makes the hang less
|
|
|
|
* frequent as it makes the interrupt distributon model be more
|
|
|
|
* like LRU than MRU (the short-term load is more even across CPUs).
|
|
|
|
* See also the comment in end_level_ioapic_irq(). --macro
|
|
|
|
*/
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/* Enable focus processor (bit==0) */
|
|
|
|
value &= ~APIC_SPIV_FOCUS_DISABLED;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
|
|
|
* Set spurious IRQ vector
|
|
|
|
*/
|
|
|
|
value |= SPURIOUS_APIC_VECTOR;
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_SPIV, value);
|
2007-02-16 02:27:58 -07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Set up LVT0, LVT1:
|
|
|
|
*
|
|
|
|
* set up through-local-APIC on the BP's LINT0. This is not
|
2007-10-19 16:13:56 -07:00
|
|
|
* strictly necessary in pure symmetric-IO mode, but sometimes
|
2007-02-16 02:27:58 -07:00
|
|
|
* we delegate interrupts to the 8259A.
|
|
|
|
*/
|
|
|
|
/*
|
|
|
|
* TODO: set up through-local-APIC from through-I/O-APIC? --macro
|
|
|
|
*/
|
|
|
|
value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
|
|
|
|
if (!smp_processor_id() && (pic_mode || !value)) {
|
|
|
|
value = APIC_DM_EXTINT;
|
|
|
|
apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
|
|
|
|
smp_processor_id());
|
|
|
|
} else {
|
|
|
|
value = APIC_DM_EXTINT | APIC_LVT_MASKED;
|
|
|
|
apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
|
|
|
|
smp_processor_id());
|
|
|
|
}
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_LVT0, value);
|
2007-02-16 02:27:58 -07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* only the BP should see the LINT1 NMI signal, obviously.
|
|
|
|
*/
|
|
|
|
if (!smp_processor_id())
|
|
|
|
value = APIC_DM_NMI;
|
|
|
|
else
|
|
|
|
value = APIC_DM_NMI | APIC_LVT_MASKED;
|
|
|
|
if (!integrated) /* 82489DX */
|
|
|
|
value |= APIC_LVT_LEVEL_TRIGGER;
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_LVT1, value);
|
2008-03-19 10:25:49 -07:00
|
|
|
}
|
2007-02-16 02:27:58 -07:00
|
|
|
|
2008-03-19 10:25:49 -07:00
|
|
|
void __cpuinit end_local_APIC_setup(void)
|
|
|
|
{
|
|
|
|
unsigned long value;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2008-03-19 10:25:49 -07:00
|
|
|
lapic_setup_esr();
|
2007-02-16 02:28:04 -07:00
|
|
|
/* Disable the local apic timer */
|
|
|
|
value = apic_read(APIC_LVTT);
|
|
|
|
value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_LVTT, value);
|
2007-02-16 02:28:04 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
setup_apic_nmi_watchdog(NULL);
|
|
|
|
apic_pm_activate();
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
|
|
|
* Detect and initialize APIC
|
|
|
|
*/
|
2008-01-30 05:32:35 -07:00
|
|
|
static int __init detect_init_APIC(void)
|
2005-04-16 15:20:36 -07:00
|
|
|
{
|
|
|
|
u32 h, l, features;
|
|
|
|
|
|
|
|
/* Disabled by kernel option? */
|
2008-06-29 00:06:37 -07:00
|
|
|
if (disable_apic)
|
2005-04-16 15:20:36 -07:00
|
|
|
return -1;
|
|
|
|
|
|
|
|
switch (boot_cpu_data.x86_vendor) {
|
|
|
|
case X86_VENDOR_AMD:
|
|
|
|
if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
|
2007-02-16 02:27:58 -07:00
|
|
|
(boot_cpu_data.x86 == 15))
|
2005-04-16 15:20:36 -07:00
|
|
|
break;
|
|
|
|
goto no_apic;
|
|
|
|
case X86_VENDOR_INTEL:
|
|
|
|
if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
|
|
|
|
(boot_cpu_data.x86 == 5 && cpu_has_apic))
|
|
|
|
break;
|
|
|
|
goto no_apic;
|
|
|
|
default:
|
|
|
|
goto no_apic;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!cpu_has_apic) {
|
|
|
|
/*
|
2007-02-16 02:27:58 -07:00
|
|
|
* Over-ride BIOS and try to enable the local APIC only if
|
|
|
|
* "lapic" specified.
|
2005-04-16 15:20:36 -07:00
|
|
|
*/
|
2008-06-29 00:06:37 -07:00
|
|
|
if (!force_enable_local_apic) {
|
2007-02-16 02:27:58 -07:00
|
|
|
printk(KERN_INFO "Local APIC disabled by BIOS -- "
|
2005-04-16 15:20:36 -07:00
|
|
|
"you can enable it with \"lapic\"\n");
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
/*
|
2007-02-16 02:27:58 -07:00
|
|
|
* Some BIOSes disable the local APIC in the APIC_BASE
|
|
|
|
* MSR. This can only be done in software for Intel P6 or later
|
|
|
|
* and AMD K7 (Model > 1) or later.
|
2005-04-16 15:20:36 -07:00
|
|
|
*/
|
|
|
|
rdmsr(MSR_IA32_APICBASE, l, h);
|
|
|
|
if (!(l & MSR_IA32_APICBASE_ENABLE)) {
|
2007-02-16 02:27:58 -07:00
|
|
|
printk(KERN_INFO
|
|
|
|
"Local APIC disabled by BIOS -- reenabling.\n");
|
2005-04-16 15:20:36 -07:00
|
|
|
l &= ~MSR_IA32_APICBASE_BASE;
|
|
|
|
l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
|
|
|
|
wrmsr(MSR_IA32_APICBASE, l, h);
|
|
|
|
enabled_via_apicbase = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* The APIC feature bit should now be enabled
|
|
|
|
* in `cpuid'
|
|
|
|
*/
|
|
|
|
features = cpuid_edx(1);
|
|
|
|
if (!(features & (1 << X86_FEATURE_APIC))) {
|
2007-02-16 02:27:58 -07:00
|
|
|
printk(KERN_WARNING "Could not enable APIC!\n");
|
2005-04-16 15:20:36 -07:00
|
|
|
return -1;
|
|
|
|
}
|
2008-01-30 05:30:55 -07:00
|
|
|
set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
|
2005-04-16 15:20:36 -07:00
|
|
|
mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
|
|
|
|
|
|
|
|
/* The BIOS may have set up the APIC at some other address */
|
|
|
|
rdmsr(MSR_IA32_APICBASE, l, h);
|
2007-02-16 02:27:58 -07:00
|
|
|
if (l & MSR_IA32_APICBASE_ENABLE)
|
|
|
|
mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
printk(KERN_INFO "Found and enabled local APIC!\n");
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
apic_pm_activate();
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
return 0;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
no_apic:
|
|
|
|
printk(KERN_INFO "No local APIC present or hardware disabled\n");
|
|
|
|
return -1;
|
|
|
|
}
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/**
|
|
|
|
* init_apic_mappings - initialize APIC mappings
|
|
|
|
*/
|
|
|
|
void __init init_apic_mappings(void)
|
2005-04-16 15:20:36 -07:00
|
|
|
{
|
|
|
|
/*
|
2007-02-16 02:27:58 -07:00
|
|
|
* If no local APIC can be found then set up a fake all
|
|
|
|
* zeroes page to simulate the local APIC and another
|
|
|
|
* one for the IO-APIC.
|
2005-04-16 15:20:36 -07:00
|
|
|
*/
|
2007-02-16 02:27:58 -07:00
|
|
|
if (!smp_found_config && detect_init_APIC()) {
|
|
|
|
apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
|
|
|
|
apic_phys = __pa(apic_phys);
|
|
|
|
} else
|
|
|
|
apic_phys = mp_lapic_addr;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
|
|
|
|
printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE,
|
|
|
|
apic_phys);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
|
|
|
* Fetch the APIC ID of the BSP in case we have a
|
|
|
|
* default configuration (or the MP table is broken).
|
|
|
|
*/
|
|
|
|
if (boot_cpu_physical_apicid == -1U)
|
2008-07-11 18:44:16 -07:00
|
|
|
boot_cpu_physical_apicid = read_apic_id();
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
}
|
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
|
|
|
* This initializes the IO-APIC and APIC hardware if this is
|
|
|
|
* a UP kernel.
|
|
|
|
*/
|
2008-03-27 13:54:31 -07:00
|
|
|
|
|
|
|
int apic_version[MAX_APICS];
|
|
|
|
|
2008-01-30 05:32:35 -07:00
|
|
|
int __init APIC_init_uniprocessor(void)
|
2005-04-16 15:20:36 -07:00
|
|
|
{
|
2008-06-29 00:06:37 -07:00
|
|
|
if (disable_apic)
|
2008-01-30 05:30:55 -07:00
|
|
|
clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
if (!smp_found_config && !cpu_has_apic)
|
|
|
|
return -1;
|
2006-01-11 14:44:21 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
|
|
|
* Complain if the BIOS pretends there is one.
|
|
|
|
*/
|
|
|
|
if (!cpu_has_apic &&
|
|
|
|
APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
|
|
|
|
printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
|
|
|
|
boot_cpu_physical_apicid);
|
2008-01-30 05:30:55 -07:00
|
|
|
clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
|
2007-02-16 02:27:58 -07:00
|
|
|
return -1;
|
2006-01-11 14:44:21 -07:00
|
|
|
}
|
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
verify_local_APIC();
|
2006-01-11 14:44:21 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
connect_bsp_APIC();
|
2006-01-11 14:44:21 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
|
|
|
* Hack: In case of kdump, after a crash, kernel might be booting
|
|
|
|
* on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
|
|
|
|
* might be zero if read from MP tables. Get it from LAPIC.
|
|
|
|
*/
|
|
|
|
#ifdef CONFIG_CRASH_DUMP
|
2008-07-11 18:44:16 -07:00
|
|
|
boot_cpu_physical_apicid = read_apic_id();
|
2007-02-16 02:27:58 -07:00
|
|
|
#endif
|
2008-06-19 19:51:05 -07:00
|
|
|
physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
setup_local_APIC();
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2008-06-05 19:27:49 -07:00
|
|
|
#ifdef CONFIG_X86_IO_APIC
|
|
|
|
if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
|
|
|
|
#endif
|
|
|
|
localise_nmi_watchdog();
|
2008-03-19 10:25:49 -07:00
|
|
|
end_local_APIC_setup();
|
2007-02-16 02:27:58 -07:00
|
|
|
#ifdef CONFIG_X86_IO_APIC
|
|
|
|
if (smp_found_config)
|
|
|
|
if (!skip_ioapic_setup && nr_ioapics)
|
|
|
|
setup_IO_APIC();
|
2005-04-16 15:20:36 -07:00
|
|
|
#endif
|
2007-02-16 02:27:58 -07:00
|
|
|
setup_boot_clock();
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
return 0;
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
|
|
|
* Local APIC interrupts
|
|
|
|
*/
|
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
/*
|
|
|
|
* This interrupt should _never_ happen with our APIC/SMP architecture
|
|
|
|
*/
|
2007-02-16 02:28:04 -07:00
|
|
|
void smp_spurious_interrupt(struct pt_regs *regs)
|
2005-04-16 15:20:36 -07:00
|
|
|
{
|
|
|
|
unsigned long v;
|
|
|
|
|
|
|
|
irq_enter();
|
|
|
|
/*
|
|
|
|
* Check if this really is a spurious interrupt and ACK it
|
|
|
|
* if it is a vectored one. Just in case...
|
|
|
|
* Spurious interrupts should not be ACKed.
|
|
|
|
*/
|
|
|
|
v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
|
|
|
|
if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
|
|
|
|
ack_APIC_irq();
|
|
|
|
|
|
|
|
/* see sw-dev-man vol 3, chapter 7.4.13.5 */
|
2007-02-16 02:27:58 -07:00
|
|
|
printk(KERN_INFO "spurious APIC interrupt on CPU#%d, "
|
|
|
|
"should never happen.\n", smp_processor_id());
|
2007-10-17 09:04:40 -07:00
|
|
|
__get_cpu_var(irq_stat).irq_spurious_count++;
|
2005-04-16 15:20:36 -07:00
|
|
|
irq_exit();
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This interrupt should never happen with our APIC/SMP architecture
|
|
|
|
*/
|
2007-02-16 02:28:04 -07:00
|
|
|
void smp_error_interrupt(struct pt_regs *regs)
|
2005-04-16 15:20:36 -07:00
|
|
|
{
|
|
|
|
unsigned long v, v1;
|
|
|
|
|
|
|
|
irq_enter();
|
|
|
|
/* First tickle the hardware, only then report what went on. -- REW */
|
|
|
|
v = apic_read(APIC_ESR);
|
|
|
|
apic_write(APIC_ESR, 0);
|
|
|
|
v1 = apic_read(APIC_ESR);
|
|
|
|
ack_APIC_irq();
|
|
|
|
atomic_inc(&irq_err_count);
|
|
|
|
|
|
|
|
/* Here is what the APIC error bits mean:
|
|
|
|
0: Send CS error
|
|
|
|
1: Receive CS error
|
|
|
|
2: Send accept error
|
|
|
|
3: Receive accept error
|
|
|
|
4: Reserved
|
|
|
|
5: Send illegal vector
|
|
|
|
6: Received illegal vector
|
|
|
|
7: Illegal register address
|
|
|
|
*/
|
2008-01-30 05:32:36 -07:00
|
|
|
printk(KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n",
|
2007-02-16 02:27:58 -07:00
|
|
|
smp_processor_id(), v , v1);
|
2005-04-16 15:20:36 -07:00
|
|
|
irq_exit();
|
|
|
|
}
|
|
|
|
|
2008-03-19 10:25:33 -07:00
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
void __init smp_intr_init(void)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* IRQ0 must be given a fixed assignment and initialized,
|
|
|
|
* because it's used before the IO-APIC is set up.
|
|
|
|
*/
|
|
|
|
set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The reschedule interrupt is a CPU-to-CPU reschedule-helper
|
|
|
|
* IPI, driven by wakeup.
|
|
|
|
*/
|
2008-04-15 13:36:56 -07:00
|
|
|
alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
|
2008-03-19 10:25:33 -07:00
|
|
|
|
|
|
|
/* IPI for invalidation */
|
2008-04-15 13:36:56 -07:00
|
|
|
alloc_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
|
2008-03-19 10:25:33 -07:00
|
|
|
|
|
|
|
/* IPI for generic function call */
|
2008-04-15 13:36:56 -07:00
|
|
|
alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
|
2008-06-26 02:21:54 -07:00
|
|
|
|
|
|
|
/* IPI for single call function */
|
|
|
|
set_intr_gate(CALL_FUNCTION_SINGLE_VECTOR,
|
|
|
|
call_function_single_interrupt);
|
2008-03-19 10:25:33 -07:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
/*
|
2007-02-16 02:27:58 -07:00
|
|
|
* Initialize APIC interrupts
|
2005-04-16 15:20:36 -07:00
|
|
|
*/
|
2007-02-16 02:27:58 -07:00
|
|
|
void __init apic_intr_init(void)
|
2005-04-16 15:20:36 -07:00
|
|
|
{
|
2007-02-16 02:27:58 -07:00
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
smp_intr_init();
|
|
|
|
#endif
|
|
|
|
/* self generated IPI for local APIC timer */
|
2008-04-15 13:36:56 -07:00
|
|
|
alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/* IPI vectors for APIC spurious and error interrupts */
|
2008-04-15 13:36:56 -07:00
|
|
|
alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
|
|
|
|
alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/* thermal monitor LVT interrupt */
|
|
|
|
#ifdef CONFIG_X86_MCE_P4THERMAL
|
2008-04-15 13:36:56 -07:00
|
|
|
alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
|
2007-02-16 02:27:58 -07:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* connect_bsp_APIC - attach the APIC to the interrupt system
|
|
|
|
*/
|
|
|
|
void __init connect_bsp_APIC(void)
|
|
|
|
{
|
|
|
|
if (pic_mode) {
|
|
|
|
/*
|
|
|
|
* Do not trust the local APIC being empty at bootup.
|
|
|
|
*/
|
|
|
|
clear_local_APIC();
|
|
|
|
/*
|
|
|
|
* PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
|
|
|
|
* local APIC to INT and NMI lines.
|
|
|
|
*/
|
|
|
|
apic_printk(APIC_VERBOSE, "leaving PIC mode, "
|
|
|
|
"enabling APIC mode.\n");
|
|
|
|
outb(0x70, 0x22);
|
|
|
|
outb(0x01, 0x23);
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
2007-02-16 02:27:58 -07:00
|
|
|
enable_apic_mode();
|
|
|
|
}
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/**
|
|
|
|
* disconnect_bsp_APIC - detach the APIC from the interrupt system
|
|
|
|
* @virt_wire_setup: indicates, whether virtual wire mode is selected
|
|
|
|
*
|
|
|
|
* Virtual wire mode is necessary to deliver legacy interrupts even when the
|
|
|
|
* APIC is disabled.
|
|
|
|
*/
|
|
|
|
void disconnect_bsp_APIC(int virt_wire_setup)
|
|
|
|
{
|
|
|
|
if (pic_mode) {
|
|
|
|
/*
|
|
|
|
* Put the board back into PIC mode (has an effect only on
|
|
|
|
* certain older boards). Note that APIC interrupts, including
|
|
|
|
* IPIs, won't work beyond this point! The only exception are
|
|
|
|
* INIT IPIs.
|
|
|
|
*/
|
|
|
|
apic_printk(APIC_VERBOSE, "disabling APIC mode, "
|
|
|
|
"entering PIC mode.\n");
|
|
|
|
outb(0x70, 0x22);
|
|
|
|
outb(0x00, 0x23);
|
|
|
|
} else {
|
|
|
|
/* Go back to Virtual Wire compatibility mode */
|
|
|
|
unsigned long value;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/* For the spurious interrupt use vector F, and enable it */
|
|
|
|
value = apic_read(APIC_SPIV);
|
|
|
|
value &= ~APIC_VECTOR_MASK;
|
|
|
|
value |= APIC_SPIV_APIC_ENABLED;
|
|
|
|
value |= 0xf;
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_SPIV, value);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
if (!virt_wire_setup) {
|
|
|
|
/*
|
|
|
|
* For LVT0 make it edge triggered, active high,
|
|
|
|
* external and enabled
|
|
|
|
*/
|
|
|
|
value = apic_read(APIC_LVT0);
|
|
|
|
value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
|
|
|
|
APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
|
2008-01-30 05:32:36 -07:00
|
|
|
APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
|
2007-02-16 02:27:58 -07:00
|
|
|
value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
|
|
|
|
value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_LVT0, value);
|
2007-02-16 02:27:58 -07:00
|
|
|
} else {
|
|
|
|
/* Disable LVT0 */
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_LVT0, APIC_LVT_MASKED);
|
2007-02-16 02:27:58 -07:00
|
|
|
}
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
|
|
|
* For LVT1 make it edge triggered, active high, nmi and
|
|
|
|
* enabled
|
|
|
|
*/
|
|
|
|
value = apic_read(APIC_LVT1);
|
|
|
|
value &= ~(
|
|
|
|
APIC_MODE_MASK | APIC_SEND_PENDING |
|
|
|
|
APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
|
|
|
|
APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
|
|
|
|
value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
|
|
|
|
value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 11:15:30 -07:00
|
|
|
apic_write(APIC_LVT1, value);
|
2007-02-16 02:27:58 -07:00
|
|
|
}
|
|
|
|
}
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2008-03-27 13:55:22 -07:00
|
|
|
unsigned int __cpuinitdata maxcpus = NR_CPUS;
|
|
|
|
|
|
|
|
void __cpuinit generic_processor_info(int apicid, int version)
|
|
|
|
{
|
|
|
|
int cpu;
|
|
|
|
cpumask_t tmp_map;
|
|
|
|
physid_mask_t phys_cpu;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Validate version
|
|
|
|
*/
|
|
|
|
if (version == 0x0) {
|
|
|
|
printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
|
|
|
|
"fixing up to 0x10. (tell your hw vendor)\n",
|
|
|
|
version);
|
|
|
|
version = 0x10;
|
|
|
|
}
|
|
|
|
apic_version[apicid] = version;
|
|
|
|
|
|
|
|
phys_cpu = apicid_to_cpu_present(apicid);
|
|
|
|
physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
|
|
|
|
|
|
|
|
if (num_processors >= NR_CPUS) {
|
|
|
|
printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
|
|
|
|
" Processor ignored.\n", NR_CPUS);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (num_processors >= maxcpus) {
|
|
|
|
printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
|
|
|
|
" Processor ignored.\n", maxcpus);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
num_processors++;
|
|
|
|
cpus_complement(tmp_map, cpu_present_map);
|
|
|
|
cpu = first_cpu(tmp_map);
|
|
|
|
|
|
|
|
if (apicid == boot_cpu_physical_apicid)
|
|
|
|
/*
|
|
|
|
* x86_bios_cpu_apicid is required to have processors listed
|
|
|
|
* in same order as logical cpu numbers. Hence the first
|
|
|
|
* entry is BSP, and so on.
|
|
|
|
*/
|
|
|
|
cpu = 0;
|
|
|
|
|
2008-06-08 18:29:22 -07:00
|
|
|
if (apicid > max_physical_apicid)
|
|
|
|
max_physical_apicid = apicid;
|
|
|
|
|
2008-03-27 13:55:22 -07:00
|
|
|
/*
|
|
|
|
* Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
|
|
|
|
* but we need to work other dependencies like SMP_SUSPEND etc
|
|
|
|
* before this can be done without some confusion.
|
|
|
|
* if (CPU_HOTPLUG_ENABLED || num_processors > 8)
|
|
|
|
* - Ashok Raj <ashok.raj@intel.com>
|
|
|
|
*/
|
2008-06-08 18:29:22 -07:00
|
|
|
if (max_physical_apicid >= 8) {
|
2008-03-27 13:55:22 -07:00
|
|
|
switch (boot_cpu_data.x86_vendor) {
|
|
|
|
case X86_VENDOR_INTEL:
|
|
|
|
if (!APIC_XAPIC(version)) {
|
|
|
|
def_to_bigsmp = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
/* If P4 and above fall through */
|
|
|
|
case X86_VENDOR_AMD:
|
|
|
|
def_to_bigsmp = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
/* are we being called early in kernel startup? */
|
x86: cleanup early per cpu variables/accesses v4
* Introduce a new PER_CPU macro called "EARLY_PER_CPU". This is
used by some per_cpu variables that are initialized and accessed
before there are per_cpu areas allocated.
["Early" in respect to per_cpu variables is "earlier than the per_cpu
areas have been setup".]
This patchset adds these new macros:
DEFINE_EARLY_PER_CPU(_type, _name, _initvalue)
EXPORT_EARLY_PER_CPU_SYMBOL(_name)
DECLARE_EARLY_PER_CPU(_type, _name)
early_per_cpu_ptr(_name)
early_per_cpu_map(_name, _idx)
early_per_cpu(_name, _cpu)
The DEFINE macro defines the per_cpu variable as well as the early
map and pointer. It also initializes the per_cpu variable and map
elements to "_initvalue". The early_* macros provide access to
the initial map (usually setup during system init) and the early
pointer. This pointer is initialized to point to the early map
but is then NULL'ed when the actual per_cpu areas are setup. After
that the per_cpu variable is the correct access to the variable.
The early_per_cpu() macro is not very efficient but does show how to
access the variable if you have a function that can be called both
"early" and "late". It tests the early ptr to be NULL, and if not
then it's still valid. Otherwise, the per_cpu variable is used
instead:
#define early_per_cpu(_name, _cpu) \
(early_per_cpu_ptr(_name) ? \
early_per_cpu_ptr(_name)[_cpu] : \
per_cpu(_name, _cpu))
A better method is to actually check the pointer manually. In the
case below, numa_set_node can be called both "early" and "late":
void __cpuinit numa_set_node(int cpu, int node)
{
int *cpu_to_node_map = early_per_cpu_ptr(x86_cpu_to_node_map);
if (cpu_to_node_map)
cpu_to_node_map[cpu] = node;
else
per_cpu(x86_cpu_to_node_map, cpu) = node;
}
* Add a flag "arch_provides_topology_pointers" that indicates pointers
to topology cpumask_t maps are available. Otherwise, use the function
returning the cpumask_t value. This is useful if cpumask_t set size
is very large to avoid copying data on to/off of the stack.
* The coverage of CONFIG_DEBUG_PER_CPU_MAPS has been increased while
the non-debug case has been optimized a bit.
* Remove an unreferenced compiler warning in drivers/base/topology.c
* Clean up #ifdef in setup.c
For inclusion into sched-devel/latest tree.
Based on:
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
+ sched-devel/latest .../mingo/linux-2.6-sched-devel.git
Signed-off-by: Mike Travis <travis@sgi.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-05-12 12:21:12 -07:00
|
|
|
if (early_per_cpu_ptr(x86_cpu_to_apicid)) {
|
|
|
|
u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid);
|
|
|
|
u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
|
2008-03-27 13:55:22 -07:00
|
|
|
|
|
|
|
cpu_to_apicid[cpu] = apicid;
|
|
|
|
bios_cpu_apicid[cpu] = apicid;
|
|
|
|
} else {
|
|
|
|
per_cpu(x86_cpu_to_apicid, cpu) = apicid;
|
|
|
|
per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
cpu_set(cpu, cpu_possible_map);
|
|
|
|
cpu_set(cpu, cpu_present_map);
|
|
|
|
}
|
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
|
|
|
* Power management
|
|
|
|
*/
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
|
|
|
|
static struct {
|
|
|
|
int active;
|
|
|
|
/* r/w apic fields */
|
|
|
|
unsigned int apic_id;
|
|
|
|
unsigned int apic_taskpri;
|
|
|
|
unsigned int apic_ldr;
|
|
|
|
unsigned int apic_dfr;
|
|
|
|
unsigned int apic_spiv;
|
|
|
|
unsigned int apic_lvtt;
|
|
|
|
unsigned int apic_lvtpc;
|
|
|
|
unsigned int apic_lvt0;
|
|
|
|
unsigned int apic_lvt1;
|
|
|
|
unsigned int apic_lvterr;
|
|
|
|
unsigned int apic_tmict;
|
|
|
|
unsigned int apic_tdcr;
|
|
|
|
unsigned int apic_thmr;
|
|
|
|
} apic_pm_state;
|
|
|
|
|
|
|
|
static int lapic_suspend(struct sys_device *dev, pm_message_t state)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
int maxlvt;
|
|
|
|
|
|
|
|
if (!apic_pm_state.active)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
maxlvt = lapic_get_maxlvt();
|
|
|
|
|
|
|
|
apic_pm_state.apic_id = apic_read(APIC_ID);
|
|
|
|
apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
|
|
|
|
apic_pm_state.apic_ldr = apic_read(APIC_LDR);
|
|
|
|
apic_pm_state.apic_dfr = apic_read(APIC_DFR);
|
|
|
|
apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
|
|
|
|
apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
|
|
|
|
if (maxlvt >= 4)
|
|
|
|
apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
|
|
|
|
apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
|
|
|
|
apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
|
|
|
|
apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
|
|
|
|
apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
|
|
|
|
apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
|
|
|
|
#ifdef CONFIG_X86_MCE_P4THERMAL
|
|
|
|
if (maxlvt >= 5)
|
|
|
|
apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
|
2005-04-16 15:20:36 -07:00
|
|
|
#endif
|
2005-10-31 20:16:17 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
local_irq_save(flags);
|
|
|
|
disable_local_APIC();
|
|
|
|
local_irq_restore(flags);
|
2005-10-31 20:16:17 -07:00
|
|
|
return 0;
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
2006-09-26 01:52:32 -07:00
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
static int lapic_resume(struct sys_device *dev)
|
2006-09-26 01:52:32 -07:00
|
|
|
{
|
2007-02-16 02:27:58 -07:00
|
|
|
unsigned int l, h;
|
|
|
|
unsigned long flags;
|
|
|
|
int maxlvt;
|
|
|
|
|
|
|
|
if (!apic_pm_state.active)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
maxlvt = lapic_get_maxlvt();
|
|
|
|
|
|
|
|
local_irq_save(flags);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Make sure the APICBASE points to the right address
|
|
|
|
*
|
|
|
|
* FIXME! This will be wrong if we ever support suspend on
|
|
|
|
* SMP! We'll need to do this as part of the CPU restore!
|
|
|
|
*/
|
|
|
|
rdmsr(MSR_IA32_APICBASE, l, h);
|
|
|
|
l &= ~MSR_IA32_APICBASE_BASE;
|
|
|
|
l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
|
|
|
|
wrmsr(MSR_IA32_APICBASE, l, h);
|
|
|
|
|
|
|
|
apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
|
|
|
|
apic_write(APIC_ID, apic_pm_state.apic_id);
|
|
|
|
apic_write(APIC_DFR, apic_pm_state.apic_dfr);
|
|
|
|
apic_write(APIC_LDR, apic_pm_state.apic_ldr);
|
|
|
|
apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
|
|
|
|
apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
|
|
|
|
apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
|
|
|
|
apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
|
|
|
|
#ifdef CONFIG_X86_MCE_P4THERMAL
|
|
|
|
if (maxlvt >= 5)
|
|
|
|
apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
|
|
|
|
#endif
|
|
|
|
if (maxlvt >= 4)
|
|
|
|
apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
|
|
|
|
apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
|
|
|
|
apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
|
|
|
|
apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
|
|
|
|
apic_write(APIC_ESR, 0);
|
|
|
|
apic_read(APIC_ESR);
|
|
|
|
apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
|
|
|
|
apic_write(APIC_ESR, 0);
|
|
|
|
apic_read(APIC_ESR);
|
|
|
|
local_irq_restore(flags);
|
2006-09-26 01:52:32 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
/*
|
|
|
|
* This device has no shutdown method - fully functioning local APICs
|
|
|
|
* are needed on every CPU up until machine_halt/restart/poweroff.
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct sysdev_class lapic_sysclass = {
|
2007-12-19 18:09:39 -07:00
|
|
|
.name = "lapic",
|
2007-02-16 02:27:58 -07:00
|
|
|
.resume = lapic_resume,
|
|
|
|
.suspend = lapic_suspend,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct sys_device device_lapic = {
|
|
|
|
.id = 0,
|
|
|
|
.cls = &lapic_sysclass,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void __devinit apic_pm_activate(void)
|
2006-09-26 01:52:32 -07:00
|
|
|
{
|
2007-02-16 02:27:58 -07:00
|
|
|
apic_pm_state.active = 1;
|
2006-09-26 01:52:32 -07:00
|
|
|
}
|
|
|
|
|
2007-02-16 02:27:58 -07:00
|
|
|
static int __init init_lapic_sysfs(void)
|
|
|
|
{
|
|
|
|
int error;
|
|
|
|
|
|
|
|
if (!cpu_has_apic)
|
|
|
|
return 0;
|
|
|
|
/* XXX: remove suspend/resume procs if !apic_pm_state.active? */
|
|
|
|
|
|
|
|
error = sysdev_class_register(&lapic_sysclass);
|
|
|
|
if (!error)
|
|
|
|
error = sysdev_register(&device_lapic);
|
|
|
|
return error;
|
|
|
|
}
|
|
|
|
device_initcall(init_lapic_sysfs);
|
|
|
|
|
|
|
|
#else /* CONFIG_PM */
|
|
|
|
|
|
|
|
static void apic_pm_activate(void) { }
|
|
|
|
|
|
|
|
#endif /* CONFIG_PM */
|
2008-01-30 05:30:20 -07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* APIC command line parameters
|
|
|
|
*/
|
|
|
|
static int __init parse_lapic(char *arg)
|
|
|
|
{
|
2008-06-29 00:06:37 -07:00
|
|
|
force_enable_local_apic = 1;
|
2008-01-30 05:30:20 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
early_param("lapic", parse_lapic);
|
|
|
|
|
|
|
|
static int __init parse_nolapic(char *arg)
|
|
|
|
{
|
2008-06-29 00:06:37 -07:00
|
|
|
disable_apic = 1;
|
2008-01-30 05:30:55 -07:00
|
|
|
clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
|
2008-01-30 05:30:20 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
early_param("nolapic", parse_nolapic);
|
|
|
|
|
|
|
|
static int __init parse_disable_lapic_timer(char *arg)
|
|
|
|
{
|
|
|
|
local_apic_timer_disabled = 1;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
early_param("nolapic_timer", parse_disable_lapic_timer);
|
|
|
|
|
|
|
|
static int __init parse_lapic_timer_c2_ok(char *arg)
|
|
|
|
{
|
|
|
|
local_apic_timer_c2_ok = 1;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
|
|
|
|
|
|
|
|
static int __init apic_set_verbosity(char *str)
|
|
|
|
{
|
|
|
|
if (strcmp("debug", str) == 0)
|
|
|
|
apic_verbosity = APIC_DEBUG;
|
|
|
|
else if (strcmp("verbose", str) == 0)
|
|
|
|
apic_verbosity = APIC_VERBOSE;
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
__setup("apic=", apic_set_verbosity);
|
|
|
|
|
2008-07-01 10:43:52 -07:00
|
|
|
static int __init lapic_insert_resource(void)
|
|
|
|
{
|
|
|
|
if (!apic_phys)
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
/* Put local APIC into the resource map. */
|
|
|
|
lapic_resource.start = apic_phys;
|
|
|
|
lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
|
|
|
|
insert_resource(&iomem_resource, &lapic_resource);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* need call insert after e820_reserve_resources()
|
|
|
|
* that is using request_resource
|
|
|
|
*/
|
|
|
|
late_initcall(lapic_insert_resource);
|