2005-04-16 15:20:36 -07:00
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/*
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2005-12-13 19:10:10 -07:00
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* arch/powerpc/sysdev/dart_iommu.c
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2005-04-16 15:20:36 -07:00
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*
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2005-11-21 01:12:32 -07:00
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* Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
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2005-12-13 19:10:10 -07:00
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* Copyright (C) 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>,
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* IBM Corporation
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2005-04-16 15:20:36 -07:00
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*
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* Based on pSeries_iommu.c:
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* Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
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2005-11-21 01:12:32 -07:00
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* Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
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2005-04-16 15:20:36 -07:00
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*
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2005-12-13 19:10:10 -07:00
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* Dynamic DMA mapping support, Apple U3, U4 & IBM CPC925 "DART" iommu.
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*
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2005-04-16 15:20:36 -07:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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2005-12-13 19:10:10 -07:00
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*
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2005-04-16 15:20:36 -07:00
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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2005-12-13 19:10:10 -07:00
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*
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2005-04-16 15:20:36 -07:00
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/mm.h>
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#include <linux/spinlock.h>
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#include <linux/string.h>
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#include <linux/pci.h>
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#include <linux/dma-mapping.h>
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#include <linux/vmalloc.h>
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2007-05-03 05:28:32 -07:00
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#include <linux/suspend.h>
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2008-02-13 17:56:49 -07:00
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#include <linux/lmb.h>
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2005-04-16 15:20:36 -07:00
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/iommu.h>
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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#include <asm/abs_addr.h>
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#include <asm/cacheflush.h>
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2005-09-27 09:50:25 -07:00
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#include <asm/ppc-pci.h>
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2005-04-16 15:20:36 -07:00
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2005-11-01 21:13:20 -07:00
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#include "dart.h"
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2005-04-16 15:20:36 -07:00
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/* Physical base address and size of the DART table */
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unsigned long dart_tablebase; /* exported to htab_initialize */
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static unsigned long dart_tablesize;
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/* Virtual base address of the DART table */
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static u32 *dart_vbase;
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2007-05-03 05:28:32 -07:00
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#ifdef CONFIG_PM
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static u32 *dart_copy;
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#endif
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2005-04-16 15:20:36 -07:00
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/* Mapped base address for the dart */
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2006-02-01 05:28:02 -07:00
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static unsigned int __iomem *dart;
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2005-04-16 15:20:36 -07:00
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/* Dummy val that entries are set to when unused */
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static unsigned int dart_emptyval;
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2005-12-13 19:10:10 -07:00
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static struct iommu_table iommu_table_dart;
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static int iommu_table_dart_inited;
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2005-04-16 15:20:36 -07:00
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static int dart_dirty;
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2005-12-13 19:10:10 -07:00
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static int dart_is_u4;
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2005-04-16 15:20:36 -07:00
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#define DBG(...)
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static inline void dart_tlb_invalidate_all(void)
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{
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unsigned long l = 0;
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2005-12-13 19:10:10 -07:00
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unsigned int reg, inv_bit;
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2005-04-16 15:20:36 -07:00
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unsigned long limit;
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DBG("dart: flush\n");
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/* To invalidate the DART, set the DARTCNTL_FLUSHTLB bit in the
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* control register and wait for it to clear.
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*
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* Gotcha: Sometimes, the DART won't detect that the bit gets
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* set. If so, clear it and set it again.
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2005-12-13 19:10:10 -07:00
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*/
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2005-04-16 15:20:36 -07:00
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limit = 0;
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2005-12-13 19:10:10 -07:00
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inv_bit = dart_is_u4 ? DART_CNTL_U4_FLUSHTLB : DART_CNTL_U3_FLUSHTLB;
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2005-04-16 15:20:36 -07:00
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retry:
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l = 0;
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2005-12-13 19:10:10 -07:00
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reg = DART_IN(DART_CNTL);
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reg |= inv_bit;
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DART_OUT(DART_CNTL, reg);
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while ((DART_IN(DART_CNTL) & inv_bit) && l < (1L << limit))
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2005-04-16 15:20:36 -07:00
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l++;
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2005-12-13 19:10:10 -07:00
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if (l == (1L << limit)) {
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2005-04-16 15:20:36 -07:00
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if (limit < 4) {
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limit++;
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2006-06-28 02:50:36 -07:00
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reg = DART_IN(DART_CNTL);
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reg &= ~inv_bit;
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2005-12-13 19:10:10 -07:00
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DART_OUT(DART_CNTL, reg);
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2005-04-16 15:20:36 -07:00
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goto retry;
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} else
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2005-12-13 19:10:10 -07:00
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panic("DART: TLB did not flush after waiting a long "
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2005-04-16 15:20:36 -07:00
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"time. Buggy U3 ?");
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}
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}
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2006-06-28 02:50:36 -07:00
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static inline void dart_tlb_invalidate_one(unsigned long bus_rpn)
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{
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unsigned int reg;
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unsigned int l, limit;
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reg = DART_CNTL_U4_ENABLE | DART_CNTL_U4_IONE |
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(bus_rpn & DART_CNTL_U4_IONE_MASK);
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DART_OUT(DART_CNTL, reg);
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limit = 0;
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wait_more:
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l = 0;
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while ((DART_IN(DART_CNTL) & DART_CNTL_U4_IONE) && l < (1L << limit)) {
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rmb();
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l++;
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}
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if (l == (1L << limit)) {
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if (limit < 4) {
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limit++;
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goto wait_more;
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} else
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panic("DART: TLB did not flush after waiting a long "
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"time. Buggy U4 ?");
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}
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}
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2005-04-16 15:20:36 -07:00
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static void dart_flush(struct iommu_table *tbl)
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{
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2006-09-13 05:12:52 -07:00
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mb();
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2006-06-28 02:50:36 -07:00
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if (dart_dirty) {
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2005-04-16 15:20:36 -07:00
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dart_tlb_invalidate_all();
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2006-06-28 02:50:36 -07:00
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dart_dirty = 0;
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}
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2005-04-16 15:20:36 -07:00
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}
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2008-07-23 11:31:16 -07:00
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static int dart_build(struct iommu_table *tbl, long index,
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2005-04-16 15:20:36 -07:00
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long npages, unsigned long uaddr,
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2008-07-15 12:51:47 -07:00
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enum dma_data_direction direction,
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struct dma_attrs *attrs)
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2005-04-16 15:20:36 -07:00
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{
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unsigned int *dp;
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unsigned int rpn;
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2006-06-28 02:50:36 -07:00
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long l;
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2005-04-16 15:20:36 -07:00
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DBG("dart: build at: %lx, %lx, addr: %x\n", index, npages, uaddr);
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dp = ((unsigned int*)tbl->it_base) + index;
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2005-12-13 19:10:10 -07:00
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2005-04-16 15:20:36 -07:00
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/* On U3, all memory is contigous, so we can move this
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* out of the loop.
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*/
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2006-06-28 02:50:36 -07:00
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l = npages;
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while (l--) {
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2005-09-19 20:46:44 -07:00
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rpn = virt_to_abs(uaddr) >> DART_PAGE_SHIFT;
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2005-04-16 15:20:36 -07:00
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*(dp++) = DARTMAP_VALID | (rpn & DARTMAP_RPNMASK);
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2005-09-19 20:46:44 -07:00
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uaddr += DART_PAGE_SIZE;
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2005-04-16 15:20:36 -07:00
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}
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2006-09-13 05:12:52 -07:00
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/* make sure all updates have reached memory */
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mb();
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in_be32((unsigned __iomem *)dp);
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mb();
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2006-06-28 02:50:36 -07:00
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if (dart_is_u4) {
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rpn = index;
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while (npages--)
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dart_tlb_invalidate_one(rpn++);
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} else {
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dart_dirty = 1;
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}
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2008-07-23 11:31:16 -07:00
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return 0;
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2005-04-16 15:20:36 -07:00
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}
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static void dart_free(struct iommu_table *tbl, long index, long npages)
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{
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unsigned int *dp;
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2005-12-13 19:10:10 -07:00
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2005-04-16 15:20:36 -07:00
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/* We don't worry about flushing the TLB cache. The only drawback of
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* not doing it is that we won't catch buggy device drivers doing
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* bad DMAs, but then no 32-bit architecture ever does either.
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*/
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DBG("dart: free at: %lx, %lx\n", index, npages);
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dp = ((unsigned int *)tbl->it_base) + index;
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2005-12-13 19:10:10 -07:00
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2005-04-16 15:20:36 -07:00
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while (npages--)
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*(dp++) = dart_emptyval;
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}
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2007-08-15 03:54:32 -07:00
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static int __init dart_init(struct device_node *dart_node)
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2005-04-16 15:20:36 -07:00
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{
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unsigned int i;
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2005-12-13 19:10:10 -07:00
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unsigned long tmp, base, size;
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struct resource r;
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2005-04-16 15:20:36 -07:00
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if (dart_tablebase == 0 || dart_tablesize == 0) {
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2005-12-13 19:10:10 -07:00
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printk(KERN_INFO "DART: table not allocated, using "
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"direct DMA\n");
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2005-04-16 15:20:36 -07:00
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return -ENODEV;
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}
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2005-12-13 19:10:10 -07:00
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if (of_address_to_resource(dart_node, 0, &r))
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panic("DART: can't get register base ! ");
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2005-04-16 15:20:36 -07:00
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/* Make sure nothing from the DART range remains in the CPU cache
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* from a previous mapping that existed before the kernel took
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* over
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*/
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2005-12-13 19:10:10 -07:00
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flush_dcache_phys_range(dart_tablebase,
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dart_tablebase + dart_tablesize);
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2005-04-16 15:20:36 -07:00
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/* Allocate a spare page to map all invalid DART pages. We need to do
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* that to work around what looks like a problem with the HT bridge
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* prefetching into invalid pages and corrupting data
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*/
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2005-09-19 20:46:44 -07:00
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tmp = lmb_alloc(DART_PAGE_SIZE, DART_PAGE_SIZE);
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2005-12-13 19:10:10 -07:00
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dart_emptyval = DARTMAP_VALID | ((tmp >> DART_PAGE_SHIFT) &
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DARTMAP_RPNMASK);
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2005-04-16 15:20:36 -07:00
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2005-12-13 19:10:10 -07:00
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/* Map in DART registers */
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dart = ioremap(r.start, r.end - r.start + 1);
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2005-04-16 15:20:36 -07:00
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if (dart == NULL)
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2005-12-13 19:10:10 -07:00
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panic("DART: Cannot map registers!");
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2005-04-16 15:20:36 -07:00
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2005-12-13 19:10:10 -07:00
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/* Map in DART table */
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2005-04-16 15:20:36 -07:00
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dart_vbase = ioremap(virt_to_abs(dart_tablebase), dart_tablesize);
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/* Fill initial table */
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for (i = 0; i < dart_tablesize/4; i++)
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dart_vbase[i] = dart_emptyval;
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/* Initialize DART with table base and enable it. */
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2005-12-13 19:10:10 -07:00
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base = dart_tablebase >> DART_PAGE_SHIFT;
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size = dart_tablesize >> DART_PAGE_SHIFT;
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if (dart_is_u4) {
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2005-12-18 22:49:07 -07:00
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size &= DART_SIZE_U4_SIZE_MASK;
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2005-12-13 19:10:10 -07:00
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DART_OUT(DART_BASE_U4, base);
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DART_OUT(DART_SIZE_U4, size);
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DART_OUT(DART_CNTL, DART_CNTL_U4_ENABLE);
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} else {
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2005-12-18 22:49:07 -07:00
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size &= DART_CNTL_U3_SIZE_MASK;
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2005-12-13 19:10:10 -07:00
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DART_OUT(DART_CNTL,
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DART_CNTL_U3_ENABLE |
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(base << DART_CNTL_U3_BASE_SHIFT) |
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(size << DART_CNTL_U3_SIZE_SHIFT));
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}
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2005-04-16 15:20:36 -07:00
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/* Invalidate DART to get rid of possible stale TLBs */
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dart_tlb_invalidate_all();
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2005-12-13 19:10:10 -07:00
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printk(KERN_INFO "DART IOMMU initialized for %s type chipset\n",
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dart_is_u4 ? "U4" : "U3");
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2005-04-16 15:20:36 -07:00
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return 0;
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}
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2005-12-13 19:10:10 -07:00
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static void iommu_table_dart_setup(void)
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2005-04-16 15:20:36 -07:00
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{
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2005-12-13 19:10:10 -07:00
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iommu_table_dart.it_busno = 0;
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iommu_table_dart.it_offset = 0;
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2005-04-16 15:20:36 -07:00
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/* it_size is in number of entries */
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2006-10-29 22:15:59 -07:00
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iommu_table_dart.it_size = dart_tablesize / sizeof(u32);
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2005-04-16 15:20:36 -07:00
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/* Initialize the common IOMMU code */
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2005-12-13 19:10:10 -07:00
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iommu_table_dart.it_base = (unsigned long)dart_vbase;
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iommu_table_dart.it_index = 0;
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iommu_table_dart.it_blocksize = 1;
|
2006-06-10 03:58:08 -07:00
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iommu_init_table(&iommu_table_dart, -1);
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2005-04-16 15:20:36 -07:00
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/* Reserve the last page of the DART to avoid possible prefetch
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* past the DART mapped area
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*/
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2005-12-13 19:10:10 -07:00
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set_bit(iommu_table_dart.it_size - 1, iommu_table_dart.it_map);
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2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
2006-11-10 23:25:02 -07:00
|
|
|
static void pci_dma_dev_setup_dart(struct pci_dev *dev)
|
2005-04-16 15:20:36 -07:00
|
|
|
{
|
|
|
|
/* We only have one iommu table on the mac for now, which makes
|
|
|
|
* things simple. Setup all PCI devices to point to this table
|
|
|
|
*/
|
2006-11-10 23:25:02 -07:00
|
|
|
dev->dev.archdata.dma_data = &iommu_table_dart;
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
2006-11-10 23:25:02 -07:00
|
|
|
static void pci_dma_bus_setup_dart(struct pci_bus *bus)
|
2005-04-16 15:20:36 -07:00
|
|
|
{
|
|
|
|
struct device_node *dn;
|
|
|
|
|
2005-12-13 19:10:10 -07:00
|
|
|
if (!iommu_table_dart_inited) {
|
|
|
|
iommu_table_dart_inited = 1;
|
|
|
|
iommu_table_dart_setup();
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
dn = pci_bus_to_OF_node(bus);
|
|
|
|
|
|
|
|
if (dn)
|
2005-12-13 19:10:10 -07:00
|
|
|
PCI_DN(dn)->iommu_table = &iommu_table_dart;
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
2007-08-15 03:54:32 -07:00
|
|
|
void __init iommu_init_early_dart(void)
|
2005-04-16 15:20:36 -07:00
|
|
|
{
|
|
|
|
struct device_node *dn;
|
|
|
|
|
|
|
|
/* Find the DART in the device-tree */
|
|
|
|
dn = of_find_compatible_node(NULL, "dart", "u3-dart");
|
2005-12-13 19:10:10 -07:00
|
|
|
if (dn == NULL) {
|
|
|
|
dn = of_find_compatible_node(NULL, "dart", "u4-dart");
|
|
|
|
if (dn == NULL)
|
|
|
|
goto bail;
|
|
|
|
dart_is_u4 = 1;
|
|
|
|
}
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
/* Setup low level TCE operations for the core IOMMU code */
|
|
|
|
ppc_md.tce_build = dart_build;
|
|
|
|
ppc_md.tce_free = dart_free;
|
|
|
|
ppc_md.tce_flush = dart_flush;
|
|
|
|
|
|
|
|
/* Initialize the DART HW */
|
2005-12-13 19:10:10 -07:00
|
|
|
if (dart_init(dn) == 0) {
|
2006-11-10 23:25:02 -07:00
|
|
|
ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_dart;
|
|
|
|
ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_dart;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
/* Setup pci_dma ops */
|
2007-03-03 22:58:39 -07:00
|
|
|
set_pci_dma_ops(&dma_iommu_ops);
|
2005-12-13 19:10:10 -07:00
|
|
|
return;
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
2005-12-13 19:10:10 -07:00
|
|
|
|
|
|
|
bail:
|
|
|
|
/* If init failed, use direct iommu and null setup functions */
|
2006-11-10 23:25:02 -07:00
|
|
|
ppc_md.pci_dma_dev_setup = NULL;
|
|
|
|
ppc_md.pci_dma_bus_setup = NULL;
|
2005-12-13 19:10:10 -07:00
|
|
|
|
|
|
|
/* Setup pci_dma ops */
|
2007-03-03 22:58:39 -07:00
|
|
|
set_pci_dma_ops(&dma_direct_ops);
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
2007-05-03 05:28:32 -07:00
|
|
|
#ifdef CONFIG_PM
|
|
|
|
static void iommu_dart_save(void)
|
|
|
|
{
|
|
|
|
memcpy(dart_copy, dart_vbase, 2*1024*1024);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void iommu_dart_restore(void)
|
|
|
|
{
|
|
|
|
memcpy(dart_vbase, dart_copy, 2*1024*1024);
|
|
|
|
dart_tlb_invalidate_all();
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __init iommu_init_late_dart(void)
|
|
|
|
{
|
|
|
|
unsigned long tbasepfn;
|
|
|
|
struct page *p;
|
|
|
|
|
|
|
|
/* if no dart table exists then we won't need to save it
|
|
|
|
* and the area has also not been reserved */
|
|
|
|
if (!dart_tablebase)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
tbasepfn = __pa(dart_tablebase) >> PAGE_SHIFT;
|
|
|
|
register_nosave_region_late(tbasepfn,
|
|
|
|
tbasepfn + ((1<<24) >> PAGE_SHIFT));
|
|
|
|
|
|
|
|
/* For suspend we need to copy the dart contents because
|
|
|
|
* it is not part of the regular mapping (see above) and
|
|
|
|
* thus not saved automatically. The memory for this copy
|
|
|
|
* must be allocated early because we need 2 MB. */
|
|
|
|
p = alloc_pages(GFP_KERNEL, 21 - PAGE_SHIFT);
|
|
|
|
BUG_ON(!p);
|
|
|
|
dart_copy = page_address(p);
|
|
|
|
|
|
|
|
ppc_md.iommu_save = iommu_dart_save;
|
|
|
|
ppc_md.iommu_restore = iommu_dart_restore;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
late_initcall(iommu_init_late_dart);
|
|
|
|
#endif
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2005-12-13 19:10:10 -07:00
|
|
|
void __init alloc_dart_table(void)
|
2005-04-16 15:20:36 -07:00
|
|
|
{
|
2006-04-12 19:52:33 -07:00
|
|
|
/* Only reserve DART space if machine has more than 1GB of RAM
|
2005-04-16 15:20:36 -07:00
|
|
|
* or if requested with iommu=on on cmdline.
|
2006-04-12 19:52:33 -07:00
|
|
|
*
|
|
|
|
* 1GB of RAM is picked as limit because some default devices
|
|
|
|
* (i.e. Airport Extreme) have 30 bit address range limits.
|
2005-04-16 15:20:36 -07:00
|
|
|
*/
|
2006-04-12 19:52:33 -07:00
|
|
|
|
|
|
|
if (iommu_is_off)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (!iommu_force_on && lmb_end_of_DRAM() <= 0x40000000ull)
|
2005-04-16 15:20:36 -07:00
|
|
|
return;
|
|
|
|
|
|
|
|
/* 512 pages (2MB) is max DART tablesize. */
|
|
|
|
dart_tablesize = 1UL << 21;
|
|
|
|
/* 16MB (1 << 24) alignment. We allocate a full 16Mb chuck since we
|
|
|
|
* will blow up an entire large page anyway in the kernel mapping
|
|
|
|
*/
|
|
|
|
dart_tablebase = (unsigned long)
|
|
|
|
abs_to_virt(lmb_alloc_base(1UL<<24, 1UL<<24, 0x80000000L));
|
|
|
|
|
2005-12-13 19:10:10 -07:00
|
|
|
printk(KERN_INFO "DART table allocated at: %lx\n", dart_tablebase);
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|