709 lines
20 KiB
C
709 lines
20 KiB
C
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#ifndef XTENSA_CACHEASM_H
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#define XTENSA_CACHEASM_H
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/*
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* THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
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*
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* include/asm-xtensa/xtensa/cacheasm.h -- assembler-specific cache
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* related definitions that depend on CORE configuration.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2002 Tensilica Inc.
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*/
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#include <xtensa/coreasm.h>
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/*
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* This header file defines assembler macros of the form:
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* <x>cache_<func>
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* where <x> is 'i' or 'd' for instruction and data caches,
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* and <func> indicates the function of the macro.
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*
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* The following functions <func> are defined,
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* and apply only to the specified cache (I or D):
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*
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* reset
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* Resets the cache.
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*
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* sync
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* Makes sure any previous cache instructions have been completed;
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* ie. makes sure any previous cache control operations
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* have had full effect and been synchronized to memory.
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* Eg. any invalidate completed [so as not to generate a hit],
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* any writebacks or other pipelined writes written to memory, etc.
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*
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* invalidate_line (single cache line)
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* invalidate_region (specified memory range)
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* invalidate_all (entire cache)
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* Invalidates all cache entries that cache
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* data from the specified memory range.
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* NOTE: locked entries are not invalidated.
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*
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* writeback_line (single cache line)
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* writeback_region (specified memory range)
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* writeback_all (entire cache)
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* Writes back to memory all dirty cache entries
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* that cache data from the specified memory range,
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* and marks these entries as clean.
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* NOTE: on some future implementations, this might
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* also invalidate.
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* NOTE: locked entries are written back, but never invalidated.
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* NOTE: instruction caches never implement writeback.
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*
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* writeback_inv_line (single cache line)
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* writeback_inv_region (specified memory range)
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* writeback_inv_all (entire cache)
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* Writes back to memory all dirty cache entries
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* that cache data from the specified memory range,
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* and invalidates these entries (including all clean
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* cache entries that cache data from that range).
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* NOTE: locked entries are written back but not invalidated.
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* NOTE: instruction caches never implement writeback.
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*
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* lock_line (single cache line)
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* lock_region (specified memory range)
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* Prefetch and lock the specified memory range into cache.
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* NOTE: if any part of the specified memory range cannot
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* be locked, a ??? exception occurs. These macros don't
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* do anything special (yet anyway) to handle this situation.
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*
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* unlock_line (single cache line)
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* unlock_region (specified memory range)
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* unlock_all (entire cache)
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* Unlock cache entries that cache the specified memory range.
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* Entries not already locked are unaffected.
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*/
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/*************************** GENERIC -- ALL CACHES ***************************/
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/*
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* The following macros assume the following cache size/parameter limits
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* in the current Xtensa core implementation:
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* cache size: 1024 bytes minimum
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* line size: 16 - 64 bytes
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* way count: 1 - 4
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*
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* Minimum entries per way (ie. per associativity) = 1024 / 64 / 4 = 4
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* Hence the assumption that each loop can execute four cache instructions.
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*
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* Correspondingly, the offset range of instructions is assumed able to cover
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* four lines, ie. offsets {0,1,2,3} * line_size are assumed valid for
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* both hit and indexed cache instructions. Ie. these offsets are all
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* valid: 0, 16, 32, 48, 64, 96, 128, 192 (for line sizes 16, 32, 64).
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* This is true of all original cache instructions
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* (dhi, ihi, dhwb, dhwbi, dii, iii) which have offsets
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* of 0 to 1020 in multiples of 4 (ie. 8 bits shifted by 2).
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* This is also true of subsequent cache instructions
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* (dhu, ihu, diu, iiu, diwb, diwbi, dpfl, ipfl) which have offsets
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* of 0 to 240 in multiples of 16 (ie. 4 bits shifted by 4).
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*
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* (Maximum cache size, currently 32k, doesn't affect the following macros.
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* Cache ways > MMU min page size cause aliasing but that's another matter.)
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*/
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/*
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* Macro to apply an 'indexed' cache instruction to the entire cache.
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*
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* Parameters:
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* cainst instruction/ that takes an address register parameter
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* and an offset parameter (in range 0 .. 3*linesize).
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* size size of cache in bytes
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* linesize size of cache line in bytes
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* assoc_or1 number of associativities (ways/sets) in cache
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* if all sets affected by cainst,
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* or 1 if only one set (or not all sets) of the cache
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* is affected by cainst (eg. DIWB or DIWBI [not yet ISA defined]).
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* aa, ab unique address registers (temporaries)
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*/
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.macro cache_index_all cainst, size, linesize, assoc_or1, aa, ab
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// Sanity-check on cache parameters:
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.ifne (\size % (\linesize * \assoc_or1 * 4))
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.err // cache configuration outside expected/supported range!
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.endif
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// \size byte cache, \linesize byte lines, \assoc_or1 way(s) affected by each \cainst.
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movi \aa, (\size / (\linesize * \assoc_or1 * 4))
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// Possible improvement: need only loop if \aa > 1 ;
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// however that particular condition is highly unlikely.
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movi \ab, 0 // to iterate over cache
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floop \aa, cachex\@
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\cainst \ab, 0*\linesize
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\cainst \ab, 1*\linesize
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\cainst \ab, 2*\linesize
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\cainst \ab, 3*\linesize
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addi \ab, \ab, 4*\linesize // move to next line
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floopend \aa, cachex\@
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.endm
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/*
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* Macro to apply a 'hit' cache instruction to a memory region,
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* ie. to any cache entries that cache a specified portion (region) of memory.
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* Takes care of the unaligned cases, ie. may apply to one
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* more cache line than $asize / lineSize if $aaddr is not aligned.
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*
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*
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* Parameters are:
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* cainst instruction/macro that takes an address register parameter
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* and an offset parameter (currently always zero)
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* and generates a cache instruction (eg. "dhi", "dhwb", "ihi", etc.)
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* linesize_log2 log2(size of cache line in bytes)
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* addr register containing start address of region (clobbered)
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* asize register containing size of the region in bytes (clobbered)
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* askew unique register used as temporary
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*
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* !?!?! 2DO: optimization: iterate max(cache_size and \asize) / linesize
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*/
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.macro cache_hit_region cainst, linesize_log2, addr, asize, askew
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// Make \asize the number of iterations:
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extui \askew, \addr, 0, \linesize_log2 // get unalignment amount of \addr
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add \asize, \asize, \askew // ... and add it to \asize
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addi \asize, \asize, (1 << \linesize_log2) - 1 // round up!
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srli \asize, \asize, \linesize_log2
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// Iterate over region:
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floopnez \asize, cacheh\@
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\cainst \addr, 0
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addi \addr, \addr, (1 << \linesize_log2) // move to next line
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floopend \asize, cacheh\@
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.endm
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/*************************** INSTRUCTION CACHE ***************************/
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/*
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* Reset/initialize the instruction cache by simply invalidating it:
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* (need to unlock first also, if cache locking implemented):
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*
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* Parameters:
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* aa, ab unique address registers (temporaries)
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*/
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.macro icache_reset aa, ab
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icache_unlock_all \aa, \ab
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icache_invalidate_all \aa, \ab
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.endm
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/*
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* Synchronize after an instruction cache operation,
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* to be sure everything is in sync with memory as to be
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* expected following any previous instruction cache control operations.
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*
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* Parameters are:
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* ar an address register (temporary) (currently unused, but may be used in future)
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*/
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.macro icache_sync ar
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#if XCHAL_ICACHE_SIZE > 0
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isync
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#endif
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.endm
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/*
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* Invalidate a single line of the instruction cache.
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* Parameters are:
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* ar address register that contains (virtual) address to invalidate
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* (may get clobbered in a future implementation, but not currently)
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* offset (optional) offset to add to \ar to compute effective address to invalidate
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* (note: some number of lsbits are ignored)
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*/
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.macro icache_invalidate_line ar, offset
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#if XCHAL_ICACHE_SIZE > 0
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ihi \ar, \offset // invalidate icache line
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/*
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* NOTE: in some version of the silicon [!!!SHOULD HAVE BEEN DOCUMENTED!!!]
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* 'ihi' doesn't work, so it had been replaced with 'iii'
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* (which would just invalidate more than it should,
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* which should be okay other than the performance hit
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* because cache locking did not exist in that version,
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* unless user somehow relies on something being cached).
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* [WHAT VERSION IS IT!!?!?
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* IS THERE ANY WAY TO TEST FOR THAT HERE, TO OUTPUT 'III' ONLY IF NEEDED!?!?].
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*
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* iii \ar, \offset
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*/
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icache_sync \ar
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#endif
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.endm
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/*
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* Invalidate instruction cache entries that cache a specified portion of memory.
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* Parameters are:
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* astart start address (register gets clobbered)
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* asize size of the region in bytes (register gets clobbered)
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* ac unique register used as temporary
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*/
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.macro icache_invalidate_region astart, asize, ac
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#if XCHAL_ICACHE_SIZE > 0
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// Instruction cache region invalidation:
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cache_hit_region ihi, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
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icache_sync \ac
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// End of instruction cache region invalidation
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#endif
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.endm
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/*
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* Invalidate entire instruction cache.
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*
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* Parameters:
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* aa, ab unique address registers (temporaries)
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*/
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.macro icache_invalidate_all aa, ab
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#if XCHAL_ICACHE_SIZE > 0
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// Instruction cache invalidation:
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cache_index_all iii, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE, XCHAL_ICACHE_WAYS, \aa, \ab
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icache_sync \aa
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// End of instruction cache invalidation
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#endif
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.endm
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/*
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* Lock (prefetch & lock) a single line of the instruction cache.
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*
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* Parameters are:
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* ar address register that contains (virtual) address to lock
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* (may get clobbered in a future implementation, but not currently)
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* offset offset to add to \ar to compute effective address to lock
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* (note: some number of lsbits are ignored)
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*/
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.macro icache_lock_line ar, offset
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#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
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ipfl \ar, \offset /* prefetch and lock icache line */
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icache_sync \ar
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#endif
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.endm
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/*
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* Lock (prefetch & lock) a specified portion of memory into the instruction cache.
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* Parameters are:
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* astart start address (register gets clobbered)
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* asize size of the region in bytes (register gets clobbered)
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* ac unique register used as temporary
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*/
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.macro icache_lock_region astart, asize, ac
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#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
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// Instruction cache region lock:
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cache_hit_region ipfl, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
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icache_sync \ac
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// End of instruction cache region lock
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#endif
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.endm
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/*
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* Unlock a single line of the instruction cache.
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*
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* Parameters are:
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* ar address register that contains (virtual) address to unlock
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* (may get clobbered in a future implementation, but not currently)
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* offset offset to add to \ar to compute effective address to unlock
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* (note: some number of lsbits are ignored)
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*/
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.macro icache_unlock_line ar, offset
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#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
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ihu \ar, \offset /* unlock icache line */
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icache_sync \ar
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#endif
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.endm
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/*
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* Unlock a specified portion of memory from the instruction cache.
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* Parameters are:
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* astart start address (register gets clobbered)
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* asize size of the region in bytes (register gets clobbered)
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* ac unique register used as temporary
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*/
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.macro icache_unlock_region astart, asize, ac
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#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
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// Instruction cache region unlock:
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cache_hit_region ihu, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
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icache_sync \ac
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// End of instruction cache region unlock
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#endif
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.endm
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/*
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* Unlock entire instruction cache.
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*
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* Parameters:
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* aa, ab unique address registers (temporaries)
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*/
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.macro icache_unlock_all aa, ab
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#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
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// Instruction cache unlock:
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cache_index_all iiu, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE, 1, \aa, \ab
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|
icache_sync \aa
|
||
|
|
// End of instruction cache unlock
|
||
|
|
#endif
|
||
|
|
.endm
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
/*************************** DATA CACHE ***************************/
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Reset/initialize the data cache by simply invalidating it
|
||
|
|
* (need to unlock first also, if cache locking implemented):
|
||
|
|
*
|
||
|
|
* Parameters:
|
||
|
|
* aa, ab unique address registers (temporaries)
|
||
|
|
*/
|
||
|
|
.macro dcache_reset aa, ab
|
||
|
|
dcache_unlock_all \aa, \ab
|
||
|
|
dcache_invalidate_all \aa, \ab
|
||
|
|
.endm
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Synchronize after a data cache operation,
|
||
|
|
* to be sure everything is in sync with memory as to be
|
||
|
|
* expected following any previous data cache control operations.
|
||
|
|
*
|
||
|
|
* Parameters are:
|
||
|
|
* ar an address register (temporary) (currently unused, but may be used in future)
|
||
|
|
*/
|
||
|
|
.macro dcache_sync ar
|
||
|
|
#if XCHAL_DCACHE_SIZE > 0
|
||
|
|
// This previous sequence errs on the conservative side (too much so); a DSYNC should be sufficient:
|
||
|
|
//memw // synchronize data cache changes relative to subsequent memory accesses
|
||
|
|
//isync // be conservative and ISYNC as well (just to be sure)
|
||
|
|
|
||
|
|
dsync
|
||
|
|
#endif
|
||
|
|
.endm
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Synchronize after a data store operation,
|
||
|
|
* to be sure the stored data is completely off the processor
|
||
|
|
* (and assuming there is no buffering outside the processor,
|
||
|
|
* that the data is in memory). This may be required to
|
||
|
|
* ensure that the processor's write buffers are emptied.
|
||
|
|
* A MEMW followed by a read guarantees this, by definition.
|
||
|
|
* We also try to make sure the read itself completes.
|
||
|
|
*
|
||
|
|
* Parameters are:
|
||
|
|
* ar an address register (temporary)
|
||
|
|
*/
|
||
|
|
.macro write_sync ar
|
||
|
|
memw // ensure previous memory accesses are complete prior to subsequent memory accesses
|
||
|
|
l32i \ar, sp, 0 // completing this read ensures any previous write has completed, because of MEMW
|
||
|
|
//slot
|
||
|
|
add \ar, \ar, \ar // use the result of the read to help ensure the read completes (in future architectures)
|
||
|
|
.endm
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Invalidate a single line of the data cache.
|
||
|
|
* Parameters are:
|
||
|
|
* ar address register that contains (virtual) address to invalidate
|
||
|
|
* (may get clobbered in a future implementation, but not currently)
|
||
|
|
* offset (optional) offset to add to \ar to compute effective address to invalidate
|
||
|
|
* (note: some number of lsbits are ignored)
|
||
|
|
*/
|
||
|
|
.macro dcache_invalidate_line ar, offset
|
||
|
|
#if XCHAL_DCACHE_SIZE > 0
|
||
|
|
dhi \ar, \offset
|
||
|
|
dcache_sync \ar
|
||
|
|
#endif
|
||
|
|
.endm
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Invalidate data cache entries that cache a specified portion of memory.
|
||
|
|
* Parameters are:
|
||
|
|
* astart start address (register gets clobbered)
|
||
|
|
* asize size of the region in bytes (register gets clobbered)
|
||
|
|
* ac unique register used as temporary
|
||
|
|
*/
|
||
|
|
.macro dcache_invalidate_region astart, asize, ac
|
||
|
|
#if XCHAL_DCACHE_SIZE > 0
|
||
|
|
// Data cache region invalidation:
|
||
|
|
cache_hit_region dhi, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
|
||
|
|
dcache_sync \ac
|
||
|
|
// End of data cache region invalidation
|
||
|
|
#endif
|
||
|
|
.endm
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
#if 0
|
||
|
|
/*
|
||
|
|
* This is a work-around for a bug in SiChip1 (???).
|
||
|
|
* There should be a proper mechanism for not outputting
|
||
|
|
* these instructions when not needed.
|
||
|
|
* To enable work-around, uncomment this and replace 'dii'
|
||
|
|
* with 'dii_s1' everywhere, eg. in dcache_invalidate_all
|
||
|
|
* macro below.
|
||
|
|
*/
|
||
|
|
.macro dii_s1 ar, offset
|
||
|
|
dii \ar, \offset
|
||
|
|
or \ar, \ar, \ar
|
||
|
|
or \ar, \ar, \ar
|
||
|
|
or \ar, \ar, \ar
|
||
|
|
or \ar, \ar, \ar
|
||
|
|
.endm
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Invalidate entire data cache.
|
||
|
|
*
|
||
|
|
* Parameters:
|
||
|
|
* aa, ab unique address registers (temporaries)
|
||
|
|
*/
|
||
|
|
.macro dcache_invalidate_all aa, ab
|
||
|
|
#if XCHAL_DCACHE_SIZE > 0
|
||
|
|
// Data cache invalidation:
|
||
|
|
cache_index_all dii, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, XCHAL_DCACHE_WAYS, \aa, \ab
|
||
|
|
dcache_sync \aa
|
||
|
|
// End of data cache invalidation
|
||
|
|
#endif
|
||
|
|
.endm
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Writeback a single line of the data cache.
|
||
|
|
* Parameters are:
|
||
|
|
* ar address register that contains (virtual) address to writeback
|
||
|
|
* (may get clobbered in a future implementation, but not currently)
|
||
|
|
* offset offset to add to \ar to compute effective address to writeback
|
||
|
|
* (note: some number of lsbits are ignored)
|
||
|
|
*/
|
||
|
|
.macro dcache_writeback_line ar, offset
|
||
|
|
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
|
||
|
|
dhwb \ar, \offset
|
||
|
|
dcache_sync \ar
|
||
|
|
#endif
|
||
|
|
.endm
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Writeback dirty data cache entries that cache a specified portion of memory.
|
||
|
|
* Parameters are:
|
||
|
|
* astart start address (register gets clobbered)
|
||
|
|
* asize size of the region in bytes (register gets clobbered)
|
||
|
|
* ac unique register used as temporary
|
||
|
|
*/
|
||
|
|
.macro dcache_writeback_region astart, asize, ac
|
||
|
|
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
|
||
|
|
// Data cache region writeback:
|
||
|
|
cache_hit_region dhwb, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
|
||
|
|
dcache_sync \ac
|
||
|
|
// End of data cache region writeback
|
||
|
|
#endif
|
||
|
|
.endm
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Writeback entire data cache.
|
||
|
|
* Parameters:
|
||
|
|
* aa, ab unique address registers (temporaries)
|
||
|
|
*/
|
||
|
|
.macro dcache_writeback_all aa, ab
|
||
|
|
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
|
||
|
|
// Data cache writeback:
|
||
|
|
cache_index_all diwb, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab
|
||
|
|
dcache_sync \aa
|
||
|
|
// End of data cache writeback
|
||
|
|
#endif
|
||
|
|
.endm
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Writeback and invalidate a single line of the data cache.
|
||
|
|
* Parameters are:
|
||
|
|
* ar address register that contains (virtual) address to writeback and invalidate
|
||
|
|
* (may get clobbered in a future implementation, but not currently)
|
||
|
|
* offset offset to add to \ar to compute effective address to writeback and invalidate
|
||
|
|
* (note: some number of lsbits are ignored)
|
||
|
|
*/
|
||
|
|
.macro dcache_writeback_inv_line ar, offset
|
||
|
|
#if XCHAL_DCACHE_SIZE > 0
|
||
|
|
dhwbi \ar, \offset /* writeback and invalidate dcache line */
|
||
|
|
dcache_sync \ar
|
||
|
|
#endif
|
||
|
|
.endm
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Writeback and invalidate data cache entries that cache a specified portion of memory.
|
||
|
|
* Parameters are:
|
||
|
|
* astart start address (register gets clobbered)
|
||
|
|
* asize size of the region in bytes (register gets clobbered)
|
||
|
|
* ac unique register used as temporary
|
||
|
|
*/
|
||
|
|
.macro dcache_writeback_inv_region astart, asize, ac
|
||
|
|
#if XCHAL_DCACHE_SIZE > 0
|
||
|
|
// Data cache region writeback and invalidate:
|
||
|
|
cache_hit_region dhwbi, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
|
||
|
|
dcache_sync \ac
|
||
|
|
// End of data cache region writeback and invalidate
|
||
|
|
#endif
|
||
|
|
.endm
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Writeback and invalidate entire data cache.
|
||
|
|
* Parameters:
|
||
|
|
* aa, ab unique address registers (temporaries)
|
||
|
|
*/
|
||
|
|
.macro dcache_writeback_inv_all aa, ab
|
||
|
|
#if XCHAL_DCACHE_SIZE > 0
|
||
|
|
// Data cache writeback and invalidate:
|
||
|
|
#if XCHAL_DCACHE_IS_WRITEBACK
|
||
|
|
cache_index_all diwbi, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab
|
||
|
|
dcache_sync \aa
|
||
|
|
#else /*writeback*/
|
||
|
|
// Data cache does not support writeback, so just invalidate: */
|
||
|
|
dcache_invalidate_all \aa, \ab
|
||
|
|
#endif /*writeback*/
|
||
|
|
// End of data cache writeback and invalidate
|
||
|
|
#endif
|
||
|
|
.endm
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Lock (prefetch & lock) a single line of the data cache.
|
||
|
|
*
|
||
|
|
* Parameters are:
|
||
|
|
* ar address register that contains (virtual) address to lock
|
||
|
|
* (may get clobbered in a future implementation, but not currently)
|
||
|
|
* offset offset to add to \ar to compute effective address to lock
|
||
|
|
* (note: some number of lsbits are ignored)
|
||
|
|
*/
|
||
|
|
.macro dcache_lock_line ar, offset
|
||
|
|
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
|
||
|
|
dpfl \ar, \offset /* prefetch and lock dcache line */
|
||
|
|
dcache_sync \ar
|
||
|
|
#endif
|
||
|
|
.endm
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Lock (prefetch & lock) a specified portion of memory into the data cache.
|
||
|
|
* Parameters are:
|
||
|
|
* astart start address (register gets clobbered)
|
||
|
|
* asize size of the region in bytes (register gets clobbered)
|
||
|
|
* ac unique register used as temporary
|
||
|
|
*/
|
||
|
|
.macro dcache_lock_region astart, asize, ac
|
||
|
|
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
|
||
|
|
// Data cache region lock:
|
||
|
|
cache_hit_region dpfl, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
|
||
|
|
dcache_sync \ac
|
||
|
|
// End of data cache region lock
|
||
|
|
#endif
|
||
|
|
.endm
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Unlock a single line of the data cache.
|
||
|
|
*
|
||
|
|
* Parameters are:
|
||
|
|
* ar address register that contains (virtual) address to unlock
|
||
|
|
* (may get clobbered in a future implementation, but not currently)
|
||
|
|
* offset offset to add to \ar to compute effective address to unlock
|
||
|
|
* (note: some number of lsbits are ignored)
|
||
|
|
*/
|
||
|
|
.macro dcache_unlock_line ar, offset
|
||
|
|
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
|
||
|
|
dhu \ar, \offset /* unlock dcache line */
|
||
|
|
dcache_sync \ar
|
||
|
|
#endif
|
||
|
|
.endm
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Unlock a specified portion of memory from the data cache.
|
||
|
|
* Parameters are:
|
||
|
|
* astart start address (register gets clobbered)
|
||
|
|
* asize size of the region in bytes (register gets clobbered)
|
||
|
|
* ac unique register used as temporary
|
||
|
|
*/
|
||
|
|
.macro dcache_unlock_region astart, asize, ac
|
||
|
|
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
|
||
|
|
// Data cache region unlock:
|
||
|
|
cache_hit_region dhu, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
|
||
|
|
dcache_sync \ac
|
||
|
|
// End of data cache region unlock
|
||
|
|
#endif
|
||
|
|
.endm
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Unlock entire data cache.
|
||
|
|
*
|
||
|
|
* Parameters:
|
||
|
|
* aa, ab unique address registers (temporaries)
|
||
|
|
*/
|
||
|
|
.macro dcache_unlock_all aa, ab
|
||
|
|
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
|
||
|
|
// Data cache unlock:
|
||
|
|
cache_index_all diu, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab
|
||
|
|
dcache_sync \aa
|
||
|
|
// End of data cache unlock
|
||
|
|
#endif
|
||
|
|
.endm
|
||
|
|
|
||
|
|
|
||
|
|
#endif /*XTENSA_CACHEASM_H*/
|
||
|
|
|