2023-08-04 03:46:01 -07:00
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// SPDX-License-Identifier: GPL-2.0
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//
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// CS42L43 SPI Controller Driver
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//
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// Copyright (C) 2022-2023 Cirrus Logic, Inc. and
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// Cirrus Logic International Semiconductor Ltd.
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2024-04-16 03:09:04 -07:00
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#include <linux/acpi.h>
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#include <linux/array_size.h>
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2023-08-04 03:46:01 -07:00
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#include <linux/bits.h>
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#include <linux/bitfield.h>
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2024-06-19 05:17:02 -07:00
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#include <linux/cleanup.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/gpio/machine.h>
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#include <linux/gpio/property.h>
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2023-08-04 03:46:01 -07:00
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#include <linux/mfd/cs42l43.h>
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#include <linux/mfd/cs42l43-regs.h>
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2024-01-29 08:25:52 -07:00
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/property.h>
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2023-08-04 03:46:01 -07:00
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#include <linux/regmap.h>
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#include <linux/spi/spi.h>
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#include <linux/units.h>
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#define CS42L43_FIFO_SIZE 16
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#define CS42L43_SPI_ROOT_HZ 49152000
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#define CS42L43_SPI_MAX_LENGTH 65532
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enum cs42l43_spi_cmd {
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CS42L43_WRITE,
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CS42L43_READ
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};
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struct cs42l43_spi {
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struct device *dev;
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struct regmap *regmap;
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struct spi_controller *ctlr;
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};
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static const unsigned int cs42l43_clock_divs[] = {
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2, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
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};
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2024-06-19 05:17:03 -07:00
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static struct spi_board_info amp_info_template = {
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.modalias = "cs35l56",
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.max_speed_hz = 11 * HZ_PER_MHZ,
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.mode = SPI_MODE_0,
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};
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static const struct software_node cs42l43_gpiochip_swnode = {
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.name = "cs42l43-pinctrl",
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};
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static const struct software_node_ref_args cs42l43_cs_refs[] = {
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SOFTWARE_NODE_REFERENCE(&cs42l43_gpiochip_swnode, 0, GPIO_ACTIVE_LOW),
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SOFTWARE_NODE_REFERENCE(&swnode_gpio_undefined),
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};
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static const struct property_entry cs42l43_cs_props[] = {
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PROPERTY_ENTRY_REF_ARRAY("cs-gpios", cs42l43_cs_refs),
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{}
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};
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2023-08-04 03:46:01 -07:00
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static int cs42l43_spi_tx(struct regmap *regmap, const u8 *buf, unsigned int len)
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{
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const u8 *end = buf + len;
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u32 val = 0;
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int ret;
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while (buf < end) {
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const u8 *block = min(buf + CS42L43_FIFO_SIZE, end);
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while (buf < block) {
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const u8 *word = min(buf + sizeof(u32), block);
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int pad = (buf + sizeof(u32)) - word;
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while (buf < word) {
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val >>= BITS_PER_BYTE;
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val |= FIELD_PREP(GENMASK(31, 24), *buf);
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buf++;
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}
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val >>= pad * BITS_PER_BYTE;
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regmap_write(regmap, CS42L43_TX_DATA, val);
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}
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regmap_write(regmap, CS42L43_TRAN_CONFIG8, CS42L43_SPI_TX_DONE_MASK);
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ret = regmap_read_poll_timeout(regmap, CS42L43_TRAN_STATUS1,
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val, (val & CS42L43_SPI_TX_REQUEST_MASK),
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1000, 5000);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int cs42l43_spi_rx(struct regmap *regmap, u8 *buf, unsigned int len)
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{
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u8 *end = buf + len;
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u32 val;
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int ret;
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while (buf < end) {
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u8 *block = min(buf + CS42L43_FIFO_SIZE, end);
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ret = regmap_read_poll_timeout(regmap, CS42L43_TRAN_STATUS1,
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val, (val & CS42L43_SPI_RX_REQUEST_MASK),
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1000, 5000);
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if (ret)
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return ret;
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while (buf < block) {
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u8 *word = min(buf + sizeof(u32), block);
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ret = regmap_read(regmap, CS42L43_RX_DATA, &val);
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if (ret)
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return ret;
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while (buf < word) {
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*buf = FIELD_GET(GENMASK(7, 0), val);
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val >>= BITS_PER_BYTE;
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buf++;
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}
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}
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regmap_write(regmap, CS42L43_TRAN_CONFIG8, CS42L43_SPI_RX_DONE_MASK);
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}
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return 0;
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}
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static int cs42l43_transfer_one(struct spi_controller *ctlr, struct spi_device *spi,
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struct spi_transfer *tfr)
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{
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struct cs42l43_spi *priv = spi_controller_get_devdata(spi->controller);
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int i, ret = -EINVAL;
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for (i = 0; i < ARRAY_SIZE(cs42l43_clock_divs); i++) {
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if (CS42L43_SPI_ROOT_HZ / cs42l43_clock_divs[i] <= tfr->speed_hz)
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break;
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}
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if (i == ARRAY_SIZE(cs42l43_clock_divs))
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return -EINVAL;
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regmap_write(priv->regmap, CS42L43_SPI_CLK_CONFIG1, i);
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if (tfr->tx_buf) {
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regmap_write(priv->regmap, CS42L43_TRAN_CONFIG3, CS42L43_WRITE);
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regmap_write(priv->regmap, CS42L43_TRAN_CONFIG4, tfr->len - 1);
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} else if (tfr->rx_buf) {
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regmap_write(priv->regmap, CS42L43_TRAN_CONFIG3, CS42L43_READ);
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regmap_write(priv->regmap, CS42L43_TRAN_CONFIG5, tfr->len - 1);
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}
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regmap_write(priv->regmap, CS42L43_TRAN_CONFIG1, CS42L43_SPI_START_MASK);
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if (tfr->tx_buf)
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ret = cs42l43_spi_tx(priv->regmap, (const u8 *)tfr->tx_buf, tfr->len);
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else if (tfr->rx_buf)
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ret = cs42l43_spi_rx(priv->regmap, (u8 *)tfr->rx_buf, tfr->len);
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return ret;
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}
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static void cs42l43_set_cs(struct spi_device *spi, bool is_high)
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{
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struct cs42l43_spi *priv = spi_controller_get_devdata(spi->controller);
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2024-03-06 09:10:04 -07:00
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regmap_write(priv->regmap, CS42L43_SPI_CONFIG2, !is_high);
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}
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static int cs42l43_prepare_message(struct spi_controller *ctlr, struct spi_message *msg)
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{
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struct cs42l43_spi *priv = spi_controller_get_devdata(ctlr);
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struct spi_device *spi = msg->spi;
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unsigned int spi_config1 = 0;
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/* select another internal CS, which doesn't exist, so CS 0 is not used */
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if (spi_get_csgpiod(spi, 0))
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spi_config1 |= 1 << CS42L43_SPI_SS_SEL_SHIFT;
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if (spi->mode & SPI_CPOL)
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spi_config1 |= CS42L43_SPI_CPOL_MASK;
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if (spi->mode & SPI_CPHA)
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spi_config1 |= CS42L43_SPI_CPHA_MASK;
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if (spi->mode & SPI_3WIRE)
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spi_config1 |= CS42L43_SPI_THREE_WIRE_MASK;
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regmap_write(priv->regmap, CS42L43_SPI_CONFIG1, spi_config1);
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return 0;
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}
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static int cs42l43_prepare_transfer_hardware(struct spi_controller *ctlr)
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{
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struct cs42l43_spi *priv = spi_controller_get_devdata(ctlr);
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int ret;
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ret = regmap_write(priv->regmap, CS42L43_BLOCK_EN2, CS42L43_SPI_MSTR_EN_MASK);
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if (ret)
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dev_err(priv->dev, "Failed to enable SPI controller: %d\n", ret);
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return ret;
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}
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static int cs42l43_unprepare_transfer_hardware(struct spi_controller *ctlr)
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{
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struct cs42l43_spi *priv = spi_controller_get_devdata(ctlr);
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int ret;
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ret = regmap_write(priv->regmap, CS42L43_BLOCK_EN2, 0);
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if (ret)
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dev_err(priv->dev, "Failed to disable SPI controller: %d\n", ret);
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return ret;
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}
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static size_t cs42l43_spi_max_length(struct spi_device *spi)
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{
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return CS42L43_SPI_MAX_LENGTH;
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}
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2024-06-11 06:25:54 -07:00
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static struct fwnode_handle *cs42l43_find_xu_node(struct fwnode_handle *fwnode)
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{
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static const u32 func_smart_amp = 0x1;
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struct fwnode_handle *child_fwnode, *ext_fwnode;
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u32 function;
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int ret;
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fwnode_for_each_child_node(fwnode, child_fwnode) {
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acpi_handle handle = ACPI_HANDLE_FWNODE(child_fwnode);
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ret = acpi_get_local_address(handle, &function);
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if (ret || function != func_smart_amp)
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continue;
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ext_fwnode = fwnode_get_named_child_node(child_fwnode,
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"mipi-sdca-function-expansion-subproperties");
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if (!ext_fwnode)
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continue;
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fwnode_handle_put(child_fwnode);
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return ext_fwnode;
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}
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2024-06-11 06:25:54 -07:00
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return NULL;
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2024-04-16 03:09:04 -07:00
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}
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2024-06-19 05:17:03 -07:00
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static struct spi_board_info *cs42l43_create_bridge_amp(struct cs42l43_spi *priv,
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const char * const name,
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int cs, int spkid)
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{
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struct property_entry *props = NULL;
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struct software_node *swnode;
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struct spi_board_info *info;
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if (spkid >= 0) {
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props = devm_kmalloc(priv->dev, sizeof(*props), GFP_KERNEL);
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if (!props)
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return NULL;
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*props = PROPERTY_ENTRY_U32("cirrus,speaker-id", spkid);
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}
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swnode = devm_kmalloc(priv->dev, sizeof(*swnode), GFP_KERNEL);
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if (!swnode)
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return NULL;
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*swnode = SOFTWARE_NODE(name, props, NULL);
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info = devm_kmemdup(priv->dev, &_info_template,
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sizeof(amp_info_template), GFP_KERNEL);
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if (!info)
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return NULL;
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info->chip_select = cs;
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info->swnode = swnode;
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return info;
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}
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2024-02-02 03:34:30 -07:00
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static void cs42l43_release_of_node(void *data)
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{
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fwnode_handle_put(data);
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}
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2024-04-16 03:09:04 -07:00
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static void cs42l43_release_sw_node(void *data)
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{
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software_node_unregister(&cs42l43_gpiochip_swnode);
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}
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2023-08-04 03:46:01 -07:00
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static int cs42l43_spi_probe(struct platform_device *pdev)
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{
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struct cs42l43 *cs42l43 = dev_get_drvdata(pdev->dev.parent);
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struct cs42l43_spi *priv;
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struct fwnode_handle *fwnode = dev_fwnode(cs42l43->dev);
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2024-06-11 06:25:54 -07:00
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struct fwnode_handle *xu_fwnode __free(fwnode_handle) = cs42l43_find_xu_node(fwnode);
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int nsidecars = 0;
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2023-08-04 03:46:01 -07:00
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int ret;
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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2023-11-28 02:30:30 -07:00
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priv->ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*priv->ctlr));
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2023-08-04 03:46:01 -07:00
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if (!priv->ctlr)
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return -ENOMEM;
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spi_controller_set_devdata(priv->ctlr, priv);
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priv->dev = &pdev->dev;
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priv->regmap = cs42l43->regmap;
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priv->ctlr->prepare_message = cs42l43_prepare_message;
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priv->ctlr->prepare_transfer_hardware = cs42l43_prepare_transfer_hardware;
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priv->ctlr->unprepare_transfer_hardware = cs42l43_unprepare_transfer_hardware;
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priv->ctlr->transfer_one = cs42l43_transfer_one;
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priv->ctlr->set_cs = cs42l43_set_cs;
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priv->ctlr->max_transfer_size = cs42l43_spi_max_length;
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priv->ctlr->mode_bits = SPI_3WIRE | SPI_MODE_X_MASK;
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priv->ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX;
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priv->ctlr->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
|
|
|
|
SPI_BPW_MASK(32);
|
|
|
|
priv->ctlr->min_speed_hz = CS42L43_SPI_ROOT_HZ /
|
|
|
|
cs42l43_clock_divs[ARRAY_SIZE(cs42l43_clock_divs) - 1];
|
|
|
|
priv->ctlr->max_speed_hz = CS42L43_SPI_ROOT_HZ / cs42l43_clock_divs[0];
|
|
|
|
priv->ctlr->use_gpio_descriptors = true;
|
|
|
|
priv->ctlr->auto_runtime_pm = true;
|
|
|
|
|
2024-01-24 10:41:01 -07:00
|
|
|
ret = devm_pm_runtime_enable(priv->dev);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2023-08-04 03:46:01 -07:00
|
|
|
pm_runtime_idle(priv->dev);
|
|
|
|
|
|
|
|
regmap_write(priv->regmap, CS42L43_TRAN_CONFIG6, CS42L43_FIFO_SIZE - 1);
|
|
|
|
regmap_write(priv->regmap, CS42L43_TRAN_CONFIG7, CS42L43_FIFO_SIZE - 1);
|
|
|
|
|
|
|
|
// Disable Watchdog timer and enable stall
|
|
|
|
regmap_write(priv->regmap, CS42L43_SPI_CONFIG3, 0);
|
|
|
|
regmap_write(priv->regmap, CS42L43_SPI_CONFIG4, CS42L43_SPI_STALL_ENA_MASK);
|
|
|
|
|
2024-02-02 03:34:30 -07:00
|
|
|
if (is_of_node(fwnode)) {
|
|
|
|
fwnode = fwnode_get_named_child_node(fwnode, "spi");
|
2024-04-17 02:30:26 -07:00
|
|
|
ret = devm_add_action_or_reset(priv->dev, cs42l43_release_of_node, fwnode);
|
|
|
|
if (ret)
|
2024-02-02 03:34:30 -07:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2024-06-11 06:25:54 -07:00
|
|
|
fwnode_property_read_u32(xu_fwnode, "01fa-sidecar-instances", &nsidecars);
|
|
|
|
|
|
|
|
if (nsidecars) {
|
2024-04-16 03:09:04 -07:00
|
|
|
ret = software_node_register(&cs42l43_gpiochip_swnode);
|
|
|
|
if (ret)
|
|
|
|
return dev_err_probe(priv->dev, ret,
|
|
|
|
"Failed to register gpio swnode\n");
|
|
|
|
|
2024-04-17 02:30:26 -07:00
|
|
|
ret = devm_add_action_or_reset(priv->dev, cs42l43_release_sw_node, NULL);
|
|
|
|
if (ret)
|
2024-04-16 03:09:04 -07:00
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = device_create_managed_software_node(&priv->ctlr->dev,
|
|
|
|
cs42l43_cs_props, NULL);
|
|
|
|
if (ret)
|
|
|
|
return dev_err_probe(priv->dev, ret, "Failed to add swnode\n");
|
|
|
|
} else {
|
|
|
|
device_set_node(&priv->ctlr->dev, fwnode);
|
|
|
|
}
|
2024-02-02 03:34:30 -07:00
|
|
|
|
2023-08-04 03:46:01 -07:00
|
|
|
ret = devm_spi_register_controller(priv->dev, priv->ctlr);
|
2024-04-16 03:09:04 -07:00
|
|
|
if (ret)
|
|
|
|
return dev_err_probe(priv->dev, ret,
|
|
|
|
"Failed to register SPI controller\n");
|
|
|
|
|
2024-06-11 06:25:54 -07:00
|
|
|
if (nsidecars) {
|
2024-06-19 05:17:03 -07:00
|
|
|
struct spi_board_info *ampl_info;
|
|
|
|
struct spi_board_info *ampr_info;
|
|
|
|
int spkid = -EINVAL;
|
|
|
|
|
|
|
|
fwnode_property_read_u32(xu_fwnode, "01fa-spk-id-val", &spkid);
|
|
|
|
|
|
|
|
dev_dbg(priv->dev, "Found speaker ID %d\n", spkid);
|
|
|
|
|
|
|
|
ampl_info = cs42l43_create_bridge_amp(priv, "cs35l56-left", 0, spkid);
|
|
|
|
if (!ampl_info)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
ampr_info = cs42l43_create_bridge_amp(priv, "cs35l56-right", 1, spkid);
|
|
|
|
if (!ampr_info)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
if (!spi_new_device(priv->ctlr, ampl_info))
|
2024-04-16 03:09:04 -07:00
|
|
|
return dev_err_probe(priv->dev, -ENODEV,
|
|
|
|
"Failed to create left amp slave\n");
|
|
|
|
|
2024-06-19 05:17:03 -07:00
|
|
|
if (!spi_new_device(priv->ctlr, ampr_info))
|
2024-04-16 03:09:04 -07:00
|
|
|
return dev_err_probe(priv->dev, -ENODEV,
|
|
|
|
"Failed to create right amp slave\n");
|
2023-08-04 03:46:01 -07:00
|
|
|
}
|
|
|
|
|
2024-04-16 03:09:04 -07:00
|
|
|
return 0;
|
2023-08-04 03:46:01 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static const struct platform_device_id cs42l43_spi_id_table[] = {
|
|
|
|
{ "cs42l43-spi", },
|
|
|
|
{}
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(platform, cs42l43_spi_id_table);
|
|
|
|
|
|
|
|
static struct platform_driver cs42l43_spi_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "cs42l43-spi",
|
|
|
|
},
|
|
|
|
.probe = cs42l43_spi_probe,
|
|
|
|
.id_table = cs42l43_spi_id_table,
|
|
|
|
};
|
|
|
|
module_platform_driver(cs42l43_spi_driver);
|
|
|
|
|
2024-04-16 03:09:04 -07:00
|
|
|
MODULE_IMPORT_NS(GPIO_SWNODE);
|
2023-08-04 03:46:01 -07:00
|
|
|
MODULE_DESCRIPTION("CS42L43 SPI Driver");
|
|
|
|
MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>");
|
|
|
|
MODULE_AUTHOR("Maciej Strozek <mstrozek@opensource.cirrus.com>");
|
|
|
|
MODULE_LICENSE("GPL");
|