2023-01-30 08:16:16 -07:00
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2022 Baylibre, SAS.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/mdio-mux.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#define ETH_REG2 0x0
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#define REG2_PHYID GENMASK(21, 0)
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#define EPHY_GXL_ID 0x110181
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#define REG2_LEDACT GENMASK(23, 22)
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#define REG2_LEDLINK GENMASK(25, 24)
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#define REG2_DIV4SEL BIT(27)
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#define REG2_ADCBYPASS BIT(30)
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#define REG2_CLKINSEL BIT(31)
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#define ETH_REG3 0x4
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#define REG3_ENH BIT(3)
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#define REG3_CFGMODE GENMASK(6, 4)
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#define REG3_AUTOMDIX BIT(7)
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#define REG3_PHYADDR GENMASK(12, 8)
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#define REG3_PWRUPRST BIT(21)
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#define REG3_PWRDOWN BIT(22)
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#define REG3_LEDPOL BIT(23)
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#define REG3_PHYMDI BIT(26)
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#define REG3_CLKINEN BIT(29)
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#define REG3_PHYIP BIT(30)
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#define REG3_PHYEN BIT(31)
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#define ETH_REG4 0x8
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#define REG4_PWRUPRSTSIG BIT(0)
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#define MESON_GXL_MDIO_EXTERNAL_ID 0
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#define MESON_GXL_MDIO_INTERNAL_ID 1
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struct gxl_mdio_mux {
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void __iomem *regs;
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void *mux_handle;
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};
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static void gxl_enable_internal_mdio(struct gxl_mdio_mux *priv)
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{
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u32 val;
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/* Setup the internal phy */
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val = (REG3_ENH |
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FIELD_PREP(REG3_CFGMODE, 0x7) |
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REG3_AUTOMDIX |
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FIELD_PREP(REG3_PHYADDR, 8) |
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REG3_LEDPOL |
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REG3_PHYMDI |
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REG3_CLKINEN |
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REG3_PHYIP);
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writel(REG4_PWRUPRSTSIG, priv->regs + ETH_REG4);
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writel(val, priv->regs + ETH_REG3);
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mdelay(10);
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/* NOTE: The HW kept the phy id configurable at runtime.
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* The id below is arbitrary. It is the one used in the vendor code.
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* The only constraint is that it must match the one in
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* drivers/net/phy/meson-gxl.c to properly match the PHY.
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*/
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writel(FIELD_PREP(REG2_PHYID, EPHY_GXL_ID),
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priv->regs + ETH_REG2);
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/* Enable the internal phy */
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val |= REG3_PHYEN;
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writel(val, priv->regs + ETH_REG3);
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writel(0, priv->regs + ETH_REG4);
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/* The phy needs a bit of time to power up */
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mdelay(10);
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}
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static void gxl_enable_external_mdio(struct gxl_mdio_mux *priv)
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{
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/* Reset the mdio bus mux to the external phy */
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writel(0, priv->regs + ETH_REG3);
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}
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static int gxl_mdio_switch_fn(int current_child, int desired_child,
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void *data)
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{
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struct gxl_mdio_mux *priv = dev_get_drvdata(data);
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if (current_child == desired_child)
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return 0;
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switch (desired_child) {
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case MESON_GXL_MDIO_EXTERNAL_ID:
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gxl_enable_external_mdio(priv);
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break;
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case MESON_GXL_MDIO_INTERNAL_ID:
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gxl_enable_internal_mdio(priv);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static const struct of_device_id gxl_mdio_mux_match[] = {
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{ .compatible = "amlogic,gxl-mdio-mux", },
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{},
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};
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MODULE_DEVICE_TABLE(of, gxl_mdio_mux_match);
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static int gxl_mdio_mux_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct gxl_mdio_mux *priv;
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struct clk *rclk;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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platform_set_drvdata(pdev, priv);
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priv->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->regs))
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return PTR_ERR(priv->regs);
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rclk = devm_clk_get_enabled(dev, "ref");
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if (IS_ERR(rclk))
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return dev_err_probe(dev, PTR_ERR(rclk),
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"failed to get reference clock\n");
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ret = mdio_mux_init(dev, dev->of_node, gxl_mdio_switch_fn,
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&priv->mux_handle, dev, NULL);
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if (ret)
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dev_err_probe(dev, ret, "mdio multiplexer init failed\n");
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return ret;
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}
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2023-09-18 12:50:57 -07:00
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static void gxl_mdio_mux_remove(struct platform_device *pdev)
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2023-01-30 08:16:16 -07:00
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{
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struct gxl_mdio_mux *priv = platform_get_drvdata(pdev);
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mdio_mux_uninit(priv->mux_handle);
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}
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static struct platform_driver gxl_mdio_mux_driver = {
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.probe = gxl_mdio_mux_probe,
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2023-09-18 12:50:57 -07:00
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.remove_new = gxl_mdio_mux_remove,
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2023-01-30 08:16:16 -07:00
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.driver = {
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.name = "gxl-mdio-mux",
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.of_match_table = gxl_mdio_mux_match,
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},
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};
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module_platform_driver(gxl_mdio_mux_driver);
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MODULE_DESCRIPTION("Amlogic GXL MDIO multiplexer driver");
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MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
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MODULE_LICENSE("GPL");
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