2020-03-05 21:28:19 -07:00
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
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2024-04-16 16:10:13 -07:00
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* Copyright (C) 2019-2024 Linaro Ltd.
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2020-03-05 21:28:19 -07:00
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*/
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#include <linux/dma-mapping.h>
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2024-04-16 16:10:18 -07:00
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#include <linux/io.h>
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2020-05-04 10:58:58 -07:00
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#include <linux/iommu.h>
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2024-03-01 10:02:39 -07:00
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#include <linux/platform_device.h>
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2024-04-16 16:10:18 -07:00
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#include <linux/types.h>
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2020-05-04 10:58:59 -07:00
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#include <linux/soc/qcom/smem.h>
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2020-03-05 21:28:19 -07:00
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2024-04-16 16:10:18 -07:00
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#include "gsi_trans.h"
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2020-03-05 21:28:19 -07:00
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#include "ipa.h"
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#include "ipa_cmd.h"
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2024-04-16 16:10:18 -07:00
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#include "ipa_data.h"
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2020-03-05 21:28:19 -07:00
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#include "ipa_mem.h"
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2024-04-16 16:10:18 -07:00
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#include "ipa_reg.h"
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2020-03-05 21:28:19 -07:00
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#include "ipa_table.h"
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/* "Canary" value placed between memory regions to detect overflow */
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#define IPA_MEM_CANARY_VAL cpu_to_le32(0xdeadbeef)
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2020-05-04 10:58:59 -07:00
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/* SMEM host id representing the modem. */
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#define QCOM_SMEM_HOST_MODEM 1
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2021-06-10 12:23:07 -07:00
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const struct ipa_mem *ipa_mem_find(struct ipa *ipa, enum ipa_mem_id mem_id)
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{
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2021-06-10 12:23:08 -07:00
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u32 i;
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for (i = 0; i < ipa->mem_count; i++) {
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const struct ipa_mem *mem = &ipa->mem[i];
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if (mem->id == mem_id)
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return mem;
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}
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2021-06-10 12:23:07 -07:00
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return NULL;
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}
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2020-03-05 21:28:19 -07:00
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/* Add an immediate command to a transaction that zeroes a memory region */
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static void
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2021-06-10 12:23:04 -07:00
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ipa_mem_zero_region_add(struct gsi_trans *trans, enum ipa_mem_id mem_id)
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2020-03-05 21:28:19 -07:00
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{
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struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi);
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2021-06-10 12:23:07 -07:00
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const struct ipa_mem *mem = ipa_mem_find(ipa, mem_id);
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2020-03-05 21:28:19 -07:00
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dma_addr_t addr = ipa->zero_addr;
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if (!mem->size)
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return;
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ipa_cmd_dma_shared_mem_add(trans, mem->offset, mem->size, addr, true);
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}
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/**
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* ipa_mem_setup() - Set up IPA AP and modem shared memory areas
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2020-07-13 05:24:18 -07:00
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* @ipa: IPA pointer
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2020-03-05 21:28:19 -07:00
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*
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* Set up the shared memory regions in IPA local memory. This involves
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* zero-filling memory regions, and in the case of header memory, telling
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* the IPA where it's located.
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*
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* This function performs the initial setup of this memory. If the modem
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* crashes, its regions are re-zeroed in ipa_mem_zero_modem().
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*
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* The AP informs the modem where its portions of memory are located
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* in a QMI exchange that occurs at modem startup.
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*
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2021-04-09 11:07:20 -07:00
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* There is no need for a matching ipa_mem_teardown() function.
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*
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2020-07-13 05:24:18 -07:00
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* Return: 0 if successful, or a negative error code
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2020-03-05 21:28:19 -07:00
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*/
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int ipa_mem_setup(struct ipa *ipa)
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{
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dma_addr_t addr = ipa->zero_addr;
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2021-06-10 12:23:07 -07:00
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const struct ipa_mem *mem;
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2020-03-05 21:28:19 -07:00
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struct gsi_trans *trans;
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2024-03-01 10:02:39 -07:00
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const struct reg *reg;
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2020-03-05 21:28:19 -07:00
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u32 offset;
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u16 size;
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2021-03-24 06:15:26 -07:00
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u32 val;
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2020-03-05 21:28:19 -07:00
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/* Get a transaction to define the header memory region and to zero
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* the processing context and modem memory regions.
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*/
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trans = ipa_cmd_trans_alloc(ipa, 4);
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if (!trans) {
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2024-03-01 10:02:42 -07:00
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dev_err(ipa->dev, "no transaction for memory setup\n");
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2020-03-05 21:28:19 -07:00
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return -EBUSY;
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}
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2021-06-10 12:23:07 -07:00
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/* Initialize IPA-local header memory. The AP header region, if
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* present, is contiguous with and follows the modem header region,
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* and they are initialized together.
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2020-03-05 21:28:19 -07:00
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*/
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2021-06-10 12:23:07 -07:00
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mem = ipa_mem_find(ipa, IPA_MEM_MODEM_HEADER);
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offset = mem->offset;
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size = mem->size;
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mem = ipa_mem_find(ipa, IPA_MEM_AP_HEADER);
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if (mem)
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size += mem->size;
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2020-03-05 21:28:19 -07:00
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ipa_cmd_hdr_init_local_add(trans, offset, size, addr);
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2021-06-10 12:23:04 -07:00
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ipa_mem_zero_region_add(trans, IPA_MEM_MODEM_PROC_CTX);
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ipa_mem_zero_region_add(trans, IPA_MEM_AP_PROC_CTX);
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ipa_mem_zero_region_add(trans, IPA_MEM_MODEM);
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2020-03-05 21:28:19 -07:00
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gsi_trans_commit_wait(trans);
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/* Tell the hardware where the processing context area is located */
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2021-06-10 12:23:07 -07:00
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mem = ipa_mem_find(ipa, IPA_MEM_MODEM_PROC_CTX);
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offset = ipa->mem_offset + mem->offset;
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2022-09-26 15:09:18 -07:00
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2022-09-26 15:09:21 -07:00
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reg = ipa_reg(ipa, LOCAL_PKT_PROC_CNTXT);
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2023-02-08 13:56:53 -07:00
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val = reg_encode(reg, IPA_BASE_ADDR, offset);
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2023-02-08 13:56:52 -07:00
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iowrite32(val, ipa->reg_virt + reg_offset(reg));
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2020-03-05 21:28:19 -07:00
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return 0;
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}
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2021-06-09 15:35:01 -07:00
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/* Is the given memory region ID is valid for the current IPA version? */
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static bool ipa_mem_id_valid(struct ipa *ipa, enum ipa_mem_id mem_id)
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{
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enum ipa_version version = ipa->version;
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switch (mem_id) {
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case IPA_MEM_UC_SHARED:
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case IPA_MEM_UC_INFO:
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case IPA_MEM_V4_FILTER_HASHED:
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case IPA_MEM_V4_FILTER:
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case IPA_MEM_V6_FILTER_HASHED:
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case IPA_MEM_V6_FILTER:
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case IPA_MEM_V4_ROUTE_HASHED:
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case IPA_MEM_V4_ROUTE:
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case IPA_MEM_V6_ROUTE_HASHED:
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case IPA_MEM_V6_ROUTE:
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case IPA_MEM_MODEM_HEADER:
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case IPA_MEM_AP_HEADER:
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case IPA_MEM_MODEM_PROC_CTX:
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case IPA_MEM_AP_PROC_CTX:
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case IPA_MEM_MODEM:
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case IPA_MEM_UC_EVENT_RING:
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case IPA_MEM_PDN_CONFIG:
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case IPA_MEM_STATS_QUOTA_MODEM:
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case IPA_MEM_STATS_QUOTA_AP:
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case IPA_MEM_END_MARKER: /* pseudo region */
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break;
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case IPA_MEM_STATS_TETHERING:
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case IPA_MEM_STATS_DROP:
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if (version < IPA_VERSION_4_0)
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return false;
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break;
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case IPA_MEM_STATS_V4_FILTER:
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case IPA_MEM_STATS_V6_FILTER:
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case IPA_MEM_STATS_V4_ROUTE:
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case IPA_MEM_STATS_V6_ROUTE:
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if (version < IPA_VERSION_4_0 || version > IPA_VERSION_4_2)
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return false;
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break;
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2023-01-30 14:01:58 -07:00
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case IPA_MEM_AP_V4_FILTER:
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case IPA_MEM_AP_V6_FILTER:
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2023-11-22 16:09:07 -07:00
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if (version < IPA_VERSION_5_0)
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2023-01-30 14:01:58 -07:00
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return false;
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break;
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2021-06-09 15:35:01 -07:00
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case IPA_MEM_NAT_TABLE:
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case IPA_MEM_STATS_FILTER_ROUTE:
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if (version < IPA_VERSION_4_5)
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return false;
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break;
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default:
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return false;
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}
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return true;
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}
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2021-06-09 15:35:00 -07:00
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/* Must the given memory region be present in the configuration? */
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static bool ipa_mem_id_required(struct ipa *ipa, enum ipa_mem_id mem_id)
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{
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switch (mem_id) {
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case IPA_MEM_UC_SHARED:
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case IPA_MEM_UC_INFO:
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case IPA_MEM_V4_FILTER_HASHED:
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case IPA_MEM_V4_FILTER:
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case IPA_MEM_V6_FILTER_HASHED:
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case IPA_MEM_V6_FILTER:
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case IPA_MEM_V4_ROUTE_HASHED:
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case IPA_MEM_V4_ROUTE:
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case IPA_MEM_V6_ROUTE_HASHED:
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case IPA_MEM_V6_ROUTE:
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case IPA_MEM_MODEM_HEADER:
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case IPA_MEM_MODEM_PROC_CTX:
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case IPA_MEM_AP_PROC_CTX:
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case IPA_MEM_MODEM:
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return true;
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case IPA_MEM_PDN_CONFIG:
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case IPA_MEM_STATS_QUOTA_MODEM:
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return ipa->version >= IPA_VERSION_4_0;
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2022-10-27 05:26:27 -07:00
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case IPA_MEM_STATS_TETHERING:
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return ipa->version >= IPA_VERSION_4_0 &&
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ipa->version != IPA_VERSION_5_0;
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2021-06-09 15:35:00 -07:00
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default:
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return false; /* Anything else is optional */
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}
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}
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2021-06-09 15:34:56 -07:00
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static bool ipa_mem_valid_one(struct ipa *ipa, const struct ipa_mem *mem)
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2020-03-05 21:28:19 -07:00
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{
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2021-06-09 15:34:55 -07:00
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enum ipa_mem_id mem_id = mem->id;
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2024-03-01 10:02:42 -07:00
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struct device *dev = ipa->dev;
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2020-03-05 21:28:19 -07:00
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u16 size_multiple;
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2021-06-09 15:35:01 -07:00
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/* Make sure the memory region is valid for this version of IPA */
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if (!ipa_mem_id_valid(ipa, mem_id)) {
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dev_err(dev, "region id %u not valid\n", mem_id);
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return false;
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}
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2021-06-10 12:23:08 -07:00
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if (!mem->size && !mem->canary_count) {
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dev_err(dev, "empty memory region %u\n", mem_id);
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return false;
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}
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2020-03-05 21:28:19 -07:00
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/* Other than modem memory, sizes must be a multiple of 8 */
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size_multiple = mem_id == IPA_MEM_MODEM ? 4 : 8;
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if (mem->size % size_multiple)
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dev_err(dev, "region %u size not a multiple of %u bytes\n",
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mem_id, size_multiple);
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else if (mem->offset % 8)
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dev_err(dev, "region %u offset not 8-byte aligned\n", mem_id);
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else if (mem->offset < mem->canary_count * sizeof(__le32))
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dev_err(dev, "region %u offset too small for %hu canaries\n",
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mem_id, mem->canary_count);
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2021-06-09 15:34:53 -07:00
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else if (mem_id == IPA_MEM_END_MARKER && mem->size)
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dev_err(dev, "non-zero end marker region size\n");
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2020-03-05 21:28:19 -07:00
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else
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return true;
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return false;
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}
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2021-06-09 15:34:56 -07:00
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/* Verify each defined memory region is valid. */
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2021-06-09 15:34:59 -07:00
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static bool ipa_mem_valid(struct ipa *ipa, const struct ipa_mem_data *mem_data)
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2021-06-09 15:34:56 -07:00
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{
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2021-06-09 15:35:02 -07:00
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DECLARE_BITMAP(regions, IPA_MEM_COUNT) = { };
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2024-03-01 10:02:42 -07:00
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struct device *dev = ipa->dev;
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2021-06-09 15:34:56 -07:00
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enum ipa_mem_id mem_id;
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2021-06-10 12:23:01 -07:00
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u32 i;
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2021-06-09 15:34:56 -07:00
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2021-06-09 15:34:59 -07:00
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if (mem_data->local_count > IPA_MEM_COUNT) {
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dev_err(dev, "too many memory regions (%u > %u)\n",
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mem_data->local_count, IPA_MEM_COUNT);
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return false;
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}
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2021-06-10 12:23:01 -07:00
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for (i = 0; i < mem_data->local_count; i++) {
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const struct ipa_mem *mem = &mem_data->local[i];
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2021-06-09 15:34:56 -07:00
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2021-06-09 15:35:02 -07:00
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if (__test_and_set_bit(mem->id, regions)) {
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dev_err(dev, "duplicate memory region %u\n", mem->id);
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return false;
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}
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2021-06-09 15:34:56 -07:00
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/* Defined regions have non-zero size and/or canary count */
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2021-06-10 12:23:08 -07:00
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if (!ipa_mem_valid_one(ipa, mem))
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2021-06-09 15:34:56 -07:00
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return false;
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}
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2021-06-09 15:35:00 -07:00
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/* Now see if any required regions are not defined */
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2021-11-18 12:37:15 -07:00
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for_each_clear_bit(mem_id, regions, IPA_MEM_COUNT) {
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2021-06-09 15:35:03 -07:00
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if (ipa_mem_id_required(ipa, mem_id))
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2021-06-09 15:35:00 -07:00
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dev_err(dev, "required memory region %u missing\n",
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mem_id);
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2021-06-09 15:35:03 -07:00
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}
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2021-06-09 15:35:00 -07:00
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2021-06-09 15:34:56 -07:00
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return true;
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}
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2021-06-09 15:34:57 -07:00
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/* Do all memory regions fit within the IPA local memory? */
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static bool ipa_mem_size_valid(struct ipa *ipa)
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{
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2024-03-01 10:02:42 -07:00
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struct device *dev = ipa->dev;
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2021-06-09 15:34:57 -07:00
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u32 limit = ipa->mem_size;
|
2021-06-10 12:23:01 -07:00
|
|
|
u32 i;
|
2021-06-09 15:34:57 -07:00
|
|
|
|
2021-06-10 12:23:01 -07:00
|
|
|
for (i = 0; i < ipa->mem_count; i++) {
|
|
|
|
const struct ipa_mem *mem = &ipa->mem[i];
|
2021-06-09 15:34:57 -07:00
|
|
|
|
|
|
|
if (mem->offset + mem->size <= limit)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
dev_err(dev, "region %u ends beyond memory limit (0x%08x)\n",
|
2021-06-10 12:23:01 -07:00
|
|
|
mem->id, limit);
|
2021-06-09 15:34:57 -07:00
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2020-03-05 21:28:19 -07:00
|
|
|
/**
|
|
|
|
* ipa_mem_config() - Configure IPA shared memory
|
2020-07-13 05:24:18 -07:00
|
|
|
* @ipa: IPA pointer
|
2020-03-05 21:28:19 -07:00
|
|
|
*
|
2020-07-13 05:24:18 -07:00
|
|
|
* Return: 0 if successful, or a negative error code
|
2020-03-05 21:28:19 -07:00
|
|
|
*/
|
|
|
|
int ipa_mem_config(struct ipa *ipa)
|
|
|
|
{
|
2024-03-01 10:02:42 -07:00
|
|
|
struct device *dev = ipa->dev;
|
2021-06-10 12:23:07 -07:00
|
|
|
const struct ipa_mem *mem;
|
net: ipa: start generalizing "ipa_reg"
IPA register definitions have evolved with each new version. The
changes required to support more than 32 endpoints in IPA v5.0 made
it best to define a unified mechanism for defining registers and
their fields.
GSI register definitions, meanwhile, have remained fairly stable.
And even as the total number of IPA endpoints goes beyond 32, the
number of GSI channels on a given EE that underly endpoints still
remains 32 or less.
Despite that, GSI v3.0 (which is used with IPA v5.0) extends the
number of channels (and events) it supports to be about 256, and as
a result, many GSI register definitions must change significantly.
To address this, we'll use the same "ipa_reg" mechanism to define
the GSI registers.
As a first step in generalizing the "ipa_reg" to also support GSI
registers, isolate the definitions of the "ipa_reg" and "ipa_regs"
structure types (and some supporting macros) into a new header file,
and remove the "ipa_" and "IPA_" from symbol names.
Separate the IPA register ID validity checking from the generic
check that a register ID is in range. Aside from that, this is
intended to have no functional effect on the code.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2023-02-08 13:56:51 -07:00
|
|
|
const struct reg *reg;
|
2020-03-05 21:28:19 -07:00
|
|
|
dma_addr_t addr;
|
|
|
|
u32 mem_size;
|
|
|
|
void *virt;
|
|
|
|
u32 val;
|
2021-06-10 12:23:01 -07:00
|
|
|
u32 i;
|
2020-03-05 21:28:19 -07:00
|
|
|
|
|
|
|
/* Check the advertised location and size of the shared memory area */
|
2022-09-26 15:09:21 -07:00
|
|
|
reg = ipa_reg(ipa, SHARED_MEM_SIZE);
|
2023-02-08 13:56:52 -07:00
|
|
|
val = ioread32(ipa->reg_virt + reg_offset(reg));
|
2020-03-05 21:28:19 -07:00
|
|
|
|
|
|
|
/* The fields in the register are in 8 byte units */
|
2023-02-08 13:56:53 -07:00
|
|
|
ipa->mem_offset = 8 * reg_decode(reg, MEM_BADDR, val);
|
2022-09-26 15:09:25 -07:00
|
|
|
|
2020-03-05 21:28:19 -07:00
|
|
|
/* Make sure the end is within the region's mapped space */
|
2023-02-08 13:56:53 -07:00
|
|
|
mem_size = 8 * reg_decode(reg, MEM_SIZE, val);
|
2020-03-05 21:28:19 -07:00
|
|
|
|
|
|
|
/* If the sizes don't match, issue a warning */
|
2020-11-09 09:56:34 -07:00
|
|
|
if (ipa->mem_offset + mem_size < ipa->mem_size) {
|
2020-03-05 21:28:19 -07:00
|
|
|
dev_warn(dev, "limiting IPA memory size to 0x%08x\n",
|
|
|
|
mem_size);
|
|
|
|
ipa->mem_size = mem_size;
|
2020-11-09 09:56:34 -07:00
|
|
|
} else if (ipa->mem_offset + mem_size > ipa->mem_size) {
|
|
|
|
dev_dbg(dev, "ignoring larger reported memory size: 0x%08x\n",
|
|
|
|
mem_size);
|
2020-03-05 21:28:19 -07:00
|
|
|
}
|
|
|
|
|
2021-06-09 15:34:57 -07:00
|
|
|
/* We know our memory size; make sure regions are all in range */
|
|
|
|
if (!ipa_mem_size_valid(ipa))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2020-03-05 21:28:19 -07:00
|
|
|
/* Prealloc DMA memory for zeroing regions */
|
|
|
|
virt = dma_alloc_coherent(dev, IPA_MEM_MAX, &addr, GFP_KERNEL);
|
|
|
|
if (!virt)
|
|
|
|
return -ENOMEM;
|
|
|
|
ipa->zero_addr = addr;
|
|
|
|
ipa->zero_virt = virt;
|
|
|
|
ipa->zero_size = IPA_MEM_MAX;
|
|
|
|
|
2021-06-10 12:23:01 -07:00
|
|
|
/* For each defined region, write "canary" values in the
|
|
|
|
* space prior to the region's base address if indicated.
|
2020-03-05 21:28:19 -07:00
|
|
|
*/
|
2021-06-10 12:23:01 -07:00
|
|
|
for (i = 0; i < ipa->mem_count; i++) {
|
2021-06-10 12:23:08 -07:00
|
|
|
u16 canary_count = ipa->mem[i].canary_count;
|
2020-03-05 21:28:19 -07:00
|
|
|
__le32 *canary;
|
|
|
|
|
|
|
|
if (!canary_count)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
/* Write canary values in the space before the region */
|
2021-06-10 12:23:08 -07:00
|
|
|
canary = ipa->mem_virt + ipa->mem_offset + ipa->mem[i].offset;
|
2020-03-05 21:28:19 -07:00
|
|
|
do
|
|
|
|
*--canary = IPA_MEM_CANARY_VAL;
|
|
|
|
while (--canary_count);
|
|
|
|
}
|
|
|
|
|
2021-06-10 12:23:07 -07:00
|
|
|
/* Verify the microcontroller ring alignment (if defined) */
|
|
|
|
mem = ipa_mem_find(ipa, IPA_MEM_UC_EVENT_RING);
|
|
|
|
if (mem && mem->offset % 1024) {
|
2020-03-05 21:28:19 -07:00
|
|
|
dev_err(dev, "microcontroller ring not 1024-byte aligned\n");
|
|
|
|
goto err_dma_free;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_dma_free:
|
|
|
|
dma_free_coherent(dev, IPA_MEM_MAX, ipa->zero_virt, ipa->zero_addr);
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Inverse of ipa_mem_config() */
|
|
|
|
void ipa_mem_deconfig(struct ipa *ipa)
|
|
|
|
{
|
2024-03-01 10:02:42 -07:00
|
|
|
struct device *dev = ipa->dev;
|
2020-03-05 21:28:19 -07:00
|
|
|
|
|
|
|
dma_free_coherent(dev, ipa->zero_size, ipa->zero_virt, ipa->zero_addr);
|
|
|
|
ipa->zero_size = 0;
|
|
|
|
ipa->zero_virt = NULL;
|
|
|
|
ipa->zero_addr = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* ipa_mem_zero_modem() - Zero IPA-local memory regions owned by the modem
|
2020-07-13 05:24:18 -07:00
|
|
|
* @ipa: IPA pointer
|
2020-03-05 21:28:19 -07:00
|
|
|
*
|
|
|
|
* Zero regions of IPA-local memory used by the modem. These are configured
|
|
|
|
* (and initially zeroed) by ipa_mem_setup(), but if the modem crashes and
|
|
|
|
* restarts via SSR we need to re-initialize them. A QMI message tells the
|
|
|
|
* modem where to find regions of IPA local memory it needs to know about
|
|
|
|
* (these included).
|
|
|
|
*/
|
|
|
|
int ipa_mem_zero_modem(struct ipa *ipa)
|
|
|
|
{
|
|
|
|
struct gsi_trans *trans;
|
|
|
|
|
|
|
|
/* Get a transaction to zero the modem memory, modem header,
|
|
|
|
* and modem processing context regions.
|
|
|
|
*/
|
|
|
|
trans = ipa_cmd_trans_alloc(ipa, 3);
|
|
|
|
if (!trans) {
|
2024-03-01 10:02:42 -07:00
|
|
|
dev_err(ipa->dev, "no transaction to zero modem memory\n");
|
2020-03-05 21:28:19 -07:00
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
2021-06-10 12:23:04 -07:00
|
|
|
ipa_mem_zero_region_add(trans, IPA_MEM_MODEM_HEADER);
|
|
|
|
ipa_mem_zero_region_add(trans, IPA_MEM_MODEM_PROC_CTX);
|
|
|
|
ipa_mem_zero_region_add(trans, IPA_MEM_MODEM);
|
2020-03-05 21:28:19 -07:00
|
|
|
|
|
|
|
gsi_trans_commit_wait(trans);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-05-04 10:58:58 -07:00
|
|
|
/**
|
|
|
|
* ipa_imem_init() - Initialize IMEM memory used by the IPA
|
|
|
|
* @ipa: IPA pointer
|
|
|
|
* @addr: Physical address of the IPA region in IMEM
|
|
|
|
* @size: Size (bytes) of the IPA region in IMEM
|
|
|
|
*
|
|
|
|
* IMEM is a block of shared memory separate from system DRAM, and
|
|
|
|
* a portion of this memory is available for the IPA to use. The
|
|
|
|
* modem accesses this memory directly, but the IPA accesses it
|
|
|
|
* via the IOMMU, using the AP's credentials.
|
|
|
|
*
|
|
|
|
* If this region exists (size > 0) we map it for read/write access
|
|
|
|
* through the IOMMU using the IPA device.
|
|
|
|
*
|
|
|
|
* Note: @addr and @size are not guaranteed to be page-aligned.
|
|
|
|
*/
|
|
|
|
static int ipa_imem_init(struct ipa *ipa, unsigned long addr, size_t size)
|
|
|
|
{
|
2024-03-01 10:02:42 -07:00
|
|
|
struct device *dev = ipa->dev;
|
2020-05-04 10:58:58 -07:00
|
|
|
struct iommu_domain *domain;
|
|
|
|
unsigned long iova;
|
|
|
|
phys_addr_t phys;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!size)
|
|
|
|
return 0; /* IMEM memory not used */
|
|
|
|
|
|
|
|
domain = iommu_get_domain_for_dev(dev);
|
|
|
|
if (!domain) {
|
|
|
|
dev_err(dev, "no IOMMU domain found for IMEM\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Align the address down and the size up to page boundaries */
|
|
|
|
phys = addr & PAGE_MASK;
|
|
|
|
size = PAGE_ALIGN(size + addr - phys);
|
|
|
|
iova = phys; /* We just want a direct mapping */
|
|
|
|
|
2023-01-23 13:35:54 -07:00
|
|
|
ret = iommu_map(domain, iova, phys, size, IOMMU_READ | IOMMU_WRITE,
|
|
|
|
GFP_KERNEL);
|
2020-05-04 10:58:58 -07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ipa->imem_iova = iova;
|
|
|
|
ipa->imem_size = size;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ipa_imem_exit(struct ipa *ipa)
|
|
|
|
{
|
2024-03-01 10:02:42 -07:00
|
|
|
struct device *dev = ipa->dev;
|
2020-05-04 10:58:58 -07:00
|
|
|
struct iommu_domain *domain;
|
|
|
|
|
|
|
|
if (!ipa->imem_size)
|
|
|
|
return;
|
|
|
|
|
|
|
|
domain = iommu_get_domain_for_dev(dev);
|
|
|
|
if (domain) {
|
|
|
|
size_t size;
|
|
|
|
|
|
|
|
size = iommu_unmap(domain, ipa->imem_iova, ipa->imem_size);
|
|
|
|
if (size != ipa->imem_size)
|
2021-02-01 16:26:09 -07:00
|
|
|
dev_warn(dev, "unmapped %zu IMEM bytes, expected %zu\n",
|
2020-05-04 10:58:58 -07:00
|
|
|
size, ipa->imem_size);
|
|
|
|
} else {
|
|
|
|
dev_err(dev, "couldn't get IPA IOMMU domain for IMEM\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
ipa->imem_size = 0;
|
|
|
|
ipa->imem_iova = 0;
|
|
|
|
}
|
|
|
|
|
2020-05-04 10:58:59 -07:00
|
|
|
/**
|
|
|
|
* ipa_smem_init() - Initialize SMEM memory used by the IPA
|
|
|
|
* @ipa: IPA pointer
|
|
|
|
* @item: Item ID of SMEM memory
|
|
|
|
* @size: Size (bytes) of SMEM memory region
|
|
|
|
*
|
|
|
|
* SMEM is a managed block of shared DRAM, from which numbered "items"
|
|
|
|
* can be allocated. One item is designated for use by the IPA.
|
|
|
|
*
|
|
|
|
* The modem accesses SMEM memory directly, but the IPA accesses it
|
|
|
|
* via the IOMMU, using the AP's credentials.
|
|
|
|
*
|
|
|
|
* If size provided is non-zero, we allocate it and map it for
|
|
|
|
* access through the IOMMU.
|
|
|
|
*
|
|
|
|
* Note: @size and the item address are is not guaranteed to be page-aligned.
|
|
|
|
*/
|
|
|
|
static int ipa_smem_init(struct ipa *ipa, u32 item, size_t size)
|
|
|
|
{
|
2024-03-01 10:02:42 -07:00
|
|
|
struct device *dev = ipa->dev;
|
2020-05-04 10:58:59 -07:00
|
|
|
struct iommu_domain *domain;
|
|
|
|
unsigned long iova;
|
|
|
|
phys_addr_t phys;
|
|
|
|
phys_addr_t addr;
|
|
|
|
size_t actual;
|
|
|
|
void *virt;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!size)
|
|
|
|
return 0; /* SMEM memory not used */
|
|
|
|
|
|
|
|
/* SMEM is memory shared between the AP and another system entity
|
|
|
|
* (in this case, the modem). An allocation from SMEM is persistent
|
|
|
|
* until the AP reboots; there is no way to free an allocated SMEM
|
|
|
|
* region. Allocation only reserves the space; to use it you need
|
2021-06-10 12:23:07 -07:00
|
|
|
* to "get" a pointer it (this does not imply reference counting).
|
2020-05-04 10:58:59 -07:00
|
|
|
* The item might have already been allocated, in which case we
|
|
|
|
* use it unless the size isn't what we expect.
|
|
|
|
*/
|
|
|
|
ret = qcom_smem_alloc(QCOM_SMEM_HOST_MODEM, item, size);
|
|
|
|
if (ret && ret != -EEXIST) {
|
|
|
|
dev_err(dev, "error %d allocating size %zu SMEM item %u\n",
|
|
|
|
ret, size, item);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Now get the address of the SMEM memory region */
|
|
|
|
virt = qcom_smem_get(QCOM_SMEM_HOST_MODEM, item, &actual);
|
|
|
|
if (IS_ERR(virt)) {
|
|
|
|
ret = PTR_ERR(virt);
|
|
|
|
dev_err(dev, "error %d getting SMEM item %u\n", ret, item);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* In case the region was already allocated, verify the size */
|
|
|
|
if (ret && actual != size) {
|
|
|
|
dev_err(dev, "SMEM item %u has size %zu, expected %zu\n",
|
|
|
|
item, actual, size);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
domain = iommu_get_domain_for_dev(dev);
|
|
|
|
if (!domain) {
|
|
|
|
dev_err(dev, "no IOMMU domain found for SMEM\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Align the address down and the size up to a page boundary */
|
2022-08-18 06:42:05 -07:00
|
|
|
addr = qcom_smem_virt_to_phys(virt);
|
2020-05-04 10:58:59 -07:00
|
|
|
phys = addr & PAGE_MASK;
|
|
|
|
size = PAGE_ALIGN(size + addr - phys);
|
|
|
|
iova = phys; /* We just want a direct mapping */
|
|
|
|
|
2023-01-23 13:35:54 -07:00
|
|
|
ret = iommu_map(domain, iova, phys, size, IOMMU_READ | IOMMU_WRITE,
|
|
|
|
GFP_KERNEL);
|
2020-05-04 10:58:59 -07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ipa->smem_iova = iova;
|
|
|
|
ipa->smem_size = size;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ipa_smem_exit(struct ipa *ipa)
|
|
|
|
{
|
2024-03-01 10:02:42 -07:00
|
|
|
struct device *dev = ipa->dev;
|
2020-05-04 10:58:59 -07:00
|
|
|
struct iommu_domain *domain;
|
|
|
|
|
|
|
|
domain = iommu_get_domain_for_dev(dev);
|
|
|
|
if (domain) {
|
|
|
|
size_t size;
|
|
|
|
|
|
|
|
size = iommu_unmap(domain, ipa->smem_iova, ipa->smem_size);
|
|
|
|
if (size != ipa->smem_size)
|
2021-02-01 16:26:09 -07:00
|
|
|
dev_warn(dev, "unmapped %zu SMEM bytes, expected %zu\n",
|
2020-05-04 10:58:59 -07:00
|
|
|
size, ipa->smem_size);
|
|
|
|
|
|
|
|
} else {
|
|
|
|
dev_err(dev, "couldn't get IPA IOMMU domain for SMEM\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
ipa->smem_size = 0;
|
|
|
|
ipa->smem_iova = 0;
|
|
|
|
}
|
|
|
|
|
2020-03-05 21:28:19 -07:00
|
|
|
/* Perform memory region-related initialization */
|
2024-03-01 10:02:39 -07:00
|
|
|
int ipa_mem_init(struct ipa *ipa, struct platform_device *pdev,
|
|
|
|
const struct ipa_mem_data *mem_data)
|
2020-03-05 21:28:19 -07:00
|
|
|
{
|
2024-03-01 10:02:39 -07:00
|
|
|
struct device *dev = &pdev->dev;
|
2020-03-05 21:28:19 -07:00
|
|
|
struct resource *res;
|
|
|
|
int ret;
|
|
|
|
|
2021-06-09 15:34:59 -07:00
|
|
|
/* Make sure the set of defined memory regions is valid */
|
|
|
|
if (!ipa_mem_valid(ipa, mem_data))
|
2020-03-05 21:28:19 -07:00
|
|
|
return -EINVAL;
|
2021-06-09 15:34:59 -07:00
|
|
|
|
|
|
|
ipa->mem_count = mem_data->local_count;
|
|
|
|
ipa->mem = mem_data->local;
|
2020-03-05 21:28:19 -07:00
|
|
|
|
2022-10-21 12:13:40 -07:00
|
|
|
/* Check the route and filter table memory regions */
|
2022-10-25 12:51:42 -07:00
|
|
|
if (!ipa_table_mem_valid(ipa, false))
|
2022-10-21 12:13:40 -07:00
|
|
|
return -EINVAL;
|
2022-10-25 12:51:42 -07:00
|
|
|
if (!ipa_table_mem_valid(ipa, true))
|
2022-10-21 12:13:40 -07:00
|
|
|
return -EINVAL;
|
|
|
|
|
2024-03-01 10:02:39 -07:00
|
|
|
ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
|
2020-03-05 21:28:19 -07:00
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "error %d setting DMA mask\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2024-03-01 10:02:39 -07:00
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ipa-shared");
|
2020-03-05 21:28:19 -07:00
|
|
|
if (!res) {
|
|
|
|
dev_err(dev,
|
|
|
|
"DT error getting \"ipa-shared\" memory property\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
ipa->mem_virt = memremap(res->start, resource_size(res), MEMREMAP_WC);
|
|
|
|
if (!ipa->mem_virt) {
|
|
|
|
dev_err(dev, "unable to remap \"ipa-shared\" memory\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
ipa->mem_addr = res->start;
|
|
|
|
ipa->mem_size = resource_size(res);
|
|
|
|
|
2020-05-04 10:58:58 -07:00
|
|
|
ret = ipa_imem_init(ipa, mem_data->imem_addr, mem_data->imem_size);
|
|
|
|
if (ret)
|
|
|
|
goto err_unmap;
|
|
|
|
|
2020-05-04 10:58:59 -07:00
|
|
|
ret = ipa_smem_init(ipa, mem_data->smem_id, mem_data->smem_size);
|
|
|
|
if (ret)
|
|
|
|
goto err_imem_exit;
|
|
|
|
|
2020-03-05 21:28:19 -07:00
|
|
|
return 0;
|
2020-05-04 10:58:58 -07:00
|
|
|
|
2020-05-04 10:58:59 -07:00
|
|
|
err_imem_exit:
|
|
|
|
ipa_imem_exit(ipa);
|
2020-05-04 10:58:58 -07:00
|
|
|
err_unmap:
|
|
|
|
memunmap(ipa->mem_virt);
|
|
|
|
|
|
|
|
return ret;
|
2020-03-05 21:28:19 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Inverse of ipa_mem_init() */
|
|
|
|
void ipa_mem_exit(struct ipa *ipa)
|
|
|
|
{
|
2020-05-04 10:58:59 -07:00
|
|
|
ipa_smem_exit(ipa);
|
2020-05-04 10:58:58 -07:00
|
|
|
ipa_imem_exit(ipa);
|
2020-03-05 21:28:19 -07:00
|
|
|
memunmap(ipa->mem_virt);
|
|
|
|
}
|