License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 07:07:57 -07:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2006-10-19 01:31:22 -07:00
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#ifndef __ASM_SH_RENESAS_R7780RP_H
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#define __ASM_SH_RENESAS_R7780RP_H
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/* Box specific addresses. */
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2009-06-16 00:42:20 -07:00
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#define PA_NORFLASH_ADDR 0x00000000
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#define PA_NORFLASH_SIZE 0x04000000
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2006-10-19 01:31:22 -07:00
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#if defined(CONFIG_SH_R7780MP)
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#define PA_BCR 0xa4000000 /* FPGA */
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2007-03-11 22:38:59 -07:00
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#define PA_SDPOW (-1)
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2006-10-19 01:31:22 -07:00
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#define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
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#define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
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#define PA_IRLPRI1 (PA_BCR+0x0004) /* Interrupt Priorty 1 */
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#define PA_IRLPRI2 (PA_BCR+0x0006) /* Interrupt Priorty 2 */
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#define PA_IRLPRI3 (PA_BCR+0x0008) /* Interrupt Priorty 3 */
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#define PA_IRLPRI4 (PA_BCR+0x000a) /* Interrupt Priorty 4 */
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#define PA_RSTCTL (PA_BCR+0x000c) /* Reset Control */
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#define PA_PCIBD (PA_BCR+0x000e) /* PCI Board detect control */
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2019-10-24 08:27:00 -07:00
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#define PA_PCICD (PA_BCR+0x0010) /* PCI Connector detect control */
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2006-10-19 01:31:22 -07:00
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#define PA_EXTGIO (PA_BCR+0x0016) /* Extension GPIO Control */
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#define PA_IVDRMON (PA_BCR+0x0018) /* iVDR Moniter control */
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#define PA_IVDRCTL (PA_BCR+0x001a) /* iVDR control */
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#define PA_OBLED (PA_BCR+0x001c) /* On Board LED control */
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#define PA_OBSW (PA_BCR+0x001e) /* On Board Switch control */
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#define PA_AUDIOSEL (PA_BCR+0x0020) /* Sound Interface Select control */
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2011-03-30 18:57:33 -07:00
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#define PA_EXTPLR (PA_BCR+0x001e) /* Extension Pin Polarity control */
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2006-10-19 01:31:22 -07:00
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#define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */
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#define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */
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#define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */
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#define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */
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#define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */
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#define PA_DBSW (PA_BCR+0x0200) /* Debug Board Switch control */
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#define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */
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#define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */
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#define PA_CFCDINTCLR (PA_BCR+0x0304) /* CF Insert Interrupt clear */
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#define PA_SCSMR0 (PA_BCR+0x0400) /* SCIF0 Serial mode control */
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#define PA_SCBRR0 (PA_BCR+0x0404) /* SCIF0 Bit rate control */
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#define PA_SCSCR0 (PA_BCR+0x0408) /* SCIF0 Serial control */
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#define PA_SCFTDR0 (PA_BCR+0x040c) /* SCIF0 Send FIFO control */
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#define PA_SCFSR0 (PA_BCR+0x0410) /* SCIF0 Serial status control */
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#define PA_SCFRDR0 (PA_BCR+0x0414) /* SCIF0 Receive FIFO control */
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#define PA_SCFCR0 (PA_BCR+0x0418) /* SCIF0 FIFO control */
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#define PA_SCTFDR0 (PA_BCR+0x041c) /* SCIF0 Send FIFO data control */
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#define PA_SCRFDR0 (PA_BCR+0x0420) /* SCIF0 Receive FIFO data control */
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#define PA_SCSPTR0 (PA_BCR+0x0424) /* SCIF0 Serial Port control */
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#define PA_SCLSR0 (PA_BCR+0x0428) /* SCIF0 Line Status control */
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#define PA_SCRER0 (PA_BCR+0x042c) /* SCIF0 Serial Error control */
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#define PA_SCSMR1 (PA_BCR+0x0500) /* SCIF1 Serial mode control */
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#define PA_SCBRR1 (PA_BCR+0x0504) /* SCIF1 Bit rate control */
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#define PA_SCSCR1 (PA_BCR+0x0508) /* SCIF1 Serial control */
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#define PA_SCFTDR1 (PA_BCR+0x050c) /* SCIF1 Send FIFO control */
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#define PA_SCFSR1 (PA_BCR+0x0510) /* SCIF1 Serial status control */
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#define PA_SCFRDR1 (PA_BCR+0x0514) /* SCIF1 Receive FIFO control */
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#define PA_SCFCR1 (PA_BCR+0x0518) /* SCIF1 FIFO control */
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#define PA_SCTFDR1 (PA_BCR+0x051c) /* SCIF1 Send FIFO data control */
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#define PA_SCRFDR1 (PA_BCR+0x0520) /* SCIF1 Receive FIFO data control */
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#define PA_SCSPTR1 (PA_BCR+0x0524) /* SCIF1 Serial Port control */
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#define PA_SCLSR1 (PA_BCR+0x0528) /* SCIF1 Line Status control */
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#define PA_SCRER1 (PA_BCR+0x052c) /* SCIF1 Serial Error control */
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2008-03-20 21:38:00 -07:00
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#define PA_SMCR (PA_BCR+0x0600) /* 2-wire Serial control */
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#define PA_SMSMADR (PA_BCR+0x0602) /* 2-wire Serial Slave control */
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#define PA_SMMR (PA_BCR+0x0604) /* 2-wire Serial Mode control */
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#define PA_SMSADR1 (PA_BCR+0x0606) /* 2-wire Serial Address1 control */
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#define PA_SMTRDR1 (PA_BCR+0x0646) /* 2-wire Serial Data1 control */
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2006-10-19 01:31:22 -07:00
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#define PA_VERREG (PA_BCR+0x0700) /* FPGA Version Register */
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#define PA_POFF (PA_BCR+0x0800) /* System Power Off control */
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#define PA_PMR (PA_BCR+0x0900) /* */
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#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
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2007-05-06 18:48:56 -07:00
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#define IVDR_CK_ON 8 /* iVDR Clock ON */
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2007-03-11 22:38:59 -07:00
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#elif defined(CONFIG_SH_R7780RP)
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2007-04-30 17:40:23 -07:00
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#define PA_POFF (-1)
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2006-10-19 01:31:22 -07:00
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#define PA_BCR 0xa5000000 /* FPGA */
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#define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
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#define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
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#define PA_SDPOW (PA_BCR+0x0004) /* SD Power control */
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#define PA_RSTCTL (PA_BCR+0x0006) /* Device Reset control */
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#define PA_PCIBD (PA_BCR+0x0008) /* PCI Board detect control */
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2019-10-24 08:27:00 -07:00
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#define PA_PCICD (PA_BCR+0x000a) /* PCI Connector detect control */
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2006-10-19 01:31:22 -07:00
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#define PA_ZIGIO1 (PA_BCR+0x000c) /* Zigbee IO control 1 */
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#define PA_ZIGIO2 (PA_BCR+0x000e) /* Zigbee IO control 2 */
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#define PA_ZIGIO3 (PA_BCR+0x0010) /* Zigbee IO control 3 */
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#define PA_ZIGIO4 (PA_BCR+0x0012) /* Zigbee IO control 4 */
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#define PA_IVDRMON (PA_BCR+0x0014) /* iVDR Moniter control */
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#define PA_IVDRCTL (PA_BCR+0x0016) /* iVDR control */
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#define PA_OBLED (PA_BCR+0x0018) /* On Board LED control */
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#define PA_OBSW (PA_BCR+0x001a) /* On Board Switch control */
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#define PA_AUDIOSEL (PA_BCR+0x001c) /* Sound Interface Select control */
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2011-03-30 18:57:33 -07:00
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#define PA_EXTPLR (PA_BCR+0x001e) /* Extension Pin Polarity control */
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2006-10-19 01:31:22 -07:00
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#define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */
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#define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */
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#define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */
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#define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */
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#define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */
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#define PA_DBDET (PA_BCR+0x0200) /* Debug Board detect control */
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#define PA_DBDISPCTL (PA_BCR+0x0202) /* Debug Board Dot timing control */
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#define PA_DBSW (PA_BCR+0x0204) /* Debug Board Switch control */
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#define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */
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#define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */
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#define PA_CFCDINTCLR (PA_BCR+0x0304) /* CF Insert Interrupt clear */
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#define PA_SCSMR (PA_BCR+0x0400) /* SCIF Serial mode control */
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#define PA_SCBRR (PA_BCR+0x0402) /* SCIF Bit rate control */
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#define PA_SCSCR (PA_BCR+0x0404) /* SCIF Serial control */
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#define PA_SCFDTR (PA_BCR+0x0406) /* SCIF Send FIFO control */
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#define PA_SCFSR (PA_BCR+0x0408) /* SCIF Serial status control */
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#define PA_SCFRDR (PA_BCR+0x040a) /* SCIF Receive FIFO control */
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#define PA_SCFCR (PA_BCR+0x040c) /* SCIF FIFO control */
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#define PA_SCFDR (PA_BCR+0x040e) /* SCIF FIFO data control */
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#define PA_SCLSR (PA_BCR+0x0412) /* SCIF Line Status control */
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2008-03-20 21:38:00 -07:00
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#define PA_SMCR (PA_BCR+0x0500) /* 2-wire Serial control */
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#define PA_SMSMADR (PA_BCR+0x0502) /* 2-wire Serial Slave control */
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#define PA_SMMR (PA_BCR+0x0504) /* 2-wire Serial Mode control */
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#define PA_SMSADR1 (PA_BCR+0x0506) /* 2-wire Serial Address1 control */
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#define PA_SMTRDR1 (PA_BCR+0x0546) /* 2-wire Serial Data1 control */
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2006-10-19 01:31:22 -07:00
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#define PA_VERREG (PA_BCR+0x0600) /* FPGA Version Register */
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#define PA_AX88796L 0xa5800400 /* AX88796L Area */
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#define PA_SC1602BSLB 0xa6000000 /* SC1602BSLB Area */
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#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
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#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
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#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
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2007-05-06 18:48:56 -07:00
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#define IVDR_CK_ON 8 /* iVDR Clock ON */
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2007-03-11 22:38:59 -07:00
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#elif defined(CONFIG_SH_R7785RP)
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#define PA_BCR 0xa4000000 /* FPGA */
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#define PA_SDPOW (-1)
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#define PA_PCISCR (PA_BCR+0x0000)
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#define PA_IRLPRA (PA_BCR+0x0002)
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#define PA_IRLPRB (PA_BCR+0x0004)
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#define PA_IRLPRC (PA_BCR+0x0006)
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#define PA_IRLPRD (PA_BCR+0x0008)
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#define IRLCNTR1 (PA_BCR+0x0010)
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#define PA_IRLPRE (PA_BCR+0x000a)
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#define PA_IRLPRF (PA_BCR+0x000c)
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#define PA_EXIRLCR (PA_BCR+0x000e)
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#define PA_IRLMCR1 (PA_BCR+0x0010)
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#define PA_IRLMCR2 (PA_BCR+0x0012)
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#define PA_IRLSSR1 (PA_BCR+0x0014)
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#define PA_IRLSSR2 (PA_BCR+0x0016)
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#define PA_CFTCR (PA_BCR+0x0100)
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#define PA_CFPCR (PA_BCR+0x0102)
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#define PA_PCICR (PA_BCR+0x0110)
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#define PA_IVDRCTL (PA_BCR+0x0112)
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#define PA_IVDRSR (PA_BCR+0x0114)
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#define PA_PDRSTCR (PA_BCR+0x0116)
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#define PA_POFF (PA_BCR+0x0120)
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#define PA_LCDCR (PA_BCR+0x0130)
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#define PA_TPCR (PA_BCR+0x0140)
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#define PA_TPCKCR (PA_BCR+0x0142)
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#define PA_TPRSTR (PA_BCR+0x0144)
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#define PA_TPXPDR (PA_BCR+0x0146)
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#define PA_TPYPDR (PA_BCR+0x0148)
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#define PA_GPIOPFR (PA_BCR+0x0150)
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#define PA_GPIODR (PA_BCR+0x0152)
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#define PA_OBLED (PA_BCR+0x0154)
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#define PA_SWSR (PA_BCR+0x0156)
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#define PA_VERREG (PA_BCR+0x0158)
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#define PA_SMCR (PA_BCR+0x0200)
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#define PA_SMSMADR (PA_BCR+0x0202)
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#define PA_SMMR (PA_BCR+0x0204)
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#define PA_SMSADR1 (PA_BCR+0x0206)
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#define PA_SMSADR32 (PA_BCR+0x0244)
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#define PA_SMTRDR1 (PA_BCR+0x0246)
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#define PA_SMTRDR16 (PA_BCR+0x0264)
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#define PA_CU3MDR (PA_BCR+0x0300)
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#define PA_CU5MDR (PA_BCR+0x0302)
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#define PA_MMSR (PA_BCR+0x0400)
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2007-05-06 18:48:56 -07:00
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#define IVDR_CK_ON 4 /* iVDR Clock ON */
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2007-09-09 20:06:03 -07:00
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#endif
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2007-05-06 18:48:56 -07:00
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2023-06-01 13:22:17 -07:00
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#define HL_FPGA_IRQ_BASE (200 + 16)
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2007-09-09 20:06:03 -07:00
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#define HL_NR_IRL 15
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#define IRQ_AX88796 (HL_FPGA_IRQ_BASE + 0)
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#define IRQ_CF (HL_FPGA_IRQ_BASE + 1)
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#define IRQ_PSW (HL_FPGA_IRQ_BASE + 2)
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2008-01-15 00:55:55 -07:00
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#define IRQ_EXT0 (HL_FPGA_IRQ_BASE + 3)
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#define IRQ_EXT1 (HL_FPGA_IRQ_BASE + 4)
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#define IRQ_EXT2 (HL_FPGA_IRQ_BASE + 5)
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#define IRQ_EXT3 (HL_FPGA_IRQ_BASE + 6)
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#define IRQ_EXT4 (HL_FPGA_IRQ_BASE + 7)
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#define IRQ_EXT5 (HL_FPGA_IRQ_BASE + 8)
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#define IRQ_EXT6 (HL_FPGA_IRQ_BASE + 9)
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#define IRQ_EXT7 (HL_FPGA_IRQ_BASE + 10)
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#define IRQ_SMBUS (HL_FPGA_IRQ_BASE + 11)
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#define IRQ_TP (HL_FPGA_IRQ_BASE + 12)
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#define IRQ_RTC (HL_FPGA_IRQ_BASE + 13)
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#define IRQ_TH_ALERT (HL_FPGA_IRQ_BASE + 14)
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2008-03-20 21:38:00 -07:00
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#define IRQ_SCIF0 (HL_FPGA_IRQ_BASE + 15)
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#define IRQ_SCIF1 (HL_FPGA_IRQ_BASE + 16)
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2007-03-11 22:38:59 -07:00
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2008-04-25 01:58:21 -07:00
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unsigned char *highlander_plat_irq_setup(void);
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2006-10-19 01:31:22 -07:00
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2008-10-22 20:35:43 -07:00
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#ifdef CONFIG_SH_R7785RP
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void highlander_plat_pinmux_setup(void);
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#else
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#define highlander_plat_pinmux_setup() do { } while (0)
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#endif
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2006-10-19 01:31:22 -07:00
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#endif /* __ASM_SH_RENESAS_R7780RP */
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