2019-06-04 01:11:33 -07:00
|
|
|
// SPDX-License-Identifier: GPL-2.0-only
|
2013-03-21 09:49:02 -07:00
|
|
|
/*
|
|
|
|
*
|
|
|
|
* Parts of this file are based on Ralink's 2.6.21 BSP
|
|
|
|
*
|
|
|
|
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
|
|
|
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
2016-05-05 00:57:56 -07:00
|
|
|
* Copyright (C) 2013 John Crispin <john@phrozen.org>
|
2013-03-21 09:49:02 -07:00
|
|
|
*/
|
|
|
|
|
|
|
|
#include <linux/kernel.h>
|
|
|
|
#include <linux/init.h>
|
2017-07-18 06:25:46 -07:00
|
|
|
#include <linux/bug.h>
|
2023-02-27 03:58:06 -07:00
|
|
|
#include <linux/slab.h>
|
|
|
|
#include <linux/sys_soc.h>
|
2013-03-21 09:49:02 -07:00
|
|
|
|
|
|
|
#include <asm/mipsregs.h>
|
|
|
|
#include <asm/mach-ralink/ralink_regs.h>
|
|
|
|
#include <asm/mach-ralink/mt7620.h>
|
|
|
|
|
|
|
|
#include "common.h"
|
|
|
|
|
2014-07-27 01:16:50 -07:00
|
|
|
/* analog */
|
|
|
|
#define PMU0_CFG 0x88
|
|
|
|
#define PMU_SW_SET BIT(28)
|
|
|
|
#define A_DCDC_EN BIT(24)
|
|
|
|
#define A_SSC_PERI BIT(19)
|
|
|
|
#define A_SSC_GEN BIT(18)
|
|
|
|
#define A_SSC_M 0x3
|
|
|
|
#define A_SSC_S 16
|
|
|
|
#define A_DLY_M 0x7
|
|
|
|
#define A_DLY_S 8
|
|
|
|
#define A_VTUNE_M 0xff
|
|
|
|
|
|
|
|
/* digital */
|
|
|
|
#define PMU1_CFG 0x8C
|
|
|
|
#define DIG_SW_SEL BIT(25)
|
|
|
|
|
2015-11-04 03:50:06 -07:00
|
|
|
/* EFUSE bits */
|
|
|
|
#define EFUSE_MT7688 0x100000
|
|
|
|
|
|
|
|
/* DRAM type bit */
|
|
|
|
#define DRAM_TYPE_MT7628_MASK 0x1
|
|
|
|
|
2013-03-21 09:49:02 -07:00
|
|
|
/* does the board have sdram or ddram */
|
|
|
|
static int dram_type;
|
|
|
|
|
2023-02-27 03:58:06 -07:00
|
|
|
static struct ralink_soc_info *soc_info_ptr;
|
|
|
|
|
2014-10-08 14:30:24 -07:00
|
|
|
static __init void
|
|
|
|
mt7620_dram_init(struct ralink_soc_info *soc_info)
|
|
|
|
{
|
|
|
|
switch (dram_type) {
|
|
|
|
case SYSCFG0_DRAM_TYPE_SDRAM:
|
|
|
|
pr_info("Board has SDRAM\n");
|
|
|
|
soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
|
|
|
|
soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SYSCFG0_DRAM_TYPE_DDR1:
|
|
|
|
pr_info("Board has DDR1\n");
|
|
|
|
soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
|
|
|
|
soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SYSCFG0_DRAM_TYPE_DDR2:
|
|
|
|
pr_info("Board has DDR2\n");
|
|
|
|
soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
|
|
|
|
soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static __init void
|
|
|
|
mt7628_dram_init(struct ralink_soc_info *soc_info)
|
|
|
|
{
|
|
|
|
switch (dram_type) {
|
|
|
|
case SYSCFG0_DRAM_TYPE_DDR1_MT7628:
|
|
|
|
pr_info("Board has DDR1\n");
|
|
|
|
soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
|
|
|
|
soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SYSCFG0_DRAM_TYPE_DDR2_MT7628:
|
|
|
|
pr_info("Board has DDR2\n");
|
|
|
|
soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
|
|
|
|
soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2023-02-27 03:58:05 -07:00
|
|
|
static unsigned int __init mt7620_get_soc_name0(void)
|
2013-03-21 09:49:02 -07:00
|
|
|
{
|
2023-02-27 03:58:05 -07:00
|
|
|
return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_NAME0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned int __init mt7620_get_soc_name1(void)
|
|
|
|
{
|
|
|
|
return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_NAME1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool __init mt7620_soc_valid(void)
|
|
|
|
{
|
|
|
|
if (mt7620_get_soc_name0() == MT7620_CHIP_NAME0 &&
|
|
|
|
mt7620_get_soc_name1() == MT7620_CHIP_NAME1)
|
|
|
|
return true;
|
|
|
|
else
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool __init mt7628_soc_valid(void)
|
|
|
|
{
|
|
|
|
if (mt7620_get_soc_name0() == MT7620_CHIP_NAME0 &&
|
|
|
|
mt7620_get_soc_name1() == MT7628_CHIP_NAME1)
|
|
|
|
return true;
|
|
|
|
else
|
|
|
|
return false;
|
|
|
|
}
|
2013-03-21 09:49:02 -07:00
|
|
|
|
2023-02-27 03:58:05 -07:00
|
|
|
static unsigned int __init mt7620_get_rev(void)
|
|
|
|
{
|
|
|
|
return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_REV);
|
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned int __init mt7620_get_bga(void)
|
|
|
|
{
|
|
|
|
return (mt7620_get_rev() >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned int __init mt7620_get_efuse(void)
|
|
|
|
{
|
|
|
|
return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_EFUSE_CFG);
|
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned int __init mt7620_get_soc_ver(void)
|
|
|
|
{
|
|
|
|
return (mt7620_get_rev() >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned int __init mt7620_get_soc_eco(void)
|
|
|
|
{
|
|
|
|
return (mt7620_get_rev() & CHIP_REV_ECO_MASK);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const char __init *mt7620_get_soc_name(struct ralink_soc_info *soc_info)
|
|
|
|
{
|
|
|
|
if (mt7620_soc_valid()) {
|
|
|
|
u32 bga = mt7620_get_bga();
|
2013-03-21 09:49:02 -07:00
|
|
|
|
2014-10-08 14:30:24 -07:00
|
|
|
if (bga) {
|
2015-11-04 03:50:07 -07:00
|
|
|
ralink_soc = MT762X_SOC_MT7620A;
|
2014-10-08 14:30:24 -07:00
|
|
|
soc_info->compatible = "ralink,mt7620a-soc";
|
2023-02-27 03:58:05 -07:00
|
|
|
return "MT7620A";
|
2014-10-08 14:30:24 -07:00
|
|
|
} else {
|
2015-11-04 03:50:07 -07:00
|
|
|
ralink_soc = MT762X_SOC_MT7620N;
|
2014-10-08 14:30:24 -07:00
|
|
|
soc_info->compatible = "ralink,mt7620n-soc";
|
2023-02-27 03:58:05 -07:00
|
|
|
return "MT7620N";
|
2014-10-08 14:30:24 -07:00
|
|
|
}
|
2023-02-27 03:58:05 -07:00
|
|
|
} else if (mt7628_soc_valid()) {
|
|
|
|
u32 efuse = mt7620_get_efuse();
|
|
|
|
unsigned char *name = NULL;
|
2015-11-04 03:50:06 -07:00
|
|
|
|
|
|
|
if (efuse & EFUSE_MT7688) {
|
2015-11-04 03:50:07 -07:00
|
|
|
ralink_soc = MT762X_SOC_MT7688;
|
2015-11-04 03:50:06 -07:00
|
|
|
name = "MT7688";
|
|
|
|
} else {
|
2015-11-04 03:50:07 -07:00
|
|
|
ralink_soc = MT762X_SOC_MT7628AN;
|
2015-11-04 03:50:06 -07:00
|
|
|
name = "MT7628AN";
|
|
|
|
}
|
2014-10-08 14:30:24 -07:00
|
|
|
soc_info->compatible = "ralink,mt7628an-soc";
|
2023-02-27 03:58:05 -07:00
|
|
|
return name;
|
2014-10-08 14:30:24 -07:00
|
|
|
} else {
|
2023-02-27 03:58:05 -07:00
|
|
|
panic("mt762x: unknown SoC, n0:%08x n1:%08x\n",
|
|
|
|
mt7620_get_soc_name0(), mt7620_get_soc_name1());
|
2013-03-21 09:49:02 -07:00
|
|
|
}
|
2023-02-27 03:58:05 -07:00
|
|
|
}
|
|
|
|
|
2023-02-27 03:58:06 -07:00
|
|
|
static const char __init *mt7620_get_soc_id_name(void)
|
|
|
|
{
|
|
|
|
if (ralink_soc == MT762X_SOC_MT7620A)
|
|
|
|
return "mt7620a";
|
|
|
|
else if (ralink_soc == MT762X_SOC_MT7620N)
|
|
|
|
return "mt7620n";
|
|
|
|
else if (ralink_soc == MT762X_SOC_MT7688)
|
|
|
|
return "mt7688";
|
|
|
|
else if (ralink_soc == MT762X_SOC_MT7628AN)
|
|
|
|
return "mt7628n";
|
|
|
|
else
|
|
|
|
return "invalid";
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __init mt7620_soc_dev_init(void)
|
|
|
|
{
|
|
|
|
struct soc_device *soc_dev;
|
|
|
|
struct soc_device_attribute *soc_dev_attr;
|
|
|
|
|
|
|
|
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
|
|
|
|
if (!soc_dev_attr)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
soc_dev_attr->family = "Ralink";
|
|
|
|
soc_dev_attr->soc_id = mt7620_get_soc_id_name();
|
|
|
|
|
|
|
|
soc_dev_attr->data = soc_info_ptr;
|
|
|
|
|
|
|
|
soc_dev = soc_device_register(soc_dev_attr);
|
|
|
|
if (IS_ERR(soc_dev)) {
|
|
|
|
kfree(soc_dev_attr);
|
|
|
|
return PTR_ERR(soc_dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
device_initcall(mt7620_soc_dev_init);
|
|
|
|
|
2023-02-27 03:58:05 -07:00
|
|
|
void __init prom_soc_init(struct ralink_soc_info *soc_info)
|
|
|
|
{
|
|
|
|
const char *name = mt7620_get_soc_name(soc_info);
|
|
|
|
u32 cfg0;
|
|
|
|
u32 pmu0;
|
|
|
|
u32 pmu1;
|
2013-03-21 09:49:02 -07:00
|
|
|
|
|
|
|
snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
|
2016-01-04 12:23:59 -07:00
|
|
|
"MediaTek %s ver:%u eco:%u",
|
2023-02-27 03:58:05 -07:00
|
|
|
name, mt7620_get_soc_ver(), mt7620_get_soc_eco());
|
2013-03-21 09:49:02 -07:00
|
|
|
|
2023-02-27 03:58:04 -07:00
|
|
|
cfg0 = __raw_readl(MT7620_SYSC_BASE + SYSC_REG_SYSTEM_CONFIG0);
|
2016-04-19 20:44:45 -07:00
|
|
|
if (is_mt76x8()) {
|
2015-11-04 03:50:06 -07:00
|
|
|
dram_type = cfg0 & DRAM_TYPE_MT7628_MASK;
|
2016-04-19 20:44:45 -07:00
|
|
|
} else {
|
2015-11-04 03:50:06 -07:00
|
|
|
dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) &
|
|
|
|
SYSCFG0_DRAM_TYPE_MASK;
|
2016-04-19 20:44:45 -07:00
|
|
|
if (dram_type == SYSCFG0_DRAM_TYPE_UNKNOWN)
|
|
|
|
dram_type = SYSCFG0_DRAM_TYPE_SDRAM;
|
|
|
|
}
|
2013-04-14 00:55:29 -07:00
|
|
|
|
|
|
|
soc_info->mem_base = MT7620_DRAM_BASE;
|
2015-11-04 03:50:06 -07:00
|
|
|
if (is_mt76x8())
|
2014-10-08 14:30:24 -07:00
|
|
|
mt7628_dram_init(soc_info);
|
|
|
|
else
|
|
|
|
mt7620_dram_init(soc_info);
|
2014-07-27 01:16:50 -07:00
|
|
|
|
2023-02-27 03:58:04 -07:00
|
|
|
pmu0 = __raw_readl(MT7620_SYSC_BASE + PMU0_CFG);
|
|
|
|
pmu1 = __raw_readl(MT7620_SYSC_BASE + PMU1_CFG);
|
2014-07-27 01:16:50 -07:00
|
|
|
|
|
|
|
pr_info("Analog PMU set to %s control\n",
|
|
|
|
(pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
|
|
|
|
pr_info("Digital PMU set to %s control\n",
|
|
|
|
(pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
|
2023-02-27 03:58:06 -07:00
|
|
|
|
|
|
|
soc_info_ptr = soc_info;
|
2013-03-21 09:49:02 -07:00
|
|
|
}
|