2019-06-04 01:11:33 -07:00
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// SPDX-License-Identifier: GPL-2.0-only
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2010-01-26 20:12:54 -07:00
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/*
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* OMAP4 Clock domains framework
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*
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2011-07-09 18:15:06 -07:00
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* Copyright (C) 2009-2011 Texas Instruments, Inc.
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* Copyright (C) 2009-2011 Nokia Corporation
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2010-01-26 20:12:54 -07:00
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*
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* Abhijit Pagare (abhijitpagare@ti.com)
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* Benoit Cousson (b-cousson@ti.com)
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2011-07-09 18:15:06 -07:00
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* Paul Walmsley (paul@pwsan.com)
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2010-01-26 20:12:54 -07:00
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*
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* This file is automatically generated from the OMAP hardware databases.
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* We respectfully ask that any modifications to this file be coordinated
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* with the public linux-omap@vger.kernel.org mailing list and the
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* authors above to ensure that the autogeneration scripts are kept
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* up-to-date with the file contents.
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*/
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2010-12-21 20:01:20 -07:00
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#include <linux/kernel.h>
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#include <linux/io.h>
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2010-01-26 20:12:54 -07:00
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2010-12-21 21:05:15 -07:00
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#include "clockdomain.h"
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2010-12-21 15:30:55 -07:00
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#include "cm1_44xx.h"
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#include "cm2_44xx.h"
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2010-01-26 20:12:54 -07:00
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2010-12-21 20:01:20 -07:00
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#include "cm-regbits-44xx.h"
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2010-12-21 15:30:54 -07:00
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#include "prm44xx.h"
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2010-12-21 21:05:15 -07:00
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#include "prcm44xx.h"
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2010-12-21 15:30:54 -07:00
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#include "prcm_mpu44xx.h"
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2011-02-25 15:48:13 -07:00
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/* Static Dependencies for OMAP4 Clock Domains */
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2011-07-09 18:15:06 -07:00
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static struct clkdm_dep d2d_wkup_sleep_deps[] = {
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2011-09-14 15:01:21 -07:00
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{ .clkdm_name = "abe_clkdm" },
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{ .clkdm_name = "ivahd_clkdm" },
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{ .clkdm_name = "l3_1_clkdm" },
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{ .clkdm_name = "l3_2_clkdm" },
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{ .clkdm_name = "l3_emif_clkdm" },
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{ .clkdm_name = "l3_init_clkdm" },
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{ .clkdm_name = "l4_cfg_clkdm" },
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{ .clkdm_name = "l4_per_clkdm" },
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2011-07-09 18:15:06 -07:00
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{ NULL },
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};
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static struct clkdm_dep ducati_wkup_sleep_deps[] = {
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2011-09-14 15:01:21 -07:00
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{ .clkdm_name = "abe_clkdm" },
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{ .clkdm_name = "ivahd_clkdm" },
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{ .clkdm_name = "l3_1_clkdm" },
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{ .clkdm_name = "l3_2_clkdm" },
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{ .clkdm_name = "l3_dss_clkdm" },
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{ .clkdm_name = "l3_emif_clkdm" },
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{ .clkdm_name = "l3_gfx_clkdm" },
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{ .clkdm_name = "l3_init_clkdm" },
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{ .clkdm_name = "l4_cfg_clkdm" },
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{ .clkdm_name = "l4_per_clkdm" },
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{ .clkdm_name = "l4_secure_clkdm" },
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{ .clkdm_name = "l4_wkup_clkdm" },
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{ .clkdm_name = "tesla_clkdm" },
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2011-07-09 18:15:06 -07:00
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{ NULL },
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};
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static struct clkdm_dep iss_wkup_sleep_deps[] = {
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2011-09-14 15:01:21 -07:00
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{ .clkdm_name = "ivahd_clkdm" },
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{ .clkdm_name = "l3_1_clkdm" },
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{ .clkdm_name = "l3_emif_clkdm" },
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2011-07-09 18:15:06 -07:00
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{ NULL },
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};
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static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
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2011-09-14 15:01:21 -07:00
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{ .clkdm_name = "l3_1_clkdm" },
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{ .clkdm_name = "l3_emif_clkdm" },
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2011-02-25 15:48:13 -07:00
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{ NULL },
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};
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static struct clkdm_dep l3_dma_wkup_sleep_deps[] = {
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2011-09-14 15:01:21 -07:00
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{ .clkdm_name = "abe_clkdm" },
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{ .clkdm_name = "ducati_clkdm" },
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{ .clkdm_name = "ivahd_clkdm" },
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{ .clkdm_name = "l3_1_clkdm" },
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{ .clkdm_name = "l3_dss_clkdm" },
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{ .clkdm_name = "l3_emif_clkdm" },
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{ .clkdm_name = "l3_init_clkdm" },
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{ .clkdm_name = "l4_cfg_clkdm" },
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{ .clkdm_name = "l4_per_clkdm" },
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{ .clkdm_name = "l4_secure_clkdm" },
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{ .clkdm_name = "l4_wkup_clkdm" },
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2011-02-25 15:48:13 -07:00
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{ NULL },
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};
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static struct clkdm_dep l3_dss_wkup_sleep_deps[] = {
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2011-09-14 15:01:21 -07:00
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{ .clkdm_name = "ivahd_clkdm" },
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{ .clkdm_name = "l3_2_clkdm" },
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{ .clkdm_name = "l3_emif_clkdm" },
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2011-02-25 15:48:13 -07:00
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{ NULL },
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};
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static struct clkdm_dep l3_gfx_wkup_sleep_deps[] = {
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2011-09-14 15:01:21 -07:00
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{ .clkdm_name = "ivahd_clkdm" },
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{ .clkdm_name = "l3_1_clkdm" },
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{ .clkdm_name = "l3_emif_clkdm" },
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2011-02-25 15:48:13 -07:00
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{ NULL },
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};
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static struct clkdm_dep l3_init_wkup_sleep_deps[] = {
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2011-09-14 15:01:21 -07:00
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{ .clkdm_name = "abe_clkdm" },
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{ .clkdm_name = "ivahd_clkdm" },
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{ .clkdm_name = "l3_emif_clkdm" },
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{ .clkdm_name = "l4_cfg_clkdm" },
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{ .clkdm_name = "l4_per_clkdm" },
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{ .clkdm_name = "l4_secure_clkdm" },
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{ .clkdm_name = "l4_wkup_clkdm" },
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2011-02-25 15:48:13 -07:00
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{ NULL },
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};
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static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
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2011-09-14 15:01:21 -07:00
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{ .clkdm_name = "l3_1_clkdm" },
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{ .clkdm_name = "l3_emif_clkdm" },
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{ .clkdm_name = "l4_per_clkdm" },
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2011-02-25 15:48:13 -07:00
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{ NULL },
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};
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2011-07-09 18:15:06 -07:00
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static struct clkdm_dep mpu_wkup_sleep_deps[] = {
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2011-09-14 15:01:21 -07:00
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{ .clkdm_name = "abe_clkdm" },
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{ .clkdm_name = "ducati_clkdm" },
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{ .clkdm_name = "ivahd_clkdm" },
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{ .clkdm_name = "l3_1_clkdm" },
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{ .clkdm_name = "l3_2_clkdm" },
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{ .clkdm_name = "l3_dss_clkdm" },
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{ .clkdm_name = "l3_emif_clkdm" },
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{ .clkdm_name = "l3_gfx_clkdm" },
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{ .clkdm_name = "l3_init_clkdm" },
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{ .clkdm_name = "l4_cfg_clkdm" },
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{ .clkdm_name = "l4_per_clkdm" },
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{ .clkdm_name = "l4_secure_clkdm" },
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{ .clkdm_name = "l4_wkup_clkdm" },
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{ .clkdm_name = "tesla_clkdm" },
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2011-02-25 15:48:13 -07:00
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{ NULL },
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};
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static struct clkdm_dep tesla_wkup_sleep_deps[] = {
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2011-09-14 15:01:21 -07:00
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{ .clkdm_name = "abe_clkdm" },
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{ .clkdm_name = "ivahd_clkdm" },
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{ .clkdm_name = "l3_1_clkdm" },
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{ .clkdm_name = "l3_2_clkdm" },
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{ .clkdm_name = "l3_emif_clkdm" },
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{ .clkdm_name = "l3_init_clkdm" },
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{ .clkdm_name = "l4_cfg_clkdm" },
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{ .clkdm_name = "l4_per_clkdm" },
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{ .clkdm_name = "l4_wkup_clkdm" },
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2011-02-25 15:48:13 -07:00
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{ NULL },
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};
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2010-01-26 20:12:54 -07:00
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static struct clockdomain l4_cefuse_44xx_clkdm = {
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.name = "l4_cefuse_clkdm",
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.pwrdm = { .name = "cefuse_pwrdm" },
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2010-12-21 21:05:15 -07:00
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_CEFUSE_INST,
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.clkdm_offs = OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS,
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2010-01-26 20:12:54 -07:00
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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};
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static struct clockdomain l4_cfg_44xx_clkdm = {
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.name = "l4_cfg_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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2010-12-21 21:05:15 -07:00
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_CORE_INST,
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.clkdm_offs = OMAP4430_CM2_CORE_L4CFG_CDOFFS,
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2011-02-25 15:48:13 -07:00
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.dep_bit = OMAP4430_L4CFG_STATDEP_SHIFT,
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.flags = CLKDM_CAN_HWSUP,
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};
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static struct clockdomain tesla_44xx_clkdm = {
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.name = "tesla_clkdm",
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.pwrdm = { .name = "tesla_pwrdm" },
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2010-12-21 21:05:15 -07:00
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.prcm_partition = OMAP4430_CM1_PARTITION,
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.cm_inst = OMAP4430_CM1_TESLA_INST,
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.clkdm_offs = OMAP4430_CM1_TESLA_TESLA_CDOFFS,
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2011-02-25 15:48:13 -07:00
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.dep_bit = OMAP4430_TESLA_STATDEP_SHIFT,
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.wkdep_srcs = tesla_wkup_sleep_deps,
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.sleepdep_srcs = tesla_wkup_sleep_deps,
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2010-01-26 20:12:54 -07:00
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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};
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static struct clockdomain l3_gfx_44xx_clkdm = {
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.name = "l3_gfx_clkdm",
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.pwrdm = { .name = "gfx_pwrdm" },
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2010-12-21 21:05:15 -07:00
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_GFX_INST,
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.clkdm_offs = OMAP4430_CM2_GFX_GFX_CDOFFS,
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2011-02-25 15:48:13 -07:00
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.dep_bit = OMAP4430_GFX_STATDEP_SHIFT,
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.wkdep_srcs = l3_gfx_wkup_sleep_deps,
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.sleepdep_srcs = l3_gfx_wkup_sleep_deps,
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2010-01-26 20:12:54 -07:00
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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};
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static struct clockdomain ivahd_44xx_clkdm = {
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.name = "ivahd_clkdm",
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.pwrdm = { .name = "ivahd_pwrdm" },
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2010-12-21 21:05:15 -07:00
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_IVAHD_INST,
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.clkdm_offs = OMAP4430_CM2_IVAHD_IVAHD_CDOFFS,
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2011-02-25 15:48:13 -07:00
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.dep_bit = OMAP4430_IVAHD_STATDEP_SHIFT,
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.wkdep_srcs = ivahd_wkup_sleep_deps,
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.sleepdep_srcs = ivahd_wkup_sleep_deps,
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2010-01-26 20:12:54 -07:00
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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};
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static struct clockdomain l4_secure_44xx_clkdm = {
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.name = "l4_secure_clkdm",
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.pwrdm = { .name = "l4per_pwrdm" },
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2010-12-21 21:05:15 -07:00
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_L4PER_INST,
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.clkdm_offs = OMAP4430_CM2_L4PER_L4SEC_CDOFFS,
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2011-02-25 15:48:13 -07:00
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.dep_bit = OMAP4430_L4SEC_STATDEP_SHIFT,
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.wkdep_srcs = l4_secure_wkup_sleep_deps,
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.sleepdep_srcs = l4_secure_wkup_sleep_deps,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain l4_per_44xx_clkdm = {
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.name = "l4_per_clkdm",
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.pwrdm = { .name = "l4per_pwrdm" },
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2010-12-21 21:05:15 -07:00
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_L4PER_INST,
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.clkdm_offs = OMAP4430_CM2_L4PER_L4PER_CDOFFS,
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.dep_bit = OMAP4430_L4PER_STATDEP_SHIFT,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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};
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static struct clockdomain abe_44xx_clkdm = {
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.name = "abe_clkdm",
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.pwrdm = { .name = "abe_pwrdm" },
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2010-12-21 21:05:15 -07:00
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.prcm_partition = OMAP4430_CM1_PARTITION,
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.cm_inst = OMAP4430_CM1_ABE_INST,
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.clkdm_offs = OMAP4430_CM1_ABE_ABE_CDOFFS,
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.dep_bit = OMAP4430_ABE_STATDEP_SHIFT,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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};
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2010-01-26 20:12:58 -07:00
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static struct clockdomain l3_instr_44xx_clkdm = {
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.name = "l3_instr_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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2010-12-21 21:05:15 -07:00
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_CORE_INST,
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.clkdm_offs = OMAP4430_CM2_CORE_L3INSTR_CDOFFS,
|
2010-01-26 20:12:58 -07:00
|
|
|
};
|
|
|
|
|
|
2010-01-26 20:12:54 -07:00
|
|
|
static struct clockdomain l3_init_44xx_clkdm = {
|
|
|
|
|
.name = "l3_init_clkdm",
|
|
|
|
|
.pwrdm = { .name = "l3init_pwrdm" },
|
2010-12-21 21:05:15 -07:00
|
|
|
.prcm_partition = OMAP4430_CM2_PARTITION,
|
|
|
|
|
.cm_inst = OMAP4430_CM2_L3INIT_INST,
|
|
|
|
|
.clkdm_offs = OMAP4430_CM2_L3INIT_L3INIT_CDOFFS,
|
2011-02-25 15:48:13 -07:00
|
|
|
.dep_bit = OMAP4430_L3INIT_STATDEP_SHIFT,
|
|
|
|
|
.wkdep_srcs = l3_init_wkup_sleep_deps,
|
|
|
|
|
.sleepdep_srcs = l3_init_wkup_sleep_deps,
|
2010-01-26 20:12:54 -07:00
|
|
|
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
|
|
|
|
};
|
|
|
|
|
|
2011-07-09 18:15:06 -07:00
|
|
|
static struct clockdomain d2d_44xx_clkdm = {
|
|
|
|
|
.name = "d2d_clkdm",
|
|
|
|
|
.pwrdm = { .name = "core_pwrdm" },
|
|
|
|
|
.prcm_partition = OMAP4430_CM2_PARTITION,
|
|
|
|
|
.cm_inst = OMAP4430_CM2_CORE_INST,
|
|
|
|
|
.clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS,
|
|
|
|
|
.wkdep_srcs = d2d_wkup_sleep_deps,
|
|
|
|
|
.sleepdep_srcs = d2d_wkup_sleep_deps,
|
2010-01-26 20:12:54 -07:00
|
|
|
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct clockdomain mpu0_44xx_clkdm = {
|
|
|
|
|
.name = "mpu0_clkdm",
|
|
|
|
|
.pwrdm = { .name = "cpu0_pwrdm" },
|
2010-12-21 21:05:15 -07:00
|
|
|
.prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
|
|
|
|
|
.cm_inst = OMAP4430_PRCM_MPU_CPU0_INST,
|
2011-02-08 14:30:31 -07:00
|
|
|
.clkdm_offs = OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS,
|
2010-01-26 20:12:54 -07:00
|
|
|
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct clockdomain mpu1_44xx_clkdm = {
|
|
|
|
|
.name = "mpu1_clkdm",
|
|
|
|
|
.pwrdm = { .name = "cpu1_pwrdm" },
|
2010-12-21 21:05:15 -07:00
|
|
|
.prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
|
|
|
|
|
.cm_inst = OMAP4430_PRCM_MPU_CPU1_INST,
|
2011-02-08 14:30:31 -07:00
|
|
|
.clkdm_offs = OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS,
|
2010-01-26 20:12:54 -07:00
|
|
|
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct clockdomain l3_emif_44xx_clkdm = {
|
|
|
|
|
.name = "l3_emif_clkdm",
|
|
|
|
|
.pwrdm = { .name = "core_pwrdm" },
|
2010-12-21 21:05:15 -07:00
|
|
|
.prcm_partition = OMAP4430_CM2_PARTITION,
|
|
|
|
|
.cm_inst = OMAP4430_CM2_CORE_INST,
|
|
|
|
|
.clkdm_offs = OMAP4430_CM2_CORE_MEMIF_CDOFFS,
|
2011-02-25 15:48:13 -07:00
|
|
|
.dep_bit = OMAP4430_MEMIF_STATDEP_SHIFT,
|
2010-01-26 20:12:54 -07:00
|
|
|
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct clockdomain l4_ao_44xx_clkdm = {
|
|
|
|
|
.name = "l4_ao_clkdm",
|
|
|
|
|
.pwrdm = { .name = "always_on_core_pwrdm" },
|
2010-12-21 21:05:15 -07:00
|
|
|
.prcm_partition = OMAP4430_CM2_PARTITION,
|
|
|
|
|
.cm_inst = OMAP4430_CM2_ALWAYS_ON_INST,
|
|
|
|
|
.clkdm_offs = OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS,
|
2010-01-26 20:12:54 -07:00
|
|
|
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct clockdomain ducati_44xx_clkdm = {
|
|
|
|
|
.name = "ducati_clkdm",
|
|
|
|
|
.pwrdm = { .name = "core_pwrdm" },
|
2010-12-21 21:05:15 -07:00
|
|
|
.prcm_partition = OMAP4430_CM2_PARTITION,
|
|
|
|
|
.cm_inst = OMAP4430_CM2_CORE_INST,
|
|
|
|
|
.clkdm_offs = OMAP4430_CM2_CORE_DUCATI_CDOFFS,
|
2011-02-25 15:48:13 -07:00
|
|
|
.dep_bit = OMAP4430_DUCATI_STATDEP_SHIFT,
|
|
|
|
|
.wkdep_srcs = ducati_wkup_sleep_deps,
|
|
|
|
|
.sleepdep_srcs = ducati_wkup_sleep_deps,
|
2010-01-26 20:12:54 -07:00
|
|
|
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
|
|
|
|
};
|
|
|
|
|
|
2011-07-09 18:15:06 -07:00
|
|
|
static struct clockdomain mpu_44xx_clkdm = {
|
2011-07-10 04:56:29 -07:00
|
|
|
.name = "mpuss_clkdm",
|
2011-07-09 18:15:06 -07:00
|
|
|
.pwrdm = { .name = "mpu_pwrdm" },
|
|
|
|
|
.prcm_partition = OMAP4430_CM1_PARTITION,
|
|
|
|
|
.cm_inst = OMAP4430_CM1_MPU_INST,
|
|
|
|
|
.clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS,
|
|
|
|
|
.wkdep_srcs = mpu_wkup_sleep_deps,
|
|
|
|
|
.sleepdep_srcs = mpu_wkup_sleep_deps,
|
|
|
|
|
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
|
|
|
|
|
};
|
|
|
|
|
|
2010-01-26 20:12:54 -07:00
|
|
|
static struct clockdomain l3_2_44xx_clkdm = {
|
|
|
|
|
.name = "l3_2_clkdm",
|
|
|
|
|
.pwrdm = { .name = "core_pwrdm" },
|
2010-12-21 21:05:15 -07:00
|
|
|
.prcm_partition = OMAP4430_CM2_PARTITION,
|
|
|
|
|
.cm_inst = OMAP4430_CM2_CORE_INST,
|
|
|
|
|
.clkdm_offs = OMAP4430_CM2_CORE_L3_2_CDOFFS,
|
2011-02-25 15:48:13 -07:00
|
|
|
.dep_bit = OMAP4430_L3_2_STATDEP_SHIFT,
|
2010-01-26 20:12:54 -07:00
|
|
|
.flags = CLKDM_CAN_HWSUP,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct clockdomain l3_1_44xx_clkdm = {
|
|
|
|
|
.name = "l3_1_clkdm",
|
|
|
|
|
.pwrdm = { .name = "core_pwrdm" },
|
2010-12-21 21:05:15 -07:00
|
|
|
.prcm_partition = OMAP4430_CM2_PARTITION,
|
|
|
|
|
.cm_inst = OMAP4430_CM2_CORE_INST,
|
|
|
|
|
.clkdm_offs = OMAP4430_CM2_CORE_L3_1_CDOFFS,
|
2011-02-25 15:48:13 -07:00
|
|
|
.dep_bit = OMAP4430_L3_1_STATDEP_SHIFT,
|
2010-01-26 20:12:54 -07:00
|
|
|
.flags = CLKDM_CAN_HWSUP,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct clockdomain iss_44xx_clkdm = {
|
|
|
|
|
.name = "iss_clkdm",
|
|
|
|
|
.pwrdm = { .name = "cam_pwrdm" },
|
2010-12-21 21:05:15 -07:00
|
|
|
.prcm_partition = OMAP4430_CM2_PARTITION,
|
|
|
|
|
.cm_inst = OMAP4430_CM2_CAM_INST,
|
|
|
|
|
.clkdm_offs = OMAP4430_CM2_CAM_CAM_CDOFFS,
|
2011-02-25 15:48:13 -07:00
|
|
|
.wkdep_srcs = iss_wkup_sleep_deps,
|
|
|
|
|
.sleepdep_srcs = iss_wkup_sleep_deps,
|
2012-10-29 21:02:13 -07:00
|
|
|
.flags = CLKDM_CAN_SWSUP,
|
2010-01-26 20:12:54 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct clockdomain l3_dss_44xx_clkdm = {
|
|
|
|
|
.name = "l3_dss_clkdm",
|
|
|
|
|
.pwrdm = { .name = "dss_pwrdm" },
|
2010-12-21 21:05:15 -07:00
|
|
|
.prcm_partition = OMAP4430_CM2_PARTITION,
|
|
|
|
|
.cm_inst = OMAP4430_CM2_DSS_INST,
|
|
|
|
|
.clkdm_offs = OMAP4430_CM2_DSS_DSS_CDOFFS,
|
2011-02-25 15:48:13 -07:00
|
|
|
.dep_bit = OMAP4430_DSS_STATDEP_SHIFT,
|
|
|
|
|
.wkdep_srcs = l3_dss_wkup_sleep_deps,
|
|
|
|
|
.sleepdep_srcs = l3_dss_wkup_sleep_deps,
|
2010-01-26 20:12:54 -07:00
|
|
|
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct clockdomain l4_wkup_44xx_clkdm = {
|
|
|
|
|
.name = "l4_wkup_clkdm",
|
|
|
|
|
.pwrdm = { .name = "wkup_pwrdm" },
|
2010-12-21 21:05:15 -07:00
|
|
|
.prcm_partition = OMAP4430_PRM_PARTITION,
|
|
|
|
|
.cm_inst = OMAP4430_PRM_WKUP_CM_INST,
|
|
|
|
|
.clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS,
|
2011-02-25 15:48:13 -07:00
|
|
|
.dep_bit = OMAP4430_L4WKUP_STATDEP_SHIFT,
|
ARM: OMAP2+: hwmod code/clockdomain data: fix 32K sync timer
Kevin discovered that commit c8d82ff68fb6873691536cf33021977efbf5593c
("ARM: OMAP2/3: hwmod data: Add 32k-sync timer data to hwmod
database") broke CORE idle on OMAP3. This prevents device low power
states.
The root cause is that the 32K sync timer IP block does not support
smart-idle mode[1], and so the hwmod code keeps the IP block in
no-idle mode while it is active. This in turn prevents the WKUP
clockdomain from transitioning to idle. There is a hardcoded sleep
dependency that prevents the CORE_L3 and CORE_CM clockdomains from
transitioning to idle when the WKUP clockdomain is active[2], so the
chip cannot enter any device low power states.
It turns out that there is no need to take the 32k sync timer out of
idle. The IP block itself probably does not have any native idle
handling at all, due to its simplicity. Furthermore, the PRCM will
never request target idle for this IP block while the kernel is
running, due to the sleep dependency that prevents the WKUP
clockdomain from idling while the CORE_L3 clockdomain is active. So
we can safely leave the 32k sync timer in target-force-idle mode, even
while we continue to access it.
This workaround is implemented by defining a new clockdomain flag,
CLKDM_ACTIVE_WITH_MPU, that indicates that the clockdomain is
guaranteed to be active whenever the MPU is inactive. If an IP
block's main functional clock exists inside this clockdomain, and the
IP block does not support smart-idle modes, then the hwmod code will
place the IP block into target force-idle mode even when enabled. The
WKUP clockdomains on OMAP3/4 are marked with this flag. (On OMAP2xxx,
no OCP header existed on the 32k sync timer.) Other clockdomains also
should be marked with this flag, but those changes are deferred until
a later merge window, to create a minimal fix.
Another theoretically clean fix for this problem would be to implement
PM runtime-based control for 32k sync timer accesses. These PM
runtime calls would need to located in a custom clocksource, since the
32k sync timer is currently used as an MMIO clocksource. But in
practice, there would be little benefit to doing so; and there would
be some cost, due to the addition of unnecessary lines of code and the
additional CPU overhead of the PM runtime and hwmod code - unnecessary
in this case.
Another possible fix would have been to modify the pm34xx.c code to
force the IP block idle before entering WFI. But this would not have
been an acceptable approach: we are trying to remove this type of
centralized IP block idle control from the PM code.
This patch is a collaboration between Kevin Hilman <khilman@ti.com>
and Paul Walmsley <paul@pwsan.com>.
Thanks to Vaibhav Hiremath <hvaibhav@ti.com> for providing comments on
an earlier version of this patch. Thanks to Tero Kristo
<t-kristo@ti.com> for identifying a bug in an earlier version of this
patch. Thanks to Benoît Cousson <b-cousson@ti.com> for identifying
some bugs in several versions of this patch and for implementation
comments.
References:
1. Table 16-96 "REG_32KSYNCNT_SYSCONFIG" of the OMAP34xx TRM Rev. ZU
(SWPU223U), available from:
http://www.ti.com/pdfs/wtbu/OMAP34x_ES3.1.x_PUBLIC_TRM_vzU.zip
2. Table 4-72 "Sleep Dependencies" of the OMAP34xx TRM Rev. ZU
(SWPU223U)
3. ibid.
Cc: Tony Lindgren <tony@atomide.com>
Cc: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Tested-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-07-04 04:22:53 -07:00
|
|
|
.flags = CLKDM_CAN_HWSUP | CLKDM_ACTIVE_WITH_MPU,
|
2010-01-26 20:12:54 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct clockdomain emu_sys_44xx_clkdm = {
|
|
|
|
|
.name = "emu_sys_clkdm",
|
|
|
|
|
.pwrdm = { .name = "emu_pwrdm" },
|
2010-12-21 21:05:15 -07:00
|
|
|
.prcm_partition = OMAP4430_PRM_PARTITION,
|
|
|
|
|
.cm_inst = OMAP4430_PRM_EMU_CM_INST,
|
|
|
|
|
.clkdm_offs = OMAP4430_PRM_EMU_CM_EMU_CDOFFS,
|
ARM: OMAP2+: clockdomain/hwmod: add workaround for EMU clockdomain idle problems
The idle status of the IP blocks and clocks inside the EMU clockdomain
isn't taken into account by the PRCM hardware when deciding whether
the clockdomain is idle. Add a workaround flag in the clockdomain
code, CLKDM_MISSING_IDLE_REPORTING, to deal with this problem, and add
the code necessary to support it.
If CLKDM_MISSING_IDLE_REPORTING is set on a clockdomain, the
clockdomain will be forced active whenever an IP block inside that
clockdomain is in use, even if the clockdomain supports
hardware-supervised idle. When the kernel indicates that the last
active IP block inside the clockdomain is no longer used, the
clockdomain will be forced idle, or, if that mode is not supported in
the hardware, it will be placed into hardware-supervised idle.
This patch is an equal collaboration with Jon Hunter
<jon-hunter@ti.com>. Ming Lei <ming.lei@canonical.com>, Will Deacon
<will.deacon@arm.com>, Madhav Vij <mvij@ti.com>, Kevin Hilman
<khilman@ti.com>, Benoît Cousson <b-cousson@ti.com>, and Santosh
Shilimkar <santosh.shilimkar@ti.com> all made essential contributions
to the understanding of EMU clockdomain power management on OMAP.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Jon Hunter <jon-hunter@ti.com>
Cc: Ming Lei <ming.lei@canonical.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Madhav Vij <mvij@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Jon Hunter <jon-hunter@ti.com>
2012-09-23 16:28:28 -07:00
|
|
|
.flags = (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_FORCE_WAKEUP |
|
|
|
|
|
CLKDM_MISSING_IDLE_REPORTING),
|
2010-01-26 20:12:54 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct clockdomain l3_dma_44xx_clkdm = {
|
|
|
|
|
.name = "l3_dma_clkdm",
|
|
|
|
|
.pwrdm = { .name = "core_pwrdm" },
|
2010-12-21 21:05:15 -07:00
|
|
|
.prcm_partition = OMAP4430_CM2_PARTITION,
|
|
|
|
|
.cm_inst = OMAP4430_CM2_CORE_INST,
|
|
|
|
|
.clkdm_offs = OMAP4430_CM2_CORE_SDMA_CDOFFS,
|
2011-02-25 15:48:13 -07:00
|
|
|
.wkdep_srcs = l3_dma_wkup_sleep_deps,
|
|
|
|
|
.sleepdep_srcs = l3_dma_wkup_sleep_deps,
|
2010-01-26 20:12:54 -07:00
|
|
|
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
|
|
|
|
|
};
|
|
|
|
|
|
2011-07-09 18:15:06 -07:00
|
|
|
/* As clockdomains are added or removed above, this list must also be changed */
|
2010-12-21 20:01:20 -07:00
|
|
|
static struct clockdomain *clockdomains_omap44xx[] __initdata = {
|
|
|
|
|
&l4_cefuse_44xx_clkdm,
|
|
|
|
|
&l4_cfg_44xx_clkdm,
|
|
|
|
|
&tesla_44xx_clkdm,
|
|
|
|
|
&l3_gfx_44xx_clkdm,
|
|
|
|
|
&ivahd_44xx_clkdm,
|
|
|
|
|
&l4_secure_44xx_clkdm,
|
|
|
|
|
&l4_per_44xx_clkdm,
|
|
|
|
|
&abe_44xx_clkdm,
|
|
|
|
|
&l3_instr_44xx_clkdm,
|
|
|
|
|
&l3_init_44xx_clkdm,
|
2011-07-09 18:15:06 -07:00
|
|
|
&d2d_44xx_clkdm,
|
2010-12-21 20:01:20 -07:00
|
|
|
&mpu0_44xx_clkdm,
|
|
|
|
|
&mpu1_44xx_clkdm,
|
|
|
|
|
&l3_emif_44xx_clkdm,
|
|
|
|
|
&l4_ao_44xx_clkdm,
|
|
|
|
|
&ducati_44xx_clkdm,
|
2011-07-09 18:15:06 -07:00
|
|
|
&mpu_44xx_clkdm,
|
2010-12-21 20:01:20 -07:00
|
|
|
&l3_2_44xx_clkdm,
|
|
|
|
|
&l3_1_44xx_clkdm,
|
|
|
|
|
&iss_44xx_clkdm,
|
|
|
|
|
&l3_dss_44xx_clkdm,
|
|
|
|
|
&l4_wkup_44xx_clkdm,
|
|
|
|
|
&emu_sys_44xx_clkdm,
|
|
|
|
|
&l3_dma_44xx_clkdm,
|
2011-07-09 18:15:06 -07:00
|
|
|
NULL
|
2010-12-21 20:01:20 -07:00
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};
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2010-01-26 20:12:54 -07:00
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2011-09-14 15:01:20 -07:00
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2010-12-21 20:01:20 -07:00
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void __init omap44xx_clockdomains_init(void)
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{
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2011-09-14 15:01:20 -07:00
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clkdm_register_platform_funcs(&omap4_clkdm_operations);
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clkdm_register_clkdms(clockdomains_omap44xx);
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clkdm_complete_init();
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2010-12-21 20:01:20 -07:00
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}
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