2020-08-17 05:42:51 -07:00
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SiFive Core Local Interruptor
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maintainers:
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- Palmer Dabbelt <palmer@dabbelt.com>
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- Anup Patel <anup.patel@wdc.com>
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description:
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SiFive (and other RISC-V) SOCs include an implementation of the SiFive
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Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
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interrupts. It directly connects to the timer and inter-processor interrupt
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lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
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interrupt controller is the parent interrupt controller for CLINT device.
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The clock frequency of CLINT is specified via "timebase-frequency" DT
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property of "/cpus" DT node. The "timebase-frequency" DT property is
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described in Documentation/devicetree/bindings/riscv/cpus.yaml
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2023-02-02 00:28:14 -07:00
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T-Head C906/C910 CPU cores include an implementation of CLINT too, however
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their implementation lacks a memory-mapped MTIME register, thus not
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compatible with SiFive ones.
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2020-08-17 05:42:51 -07:00
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properties:
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compatible:
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dt-bindings: timer: sifive,clint: add legacy riscv compatible
While "real" hardware might not use the compatible string "riscv,clint0"
it is present in the driver & QEMU uses it for automatically generated
virt machine dtbs. To avoid dt-validate problems with QEMU produced
dtbs, such as the following, add it to the binding.
riscv-virt.dtb: clint@2000000: compatible:0: 'sifive,clint0' is not one of ['sifive,fu540-c000-clint', 'starfive,jh7100-clint', 'canaan,k210-clint']
Reported-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20220823183319.3314940-2-mail@conchuod.ie
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-08-23 11:33:17 -07:00
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oneOf:
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- items:
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- enum:
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2023-05-10 06:27:24 -07:00
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- canaan,k210-clint # Canaan Kendryte K210
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- sifive,fu540-c000-clint # SiFive FU540
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- starfive,jh7100-clint # StarFive JH7100
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- starfive,jh7110-clint # StarFive JH7110
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2023-12-01 05:14:07 -07:00
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- starfive,jh8100-clint # StarFive JH8100
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2023-05-10 06:27:24 -07:00
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- const: sifive,clint0 # SiFive CLINT v0 IP block
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2023-02-02 00:28:14 -07:00
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- items:
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- enum:
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- allwinner,sun20i-d1-clint
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2023-10-06 05:14:46 -07:00
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- sophgo,cv1800b-clint
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2023-10-18 16:18:49 -07:00
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- sophgo,cv1812h-clint
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2024-07-09 03:07:17 -07:00
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- sophgo,sg2002-clint
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2023-06-17 09:15:23 -07:00
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- thead,th1520-clint
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2023-02-02 00:28:14 -07:00
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- const: thead,c900-clint
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dt-bindings: timer: sifive,clint: add legacy riscv compatible
While "real" hardware might not use the compatible string "riscv,clint0"
it is present in the driver & QEMU uses it for automatically generated
virt machine dtbs. To avoid dt-validate problems with QEMU produced
dtbs, such as the following, add it to the binding.
riscv-virt.dtb: clint@2000000: compatible:0: 'sifive,clint0' is not one of ['sifive,fu540-c000-clint', 'starfive,jh7100-clint', 'canaan,k210-clint']
Reported-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20220823183319.3314940-2-mail@conchuod.ie
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-08-23 11:33:17 -07:00
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- items:
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- const: sifive,clint0
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- const: riscv,clint0
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deprecated: true
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description: For the QEMU virt machine only
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2020-08-17 05:42:51 -07:00
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description:
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2023-05-10 06:27:24 -07:00
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Should be "<vendor>,<chip>-clint", followed by "sifive,clint<version>"
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when compatible with a SiFive CLINT. Please refer to
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sifive-blocks-ip-versioning.txt for details regarding the latter.
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2020-08-17 05:42:51 -07:00
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reg:
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maxItems: 1
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interrupts-extended:
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minItems: 1
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2022-01-28 02:07:35 -07:00
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maxItems: 4095
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2020-08-17 05:42:51 -07:00
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additionalProperties: false
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required:
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- compatible
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- reg
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- interrupts-extended
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examples:
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- |
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timer@2000000 {
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compatible = "sifive,fu540-c000-clint", "sifive,clint0";
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2022-01-28 02:07:36 -07:00
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interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>,
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<&cpu2intc 3>, <&cpu2intc 7>,
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<&cpu3intc 3>, <&cpu3intc 7>,
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<&cpu4intc 3>, <&cpu4intc 7>;
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2020-08-17 05:42:51 -07:00
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reg = <0x2000000 0x10000>;
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};
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...
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