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dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoC Add YAML DT binding documentation for the Microchip PolarFire SoC. It is documented at: https://www.microsemi.com/products/fpga-soc/polarfire-soc-icicle-quick-start-guide Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-03-03 13:02:50 -07:00
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/riscv/microchip.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
dt-bindings: Remove 'Device Tree Bindings' from end of title: As indicated in link: https://lore.kernel.org/all/20220822204945.GA808626-robh@kernel.org/ DT schema files should not have 'Device Tree Binding' as part of there title: line. Remove this in most .yaml files, so hopefully preventing developers copying it into new .yaml files, and being asked to remove it. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20220825020427.3460650-1-andrew@lunn.ch Signed-off-by: Rob Herring <robh@kernel.org>
2022-08-24 19:04:27 -07:00
title: Microchip PolarFire SoC-based boards
dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoC Add YAML DT binding documentation for the Microchip PolarFire SoC. It is documented at: https://www.microsemi.com/products/fpga-soc/polarfire-soc-icicle-quick-start-guide Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-03-03 13:02:50 -07:00
maintainers:
dt-bindings: riscv: update microchip.yaml's maintainership Daire and I are the platform maintainers for Microchip's RISC-V FPGAs. Update the maintainers in microchip.yaml to reflect this and explicitly add the binding to the SoC's MAINTAINERS entry. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20221010221704.2161221-3-conor@kernel.org/ Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-10-10 15:17:05 -07:00
- Conor Dooley <conor.dooley@microchip.com>
- Daire McNamara <daire.mcnamara@microchip.com>
dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoC Add YAML DT binding documentation for the Microchip PolarFire SoC. It is documented at: https://www.microsemi.com/products/fpga-soc/polarfire-soc-icicle-quick-start-guide Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-03-03 13:02:50 -07:00
description:
Microchip PolarFire SoC-based boards
properties:
$nodename:
const: '/'
compatible:
dt-bindings: riscv: microchip: document icicle reference design The icicle kit reference design's v2022.09 release made some changes to the memory map - including adding the ability to read the fabric clock controllers via the system controller bus & making the PCI controller work with upstream Linux. While the PCI was not working in the v2022.03 design, so nothing is broken there in terms of backwards compatibility, the fabric clocks used in the v2022.03 design were chosen by the individual run of the synthesis tool. In the v2022.09 reference design, the clocks are fixed to use the "north west" fabric Clock Conditioning Circuitry. In the v2022.10 release, the memory map on the DDR side is also changing, so to avoid making a breaking change here twice, jump over the v2022.09 release and straight to the v2022.10 one. Make use of a new compatible to denote that v2022.{09,10} reference design releases are not backwards compatible. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-09-27 04:19:13 -07:00
oneOf:
- items:
- enum:
- microchip,mpfs-icicle-reference-rtlv2203
- microchip,mpfs-icicle-reference-rtlv2210
- const: microchip,mpfs-icicle-kit
- const: microchip,mpfs
- items:
- enum:
dt-bindings: riscv: microchip: document the Aldec TySoM The TySOM-M-MPFS250 is a compact SoC prototyping board featuring a Microchip PolarFire SoC MPFS250T-FCG1152. Document rev2 of this board. Link: https://www.aldec.com/en/products/emulation/tysom_boards/polarfire_microchip/tysom_m_mpfs250 Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-01-11 05:41:06 -07:00
- aldec,tysom-m-mpfs250t-rev2
dt-bindings: riscv: microchip: document the aries m100pfsevp Add a compatible for the Aries Embedded M100PFSEVP SOM + EVK platform. Link: https://www.aries-embedded.com/polarfire-soc-fpga-microsemi-m100pfs-som-mpfs025t-pcie-serdes Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Rob Herring <robh@kernel.org>
2022-09-27 04:19:14 -07:00
- aries,m100pfsevp
dt-bindings: riscv: microchip: document beaglev-fire The BeagleV Fire is a BeagleBone Black form-factor board with a PolarFire SoC. Link: https://www.beagleboard.org/boards/beaglev-fire Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-03-27 05:24:36 -07:00
- beagle,beaglev-fire
dt-bindings: riscv: microchip: document the sev kit Update devicetree bindings document with PolarFire SoC Video Kit, known by its "sev-kit" product code. Link: https://onlinedocs.microchip.com/pr/GUID-404D3738-DC76-46BA-8683-6A77E837C2DD-en-US-1/index.html?GUID-065AEBEE-7B2C-4895-8579-B1D73D797F06 Signed-off-by: Shravan Chippa <shravan.chippa@microchip.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-09-27 04:19:15 -07:00
- microchip,mpfs-sev-kit
dt-bindings: riscv: microchip: document icicle reference design The icicle kit reference design's v2022.09 release made some changes to the memory map - including adding the ability to read the fabric clock controllers via the system controller bus & making the PCI controller work with upstream Linux. While the PCI was not working in the v2022.03 design, so nothing is broken there in terms of backwards compatibility, the fabric clocks used in the v2022.03 design were chosen by the individual run of the synthesis tool. In the v2022.09 reference design, the clocks are fixed to use the "north west" fabric Clock Conditioning Circuitry. In the v2022.10 release, the memory map on the DDR side is also changing, so to avoid making a breaking change here twice, jump over the v2022.09 release and straight to the v2022.10 one. Make use of a new compatible to denote that v2022.{09,10} reference design releases are not backwards compatible. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-09-27 04:19:13 -07:00
- sundance,polarberry
- const: microchip,mpfs
dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoC Add YAML DT binding documentation for the Microchip PolarFire SoC. It is documented at: https://www.microsemi.com/products/fpga-soc/polarfire-soc-icicle-quick-start-guide Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-03-03 13:02:50 -07:00
additionalProperties: true
...
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