64 lines
1.3 KiB
YAML
64 lines
1.3 KiB
YAML
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||
|
|
%YAML 1.2
|
||
|
|
---
|
||
|
|
$id: http://devicetree.org/schemas/clock/qcom,sm4450-camcc.yaml#
|
||
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||
|
|
|
||
|
|
title: Qualcomm Camera Clock & Reset Controller on SM4450
|
||
|
|
|
||
|
|
maintainers:
|
||
|
|
- Ajit Pandey <quic_ajipan@quicinc.com>
|
||
|
|
- Taniya Das <quic_tdas@quicinc.com>
|
||
|
|
|
||
|
|
description: |
|
||
|
|
Qualcomm camera clock control module provides the clocks, resets and power
|
||
|
|
domains on SM4450
|
||
|
|
|
||
|
|
See also:: include/dt-bindings/clock/qcom,sm4450-camcc.h
|
||
|
|
|
||
|
|
properties:
|
||
|
|
compatible:
|
||
|
|
const: qcom,sm4450-camcc
|
||
|
|
|
||
|
|
reg:
|
||
|
|
maxItems: 1
|
||
|
|
|
||
|
|
clocks:
|
||
|
|
items:
|
||
|
|
- description: Board XO source
|
||
|
|
- description: Camera AHB clock source from GCC
|
||
|
|
|
||
|
|
'#clock-cells':
|
||
|
|
const: 1
|
||
|
|
|
||
|
|
'#reset-cells':
|
||
|
|
const: 1
|
||
|
|
|
||
|
|
'#power-domain-cells':
|
||
|
|
const: 1
|
||
|
|
|
||
|
|
required:
|
||
|
|
- compatible
|
||
|
|
- reg
|
||
|
|
- clocks
|
||
|
|
- '#clock-cells'
|
||
|
|
- '#reset-cells'
|
||
|
|
- '#power-domain-cells'
|
||
|
|
|
||
|
|
additionalProperties: false
|
||
|
|
|
||
|
|
examples:
|
||
|
|
- |
|
||
|
|
#include <dt-bindings/clock/qcom,rpmh.h>
|
||
|
|
#include <dt-bindings/clock/qcom,sm4450-gcc.h>
|
||
|
|
clock-controller@ade0000 {
|
||
|
|
compatible = "qcom,sm4450-camcc";
|
||
|
|
reg = <0x0ade0000 0x20000>;
|
||
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||
|
|
<&gcc GCC_CAMERA_AHB_CLK>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
#reset-cells = <1>;
|
||
|
|
#power-domain-cells = <1>;
|
||
|
|
};
|
||
|
|
...
|