87 lines
2.2 KiB
YAML
87 lines
2.2 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,qca8k-nsscc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm NSS Clock & Reset Controller on QCA8386/QCA8084
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Luo Jie <quic_luoj@quicinc.com>
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description: |
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Qualcomm NSS clock control module provides the clocks and resets
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on QCA8386(switch mode)/QCA8084(PHY mode)
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See also::
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include/dt-bindings/clock/qcom,qca8k-nsscc.h
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include/dt-bindings/reset/qcom,qca8k-nsscc.h
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properties:
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compatible:
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oneOf:
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- const: qcom,qca8084-nsscc
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- items:
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- enum:
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- qcom,qca8082-nsscc
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- qcom,qca8085-nsscc
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- qcom,qca8384-nsscc
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- qcom,qca8385-nsscc
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- qcom,qca8386-nsscc
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- const: qcom,qca8084-nsscc
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clocks:
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items:
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- description: Chip reference clock source
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- description: UNIPHY0 RX 312P5M/125M clock source
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- description: UNIPHY0 TX 312P5M/125M clock source
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- description: UNIPHY1 RX 312P5M/125M clock source
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- description: UNIPHY1 TX 312P5M/125M clock source
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- description: UNIPHY1 RX 312P5M clock source
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- description: UNIPHY1 TX 312P5M clock source
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reg:
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items:
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- description: MDIO bus address for Clock & Reset Controller register
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reset-gpios:
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description: GPIO connected to the chip
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maxItems: 1
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required:
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- compatible
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- clocks
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- reg
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- reset-gpios
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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clock-controller@18 {
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compatible = "qcom,qca8084-nsscc";
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reg = <0x18>;
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reset-gpios = <&tlmm 51 GPIO_ACTIVE_LOW>;
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clocks = <&pcs0_pll>,
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<&qca8k_uniphy0_rx>,
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<&qca8k_uniphy0_tx>,
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<&qca8k_uniphy1_rx>,
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<&qca8k_uniphy1_tx>,
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<&qca8k_uniphy1_rx312p5m>,
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<&qca8k_uniphy1_tx312p5m>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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};
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...
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