81 lines
2.3 KiB
YAML
81 lines
2.3 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip PolarFire SoC Fabric Clock Conditioning Circuitry
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maintainers:
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- Conor Dooley <conor.dooley@microchip.com>
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description: |
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Microchip PolarFire SoC has 4 Clock Conditioning Circuitry blocks. Each of
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these blocks contains two PLLs and 2 DLLs & are located in the four corners of
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the FPGA. For more information see "PolarFire SoC FPGA Clocking Resources" at:
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https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html
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properties:
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compatible:
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const: microchip,mpfs-ccc
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reg:
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items:
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- description: PLL0's control registers
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- description: PLL1's control registers
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- description: DLL0's control registers
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- description: DLL1's control registers
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clocks:
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description:
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The CCC PLL's have two input clocks. It is required that even if the input
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clocks are identical that both are provided.
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minItems: 2
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items:
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- description: PLL0's refclk0
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- description: PLL0's refclk1
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- description: PLL1's refclk0
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- description: PLL1's refclk1
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- description: DLL0's refclk
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- description: DLL1's refclk
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clock-names:
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minItems: 2
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items:
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- const: pll0_ref0
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- const: pll0_ref1
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- const: pll1_ref0
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- const: pll1_ref1
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- const: dll0_ref
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- const: dll1_ref
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'#clock-cells':
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const: 1
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description: |
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell.
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See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
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PolarFire clock IDs.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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clock-controller@38100000 {
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compatible = "microchip,mpfs-ccc";
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reg = <0x38010000 0x1000>, <0x38020000 0x1000>,
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<0x39010000 0x1000>, <0x39020000 0x1000>;
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#clock-cells = <1>;
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clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
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<&refclk_ccc>, <&refclk_ccc>;
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clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
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"dll0_ref", "dll1_ref";
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};
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