67 lines
1.5 KiB
YAML
67 lines
1.5 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/mediatek,mt6795-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek Functional Clock Controller for MT6795
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maintainers:
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- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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- Chun-Jie Chen <chun-jie.chen@mediatek.com>
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description: |
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The clock architecture in MediaTek like below
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PLLs -->
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dividers -->
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muxes
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-->
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clock gate
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The devices provide clock gate control in different IP blocks.
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properties:
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compatible:
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enum:
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- mediatek,mt6795-mfgcfg
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- mediatek,mt6795-vdecsys
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- mediatek,mt6795-vencsys
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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required:
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- compatible
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- reg
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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mfgcfg: clock-controller@13000000 {
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compatible = "mediatek,mt6795-mfgcfg";
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reg = <0 0x13000000 0 0x1000>;
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#clock-cells = <1>;
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};
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vdecsys: clock-controller@16000000 {
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compatible = "mediatek,mt6795-vdecsys";
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reg = <0 0x16000000 0 0x1000>;
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#clock-cells = <1>;
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};
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vencsys: clock-controller@18000000 {
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compatible = "mediatek,mt6795-vencsys";
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reg = <0 0x18000000 0 0x1000>;
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#clock-cells = <1>;
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};
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};
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