2019-12-19 02:07:10 -07:00
|
|
|
# SPDX-License-Identifier: GPL-2.0
|
|
|
|
%YAML 1.2
|
|
|
|
---
|
|
|
|
$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-apb0-clk.yaml#
|
|
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
|
2022-08-24 19:04:27 -07:00
|
|
|
title: Allwinner A80 APB0 Bus Clock
|
2019-12-19 02:07:10 -07:00
|
|
|
|
|
|
|
maintainers:
|
|
|
|
- Chen-Yu Tsai <wens@csie.org>
|
|
|
|
- Maxime Ripard <mripard@kernel.org>
|
|
|
|
|
|
|
|
deprecated: true
|
|
|
|
|
|
|
|
properties:
|
|
|
|
"#clock-cells":
|
|
|
|
const: 0
|
|
|
|
|
|
|
|
compatible:
|
|
|
|
enum:
|
|
|
|
- allwinner,sun9i-a80-apb0-clk
|
|
|
|
- allwinner,sun9i-a80-apb1-clk
|
|
|
|
|
|
|
|
reg:
|
|
|
|
maxItems: 1
|
|
|
|
|
|
|
|
clocks:
|
|
|
|
maxItems: 2
|
|
|
|
description: >
|
|
|
|
The parent order must match the hardware programming order.
|
|
|
|
|
|
|
|
clock-output-names:
|
|
|
|
maxItems: 1
|
|
|
|
|
|
|
|
required:
|
|
|
|
- "#clock-cells"
|
|
|
|
- compatible
|
|
|
|
- reg
|
|
|
|
- clocks
|
|
|
|
- clock-output-names
|
|
|
|
|
|
|
|
additionalProperties: false
|
|
|
|
|
|
|
|
examples:
|
|
|
|
- |
|
|
|
|
clk@6000070 {
|
|
|
|
#clock-cells = <0>;
|
|
|
|
compatible = "allwinner,sun9i-a80-apb0-clk";
|
|
|
|
reg = <0x06000070 0x4>;
|
|
|
|
clocks = <&osc24M>, <&pll4>;
|
|
|
|
clock-output-names = "apb0";
|
|
|
|
};
|
|
|
|
|
|
|
|
- |
|
|
|
|
clk@6000074 {
|
|
|
|
#clock-cells = <0>;
|
|
|
|
compatible = "allwinner,sun9i-a80-apb1-clk";
|
|
|
|
reg = <0x06000074 0x4>;
|
|
|
|
clocks = <&osc24M>, <&pll4>;
|
|
|
|
clock-output-names = "apb1";
|
|
|
|
};
|
|
|
|
|
|
|
|
...
|