2022-07-28 14:07:15 -07:00
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.. SPDX-License-Identifier: GPL-2.0
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RISC-V Linux User ABI
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=====================
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2022-12-05 07:45:26 -07:00
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ISA string ordering in /proc/cpuinfo
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------------------------------------
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The canonical order of ISA extension names in the ISA string is defined in
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chapter 27 of the unprivileged specification.
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The specification uses vague wording, such as should, when it comes to ordering,
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so for our purposes the following rules apply:
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#. Single-letter extensions come first, in canonical order.
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The canonical order is "IMAFDQLCBKJTPVH".
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#. All multi-letter extensions will be separated from other extensions by an
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underscore.
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#. Additional standard extensions (starting with 'Z') will be sorted after
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single-letter extensions and before any higher-privileged extensions.
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#. For additional standard extensions, the first letter following the 'Z'
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2023-01-29 16:57:01 -07:00
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conventionally indicates the most closely related alphabetical
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extension category. If multiple 'Z' extensions are named, they will be
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ordered first by category, in canonical order, as listed above, then
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alphabetically within a category.
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2022-12-05 07:45:26 -07:00
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#. Standard supervisor-level extensions (starting with 'S') will be listed
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after standard unprivileged extensions. If multiple supervisor-level
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extensions are listed, they will be ordered alphabetically.
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#. Standard machine-level extensions (starting with 'Zxm') will be listed
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after any lower-privileged, standard extensions. If multiple machine-level
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extensions are listed, they will be ordered alphabetically.
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#. Non-standard extensions (starting with 'X') will be listed after all standard
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extensions. If multiple non-standard extensions are listed, they will be
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ordered alphabetically.
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An example string following the order is::
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rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux
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RISC-V: Show accurate per-hart isa in /proc/cpuinfo
In /proc/cpuinfo, most of the information we show for each processor is
specific to that hart: marchid, mvendorid, mimpid, processor, hart,
compatible, and the mmu size. But the ISA string gets filtered through a
lowest common denominator mask, so that if one CPU is missing an ISA
extension, no CPUs will show it.
Now that we track the ISA extensions for each hart, let's report ISA
extension info accurately per-hart in /proc/cpuinfo. We cannot change
the "isa:" line, as usermode may be relying on that line to show only
the common set of extensions supported across all harts. Add a new "hart
isa" line instead, which reports the true set of extensions for that
hart.
Signed-off-by: Evan Green <evan@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20231106232439.3176268-1-evan@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-11-06 16:24:39 -07:00
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"isa" and "hart isa" lines in /proc/cpuinfo
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-------------------------------------------
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The "isa" line in /proc/cpuinfo describes the lowest common denominator of
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RISC-V ISA extensions recognized by the kernel and implemented on all harts. The
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"hart isa" line, in contrast, describes the set of extensions recognized by the
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kernel on the particular hart being described, even if those extensions may not
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be present on all harts in the system.
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In both lines, the presence of an extension guarantees only that the hardware
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has the described capability. Additional kernel support or policy changes may be
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required before an extension's capability is fully usable by userspace programs.
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Similarly, for S-mode extensions, presence in one of these lines does not
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guarantee that the kernel is taking advantage of the extension, or that the
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feature will be visible in guest VMs managed by this kernel.
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Inversely, the absence of an extension in these lines does not necessarily mean
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the hardware does not support that feature. The running kernel may not recognize
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the extension, or may have deliberately removed it from the listing.
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2022-12-05 07:45:26 -07:00
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Misaligned accesses
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-------------------
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2024-05-24 11:56:00 -07:00
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Misaligned scalar accesses are supported in userspace, but they may perform
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poorly. Misaligned vector accesses are only supported if the Zicclsm extension
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is supported.
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